A Novel Design Methodology for High-Performance Programmable Decoder Cores for AA-LDPC Codes

Abstract

A new parameterized-core-based design methodology targeted for programmable decoders for low-density parity-check (LDPC) codes is proposed. The methodology solves the two major drawbacks of excessive memory overhead and complex on-chip interconnects typical of existing decoder implementations and which limit the scalability, degrade the error-correction capability, and restrict the domain of application of LDPC codes. Diverse memory and interconnect optimizations are performed at the code-design, decoding algorithm, decoder architecture, and physical layout levels, with the following features: (1) architecture-aware (AA)-LDPC code design with embedded structural features that significantly reduce interconnect complexity; (2) faster and memory-efficient turbo-decoding algorithm for LDPC codes; (3) programmable architecture having distributed memory, parallel message processing units, and dynamic/scalable transport networks for routing messages; (4) a parameterized macro-cell layout library implementing the main components of the architecture with scaling parameters that enable low-level transistor sizing and power-rail scaling for power-delay-area optimization. A 14 mm/sup 2/ programmable decoder core for a rate- 1/2 , length 2048 AA-LDPC code generated using the proposed methodology is presented; it delivers a throughput of 1.6 Gbps at 125 MHz and consumes 760 mW of power.