Programmable Clock Research Articles

Performance and measurement of power quality due to harmonics from street lighting networks

The municipality government of San Miguel de Tucumán city in Argentina is interested in applying energy saving policies to street lighting facilities. In this frame, devices like astronomical programmable clocks and electronic control gear (ballast) will be used to replace photocells and inductive control gear. Also luminaries in use could be replaced by more efficient ones. A technical-economical evaluation was necessary and the technical aspect was request to the Lighting Department of Tucumán University. The performance of the devices and the power quality impact in the lighting networks evaluation was also necessary to evaluate. The study carried out involved outdoor and laboratory test. During 1,5 month six lighting networks with 273 semi-cutoff luminaires were tested. Network selected belong to residential areas which represent more than 60% of total city lighting facilities (26.000 luminaires). In addition laboratory test were conducted with a sample of inductive (in use) and electronic control gear, for high pressure sodium discharge lamps (HPS) 150W. Performance varying voltage input for aged was analyze. Some results from tests points out that: • The use of programmable astronomical clocks instead of photocell produces 11% of energy saving because of actual time on and off schedule set. • Electronic control gear instead of inductive control gear produces 28% energy saving. • Luminaire replacement of current HPS 150W by HPS 100W with Electronic control gear and photocell control produces 43% in energy saving. Outdoor test results from measurement of electrical input parameters and harmonics of existing inductive control gear in street lighting, indicate that: while THD V voltage is about 2,8%, THD A current can be reduced from 38% to 6,5% even when electronic control gear is set to the lower output power step (70% of power output and 60% of initial average illuminance value). The results obtained will be used as arguments for the widespread replacement in the city which would involve considerable investment and a new experience in the region.

A generation and distribution system of clock signal source for signal acquisition system

AbstractThe clock signal is the heartbeat of modern electronic system, and demands of increasing high‐quality signal has been raised, with the development of science and technology in the field of electronic information. The clock signal with low jitter is helpful to improve the signal‐to‐noise ratio (SNR) of sampled data and obtain high‐precision result. In this article, a programmable clock system of signal generation and distribution is designed for high‐speed acquisition system. The system can provide the clock of low jitter which frequency is as high as 3.2 GHz. The output channels for clock are 14 and each channel for clock can also be configured for synchronizing, delay adjusting or calibrating. Based on the system, a new type of configuration program is developed by using Verilog language. It can directly control the chip which has better compatibility in the application scenario of Field Programmable Gate Array (FPGA) as the master chip. It also provides a reference and guidance for the design and implementation of the dual‐Phase Locked Loop clock chips. When it provides the clocks for the high‐speed acquisition system, the SNR of the acquisition signal has been significantly improved compared with similar acquisition systems. It indicates that the clock system we designed provides an effective way for the high‐speed acquisition system to obtain the data with higher SNR.

Design of wireless audio transmission system for college English language teaching

In the past, the use of wireless microphone was affected by overload noise, resulting in incomplete transmission of teaching content. In order to solve this problem, a wireless audio transmission system design for College English language teaching is proposed. The overall architecture of SEP6010 wireless voice system is designed, which is output by PWM channel to complete voice playback. UDA1341TS low-power stereo analog-to-digital converter is used to control audio transmission. The voice circuit is designed by adding clock signal or internal programmable clock. The A/D conversion module is used to amplify the collected signal, and the original voice signal is restored through the audio playback module. MATLAB is used to simulate the process of encoding, decoding and filtering. According to CVSD quantization integral coding algorithm, the quantization noise is reduced to a given allowable value. Start Audacity software to complete wireless audio transmission. The experimental results show that the highest transmission teaching content integrity of the system under single frequency input is 98%, and the highest transmission teaching content integrity under mixing input is 93%.

Design and implementation of programmable logic array using crossbar structure in quantum‐dot cellular automata

AbstractQuantum‐dot cellular automata (QCA) is a promising nanoelectronic technology having the characteristics of stable operation, breakneck speed, and ultralow energy consumption in theory. However, no scalable and modular architecture can facilitate circuit implementation, restricting the overall development of this technology. Different from the traditional programmable logic array (PLA) using AND‐OR arrays, this paper proposes a design method of PLA using crossbar structure in QCA. The PLA consists of multiple programmable units in which the majority gates can be programmed as AND/OR gates, and an inverter following each majority gate will invert the output as needed. To flexibly adjust the logic states of each programmable unit, a programmable clock scheme and N‐bit latch are then proposed. Therefore, a circuit can arbitrarily be achieved by programming the PLA. Four circuits, including full adder, 2–1 MUX, D flip‐flop, and 1‐bit memory, are designed, implemented, and simulated in QCA, by using this PLA. Experimental results show that the designed circuits realize logic functions correctly and stably.

Characterization and Differentiation between Olive Varieties through Electrical Impedance Spectroscopy, Neural Networks and IoT.

Electrical impedance has shown itself to be useful in measuring the properties and characteristics of agri-food products: fruit quality, moisture content, the germination capacity in seeds or the frost-resistance of fruit. In the case of olives, it has been used to determine fat content and optimal harvest time. In this paper, a system based on the System on Chip (SoC) AD5933 running a 1024-point discrete Fourier transform (DFT) to return the impedance value as a magnitude and phase and which, working together with two ADG706 analog multiplexers and an external programmable clock based on a synthesized DDS in a FPGA XC3S250E-4VQG100C, allows for the impedance measurement in agri-food products with a frequency sweep from 1 Hz to 100 kHz. This paper demonstrates how electrical impedance is affected by the temperature both in freshly picked olives and in those processed in brine and provides a way to characterize cultivars by making use of only the electrical impedance, neural networks (NN) and the Internet of Things (IoT), allowing information to be collected from the olive samples analyzed both on farms and in factories.

1.28 and 5.12 Gbps multi-channel twinax cable receiver ASICs for the ATLAS Inner Tracker Pixel Detector upgrade

We present two prototypes of a gigabit transceiver ASIC, GBCR1 and GBCR2, both designed in a 65-nm CMOS technology for the ATLAS Inner Tracker Pixel Detector readout upgrade.The first prototype, GBCR1, has four upstream receiver channels and one downstream transmitter channel with pre-emphasis. Each upstream channel receives the data at 5.12 Gbps through a 5 m AWG34 Twinax cable from an ASIC driver located on the pixel module and restores the signal from the high frequency loss due to the low mass cable. The signal is retimed by a recovered clock before it is sent to the optical transmitter VTRx+. The downstream driver is designed to transmit the 2.56 Gbps signal from lpGBT to the electronics on the pixel module over the same cable. The peak–peak jitter (throughout the paper jitter is always peak–peak unless specified) of the restored signal is 35.4 ps at the output of GBCR1, and 138 ps for the downstream channel at the cable ends. GBCR1 consumes 318 mW and is tested.The second prototype, GBCR2, has seven upstream channels and two downstream channels. Each upstream channel works at 1.28 Gbps to recover the data directly from the RD53B ASIC through a 1 m custom FLEX cable followed by a 6 m AWG34 Twinax cable. The equalized signal of each upstream channel is retimed by an input 1.28 GHz phase programmable clock. Compared with the signal at the FLEX input, the additional jitter of the equalized signal is about 80 ps when the retiming logic is off. When the retiming logic is on, the jitter is 50 ps at GBCR2 output, assuming the 1.28 GHz retiming clock is from lpGBT. The downstream is designed to transmit the 160 Mbps signal from lpGBT through the same cable connection to RD53B and the jitter is about 157 ps at the cable ends. GBCR2 consumes about 150 mW when the retiming logic is off. This design was submitted in November 2019.

New technologies for smart cities – high‐resolution air pollution maps based on intelligent sensors

SummaryThis paper presents a contribution in the development of a wireless sensor network, which can be used for building, in real time, dense air pollution maps, for compact urban areas. Such system may be useful for cyclists and pedestrians moving through the city. Based on such data, they can select the route in such a way, as to avoid the most polluted areas. An important step here may be development of miniaturized and cheap intelligent sensors, capable not only of data recording and transmitting, but also of some on‐site data processing and prediction. Such sensors require a development of small and power efficient circuit, including data processing unit integrated with an artificial neural network (ANN) in a single chip. We present a prototype chip that contains main components of such sensors, which include a programmable 10‐bit analog‐to‐digital converter, a programmable clock generator, and selected blocks of the ANN. The chip is a reconfigurable device, with many testing abilities. For this reason, one of the main challenges was a fast and efficient programming and testing tool. Such tool has been developed by us and is described in this work in detail along with selected measurement results. The presented work is an extended version of our conference paper (“Novel solutions for smart cities—creating air pollution maps based on intelligent sensors”).

A time synchronization circuit with sub-microsecond skew for multi-hop wired wearable networks

This paper describes and evaluates a fully digital circuit for one-way master-to-slave, highly precise time synchronization in a low-power wearable system equipped with a set of sensor nodes. These sensors are connected to each other in a mesh topology, with conductive yarns used as one-wire bidirectional communication links. The circuit is designed to perform synchronization in the MAC layer, so that the deterministic part of the clock skew between nodes is kept constant and compensated with a single message exchange. In each sensor node, the synchronization circuit provides a programmable clock signal and a real-time counter for time stamping. Experimental results from a fabricated ASIC (in a CMOS 0.35μm technology) show that the circuit keeps the one-hop average clock skew below 4.6ns and that the skew grows linearly as the hop distance to the reference node increases. The sub-microsecond average clock skew achieved by the proposed solution satisfies the requirements of many wearable sensor network applications.

A New Fully Differential CMOS Capacitance to Digital Converter for Lab-on-Chip Applications.

In this paper, we present a new differential CMOS capacitive sensor for Lab-on-Chip applications. The proposed integrated sensor features a DC-input ΣΔ capacitance to digital converter (CDC) and two reference and sensing microelectrodes integrated on the top most metal layer in 0.35 μm CMOS process. Herein, we describe a readout circuitry with a programmable clocking strategy using a Charge Based Capacitance Measurement technique. The simulation and experimental results demonstrate a high capacitive dynamic range of 100 fF-110 fF, the sensitivity of 350 mV/fF and the minimum detectable capacitance variation of as low as 10 aF. We also demonstrate and discuss the use of this device for environmental applications through various chemical solvents.

A Versatile Timing Microsystem Based on Wafer-Level Packaged XTAL/BAW Resonators With Sub-$\mu$W RTC Mode and Programmable HF Clocks

This paper introduces and demonstrates with high yield a novel concept for the packaging under vacuum of tuning fork quartz XTALs on top of a silicon interposer equipped with TSVs. It paves the way to the implementation of a monolithic timing microsystem where the ASIC is part of the housing of a newly designed tiny 131-kHz XTAL to reach extreme module miniaturization (1.5 × 1.1 × 0.7 mm 3) and integrity. As this task is still ongoing, an early demonstration of the generic versatile timing module is presented using a chip-on-board approach with standalone conventionally packaged XTAL and BAW resonators. The module achieves 0.4 μW power dissipation and ±2 ppm stability over -40 °C to 85 °C in RTC mode and can deliver on-demand programmable clocks between 1-50 MHz. The latter are obtained either with a RC PLL or after division of the signal obtained from a 2-GHz BAW DCO at a power dissipation of 100 μW and 5.3 mW, respectively.

An IR-UWB Transmitter for Ranging Systems

This brief presents a continuous-time impulse radio ultrawideband transmitter. The transmitter is a part of a high-precision ranging single-chip transceiver that measures the time-of-flight symbol propagation. The clock burst generator in the transmitter will initiate symbol transmission in continuous time unbounded by any clock signal while maintaining an accurate chip rate during symbol transmission. Using a calibration circuit, the clock period can be programmed precisely to compensate for device mismatch. The transmitter is fabricated in Taiwan Semiconductor Manufacturing Company 90-nm CMOS technology and occupies an area of 0.123 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$ \hbox{mm}^{2}$</tex></formula> . The programmable clock range is from 12.65 to 111 MHz, and the measured rms jitter is 3.26 ps at 50 MHz. The entire transmitter has a power consumption of 1.41 mW at the data rate of 2 Mbit/s.

Unified Capture Scheme for Small Delay Defect Detection and Aging Prediction

Small delay defect (SDD) and aging-induced circuit failure are both prominent reliability concerns for nanoscale integrated circuits. Faster-than-at-speed testing is effective on SDD detection in manufacturing testing, which is always implemented by designing a suite of test signal generation circuits on the chip. Meanwhile, the integration of online aging sensors is becoming attractive in monitoring aging-induced delay degradation in the runtime. These design requirements, if implemented in separate ways, will increase the complexity of a reliable design and consume more die area. In this paper, a unified capture scheme is proposed to generate programmable clock signals for the detection of both SDDs and circuit aging. Our motivation arises from the observations that SDD detection and online aging prediction both need to capture circuit response ahead of the functional clock. The proposed aging-resistant design method enables the offline test circuit to be reused in online operations. Reversed short channel effect is also exploited to make the underlying circuit resilient to process variations. The proposed scheme is validated by intensive HSPICE simulations. Experimental results demonstrate the effectiveness in terms of low area, power, and performance overheads.

TID Effect Test of the ICS307GI-03LF Serially Programmable Clock Source for Space Applications

TID Effect Test of the ICS307GI-03LF Serially Programmable Clock Source for Space Applications

A Low Power and Wide Range Programmable Clock Generator With a High Multiplication Factor

A programmable delay locked loop (DLL) based clock generator, providing a high multiplication factor, has been developed in a 0.18- μm CMOS technology. Utilizing the proposed pulse generator, purely consisting of D flip flops (DFFs) and inverters, the clock generator provides a high multiplication factor of up to 24. It consumes only 16.2 mW when generating 2.16 GHz output signals. In addition, the proposed saturated-type unit delay cell adopted in the voltage controlled delay line (VCDL) is capable of providing a long delay while maintaining fast-switching signal edges. Thus, the DLL can lock up an input reference frequency as low as 30 MHz while maintaining good phase noise performance and small chip area occupancy. The phase noise is -88.7 and -99.8 dBc/Hz at 10 kHz and 100 kHz offsets, respectively, from the operating frequency of 1.2 GHz, which is equivalent to a 1.7 ps RMS jitter. The active chip area takes only 0.051 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

A programmable full clock rectifier and sample-and-hold amplifier for biomedical applications

Post-layout Monte Carlo analysis and characterization as function of temperature, process, and mismatch variations of a rail-to-rail full clock fully programmable differential rectifier and sample-and-hold amplifier (RSHA) for biomedical applications are presented in this paper. The RSHA is based on a class AB fully differential two-stage operational amplifier. It uses the Miller compensation capacitor to hold the output and a duplicate of the output stage to ensure proper offset cancellation and common-mode control. The circuit is designed and implemented using a 0.35 μm CMOS technology. Results show that the total harmonic distortion, for an almost rail-to-rail input swing at 10 kHz and at 100 kS/s is equivalent to more than 9 bits in worst case. The dc output offset is below 140 μV and the error introduced by the rectification with respect to the non rectified signal is less than ?100 dB. The power consumption is 3 mW with ±1.25 V supplies. The RSHA provides an output valid for more than 85% of the clock cycle.

A novel phase-coherent programmable clock for high-precision arbitrary waveform generation applied to digital ion trap mass spectrometry

Digital ion trap (DIT) mass spectrometry requires the ability to precisely and accurately produce waveforms. The quality of the mass spectra produced in terms of resolution and mass accuracy depend on the resolution and precision of the applied waveforms. This publication reveals a novel method for the production of arbitrary waveforms in general and then applies the method to the production of DIT waveforms. Arbitrary waveforms can be created by varying the clock frequency input to a programmable read only memory that is then input to a digital-to-analog converter (DAC). The arbitrary waveform is composed of a defined number of points that are triggered to be written after programmed numbers of clock cycles to define the arbitrary waveform. The novelty introduced here is that the direct digital synthesis (DDS) generated clock frequency can be precisely changed as the arbitrary waveform is written because we have developed a method to rapidly switch the DDS frequency exactly at the end of the output clock cycle allowing exact timing of multiple transitions to produce precise and temporally complex waveforms. Changing the frequency only at the end of the output clock cycle is a phase-coherent process that permits precise timing between each point in the arbitrary waveform. This waveform generation technique was demonstrated by creating a prototype that was used to operate a digital ion trap mass spectrometer. The jitter in the phase-coherent DDS TTL output that was used as the frequency-variable clock was 20 ps. This jitter represents the realizable limit of precision for waveform generation. The rectangular waveforms used to operate the mass spectrometer were created with counters that increased the arbitrary jitter to 100 ps. The mass resolution achieved was 5000 at m/ z = 414. Resolution should improve with increasing mass because the waveforms have longer periods while the jitter should remain constant. Given the current limit of the variable clock resolution, much better mass resolution should be achievable with future generations of the waveform production system. The agility of the DDS function generators permits the phase-coherent variable clock to be switched at a rate up to 250 MHz. This permits arbitrary waveforms to be produced with much more temporal complexity than previously possible.

A 70 pJ/Pulse Analog Front-End in 130 nm CMOS for UWB Impulse Radio Receivers

This paper presents an integrated ultra-low power analog front-end (AFE) architecture for UWB impulse radio receivers. The receiver is targeted towards applications like wireless sensor networks typically requiring ultra energy-efficient, low data-rate communication over a relative short range. The proposed receiver implements pulse correlation in the analog domain to severely relax the power consumption of the ADCs and digital backend. Furthermore a fully integrated prototype of the analog front-end, containing a PLL, programmable clocking generator, analog pulse correlator, a linear-in-dB variable gain amplifier and a 4-bit ADC, is demonstrated. Several design decisions and techniques, like correlation with a windowed LO instead of with a matched template, exploiting the duty-cycled nature of the system, operation in the sub-1 GHz band as well as careful circuit design are employed to reach ultra-low power consumption. The analog front-end was manufactured in 130 nm CMOS and the active circuit area measures 1000 mum times 1500 mum. A maximum channel conversion gain of 50 dB can be achieved. Two symbol rates, 39.0625 M pulses per second (Mpps) and 19.531 Mpps are supported. The AFE consumes 2.3 mA from a 1.2 V power supply when operating at 39.0625 Mpps. This corresponds to an energy consumption of 70 pJ/pulse. A wireless link over more than 10 m in an office-like environment has been demonstrated at 19.531 Mpps with a PER < 1E -3 under direct LOS conditions.

Programmable Switched Capacitor Finite Impulse Response Filter with Circular Memory Implemented in CMOS 0.18 μm Technology

This paper presents a programmable multi-mode finite impulse response (FIR) filter implemented as switched capacitor (SC) technique in CMOS 0.18 μm technology. Intended application of the described circuit is in analog base-band filtering in GSM/WCDMA systems. The proposed filter features a regular structure that allows for elimination of some parasitic capacitances, thus significantly improving the filtering accuracy. Due to its modularity that allows for dividing the circuit into two separate sections, the circuit can be easily reconfigured to work as either infinite impulse response (IIR) or as finite impulse (FIR) filter. One of the key components that allows for this multi-mode operation is the proposed programmable and ultra low power multiphase clock circuit. The 24-taps filter for the sampling frequency of 30 MHz dissipates power of 4.5 mW from a 1.8 V supply.

48.2: Display Architecture Suitable for Multiple Ambient Light‐Sensor Integration Using LTPS Technology

AbstractWe have developed a new LCD having multiple ambient light sensors (ALSs). Counters and a parallel‐to‐serial converter are formed in peripheral of the LCD panel, programmable clock drivers for the counters, and data registers to hold output of ALSs are included in a source driver LSI. The ALSs perform well in total showing nonlinear gamma property corresponding to the clock even for the case when one of the sensors is covered by a finger shadow.

Electronically tunable pulse generator with programmable pulse repetition rate for 6.0 8.5 GHz ultra‐wideband communications

AbstractAn ultra‐wideband (UWB) carrier based pulse generator with tunable carrier frequency for 6.0–8.5 GHz UWB communications compliant to European and United States indoor regulations is presented. Pulses with a pulsewidth of 2.5 ns are generated using D‐type flip‐flops and are upconverted by a frequency mixer and a tunable voltage controlled oscillator providing a carrier frequency of 6.6–7.9 GHz. For the generation of pulse trains, a pulse repetition rate of up to 333 MHz is realized using a programmable clock multiplier offering optional spread spectrum clocking to smooth the output spectrum. Suitable modulation formats are pulse position modulation and on‐off‐keying which can be easily implemented by changing baseband data. Measurement results in time domain and frequency domain are presented showing the functionality of the fabricated device and its conformity to European and US UWB regulations. © 2008 Wiley Periodicals, Inc. Microwave Opt Technol Lett 50: 1649–1651, 2008; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.23462