Approaches for solving the urgent scientific and practical problem of increasing the reliability of an onboard digital computer complex, implemented using programmable logic chips as part of the electrical circuit of such complex, are considered. In this computer complex, the specified level of reliability is achieved by means of redundancy. Therefore, the structure of the onboard digital computer is very complicated and requires special control over the switching of backup subsystems, that is, the configuration of the complex. In this article, a structure of a con-figuration control block as part of an arbitration subsystem is considered. Various approaches to the design of control devices based on programmable logic microcircuits are considered. A model of a combined microprogramming FSM (CFSM) for the implementation of the control unit is proposed. Methods for the implementation of CFSM in FPGA and ProASIC chips are studied, taking into account the general features of their internal architecture. The common thing here is that both microcircuits contain both distributed LUT resources and embedded memory blocks (EMB). FPGA chips are used in this work for experimental research and prototyping pro-jects. The experimental results, as well as the simulation of the obtained circuits on ProASIC, confirm the version that the combined FSM is advisable to use for both types of microcircuits. It is shown that the use of embedded memory blocks in the implementation of the CFSM allows, on the whole, more efficient use of the chip resources. This makes it possible to implement several devices or functional blocks on one chip, and thus improve the reliability of the entire system by reducing the number of chips used and connections between them. This is especially true for projects carried out on expensive ProASIC microcircuits with a high degree of radiation protection. This is the scientific and practical value of these studies. Promising areas of research are associated with the use of CFSM circuits on counters, as well as with the use of free triggers in distributed resources for organizing counters. This will serve for further development in the direction of efficient use of the resources of programmable logic chips