Programmable Chip Research Articles

Anisotropic quantum transport in a programmable photonic topological insulator

Quantum transport in materials describes the behavior of particles at the quantum level. Topological materials exhibit nontrivial transport properties with topological invariants, leading to the emergence of protected states that are immune against disorders at the material boundaries. In many real-world materials, especially those with anisotropic crystal structures, the transport properties can vary significantly along different directions within the material bulk. Here, we experimentally observe counterintuitive quantum transport phenomena in anisotropic topological insulators with controllable anisotropy and disorder, implemented on a programmable topological photonic chip. We examine phase transition from the topological phase to the Anderson phase, between which a new quasi-diffusive phase emerges. Anisotropic topological transport demonstrates unconventional superior robustness in the bulk mode compared to the edge mode, in the presence of disorder and loss in realistic systems. Peculiar topological transport with sophisticated gradient anisotropy, emulating stretched topological materials, occurs at the gradient domain wall that can be reconfigured. Our findings provide fresh insights into the intricate interplay between anisotropy within the bulk and robustness at the boundary of topological materials, which could lead to advancements in the field of topological material science and the development of topological devices with tailored functionalities.

Demonstration of a low-complexity real-time FBMC transmitter for a spectral-efficiency IMDD system.

Filter bank multi-carriers (FBMC) have higher spectral efficiency, lower out-of-band spectrum leakage, and stronger ability to resist synchronization errors compared to orthogonal frequency-division multiplexing (OFDM), which has been widely considered as a promising solution for short-reach applications, such as passive optical networks. However, the traditional fast Fourier transform (FFT)-based FBMC scheme has quite high implementation complexity for high-speed optical communications. In this work, we proposed a low-complexity real-time FBMC transmitter scheme enabled by a single fully parallel pruned inverse FFT and simplified short prototype filter-based polyphase networks for a low-cost intensity-modulation and direct-detection (IMDD) system. Compared to the OFDM transmitter, the proposed FBMC one occupies a similar number of look-up tables and registers but saves 21% of real multipliers, reduces latency by 16.2%, and increases the data rate by 12.5%. The real-time FBMC/OFDM signals are generated with a field programmable gate array chip and 6-bit 30-GSa/s digital-to-analog converter and are experimentally demonstrated in an IMDD system. After a 20-km standard single-mode fiber transmission, the negligible power penalty can be achieved with the proposed FBMC transmitter scheme at the bit error rate of 3.8e-3 compared to the OFDM counterpart.

MaP: Increasing node capacity of programmable cloud gateways

Virtual routing table lookup is a crucial operation in multi-tenant cloud gateways, the essential devices to enable the elastic management of Virtual Private Clouds (VPCs). However, software-based cloud gateways face performance bottlenecks when handling ever-increasing traffic. To address this challenge, a recent trend involves accelerating virtual routing table lookups using programmable switches, with Sailfish being the state-of-the-art solution. Nonetheless, Sailfish’s table scale on a single programmable switch is limited by the ASIC memory sizes. We introduce a novel scheme, named MaP (Merge and Partition), to significantly increase the memory efficiency on a single Tofino 1.0 programmable switch. MaP exploits the similarities in routing table entries across various VPCs for table compression and leverages the hardware architecture of programmable chips to minimize the memory occupancy. Performance evaluations using real-world virtual routing tables demonstrate that our approach reduces the memory cost from 25% to 47.7% compared to Sailfish, without negatively impacting the throughput and latency. With MaP, a single programmable switch can manage a massive table containing over 2 million entries for nearly 1 million VPCs, while only occupying 59.0% of memory and 63.0% of stages.

A programmable topological photonic chip

Controlling topological phases of light allows the observation of abundant topological phenomena and the development of robust photonic devices. The prospect of more sophisticated control with topological photonic devices for practical implementations requires high-level programmability. Here we demonstrate a fully programmable topological photonic chip with large-scale integration of silicon photonic nanocircuits and microresonators. Photonic artificial atoms and their interactions in our compound system can be individually addressed and controlled, allowing the arbitrary adjustment of structural parameters and geometrical configurations for the observation of dynamic topological phase transitions and diverse photonic topological insulators. Individual programming of artificial atoms on the generic chip enables the comprehensive statistical characterization of topological robustness against relatively weak disorders, and counterintuitive topological Anderson phase transitions induced by strong disorders. This generic topological photonic chip can be rapidly reprogrammed to implement multifunctionalities, providing a flexible and versatile platform for applications across fundamental science and topological technologies.

Heralded Three-Photon Entanglement from a Single-Photon Source on a Photonic Chip.

In the quest to build general-purpose photonic quantum computers, fusion-based quantum computation has risen to prominence as a promising strategy. This model allows a ballistic construction of large cluster states which are universal for quantum computation, in a scalable and loss-tolerant way without feed forward, by fusing many small n-photon entangled resource states. However, a key obstacle to this architecture lies in efficiently generating the required essential resource states on photonic chips. One such critical seed state that has not yet been achieved is the heralded three-photon Greenberger-Horne-Zeilinger (3-GHZ) state. Here, we address this elementary resource gap, by reporting the first experimental realization of a heralded 3-GHZ state. Our implementation employs a low-loss and fully programmable photonic chip that manipulates six indistinguishable single photons of wavelengths in the telecommunication regime. Conditional on the heralding detection, we obtain the desired 3-GHZ state with a fidelity 0.573±0.024. Our Letter marks an important step for the future fault-tolerant photonic quantum computing, leading to the acceleration of building a large-scale optical quantum computer.

Low-power SiPM readout BETA ASIC for space applications

The BETA application-specific integrated circuit (ASIC) is a fully programmable chip designed to amplify, shape and digitize the signal of up to 64 Silicon photomultiplier (SiPM) channels, with a power consumption of approximately ∼\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$\\sim$$\\end{document}1 mW/channel. Owing to its dual-path gain, the BETA chip is capable of resolving single photoelectrons (phes) with a signal-to-noise ratio (SNR) >5 while simultaneously achieving a dynamic range of ∼\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$\\sim$$\\end{document}4000 phes. Thus, BETA can provide a cost-effective solution for the readout of SiPMs in space missions and other applications with a maximum rate below 10 kHz. In this study, we describe the key characteristics of the BETA ASIC and present an evaluation of the performance of its 16-channel version, which is implemented using 130 nm technology. The ASIC also contains two discriminators that can provide trigger signals with a time jitter down to 400 ps FWHM for 10 phes. The linearity error of the charge gain measurement was less than 2% for a dynamic range as large as 15 bits.

Towards large-scale programmable silicon photonic chip for signal processing

Abstract Optical signal processing has been playing a crucial part as powerful engine for various information systems in the practical applications. In particular, achieving large-scale programmable chips for signal processing are highly desirable for high flexibility, low cost and powerful processing. Silicon photonics, which has been developed successfully in the past decade, provides a promising option due to its unique advantages. Here, recent progress of large-scale programmable silicon photonic chip for signal processing in microwave photonics, optical communications, optical computing, quantum photonics as well as dispersion controlling are reviewed. Particularly, we give a discussion about the realization of high-performance building-blocks, including ultra-low-loss silicon photonic waveguides, 2 × 2 Mach–Zehnder switches and microring resonator switches. The methods for configuring large-scale programmable silicon photonic chips are also discussed. The representative examples are summarized for the applications of beam steering, optical switching, optical computing, quantum photonic processing as well as optical dispersion controlling. Finally, we give an outlook for the challenges of further developing large-scale programmable silicon photonic chips.

An Approach to the State Explosion Problem: SOPC Case Study

The system on a programmable chip (SOPC) architecture is better than traditional central processing unit (CPU) + field-programmable gate array (FPGA) architecture. It forms an efficient coupling between processor software and programmable logic through an on-chip high-speed bus. The SOPC architecture is resource-rich and highly customizable. At the same time, it combines low power consumption and high performance, making it popular in the field of high reliability and other new industrial fields. The SOPC architecture system is complex and integrates multiple forms of intellectual property (IP). Because of this, the traditional dynamic test and the static test cannot meet the requirements for test depth. To solve the problem of verification depth, we should introduce formal verification. But there are some types of IP forms that formal tools cannot recognize. These include black box IP, encrypted IP, and netlist IP in the SOPC model. Also, the state space explosion caused by the huge scale of the SOPC model cannot be formally verified. In this paper, we propose a modeling method using SOPC architecture. The model solves the problem of formal tools not recognizing multi-form IPs. To compress the state space, we propose reducing SOPC variables and branch relationships based on verification properties. Then, we conduct a property verification experiment on the reduced SOPC model. The experiment result shows that the model can significantly reduce the verification time.

Programmable Gravity Self-Driven Microfluidic Chip for Point-of-Care Multiplied Immunoassays.

Point-of-care testing (POCT) is experiencing a groundbreaking transformation with microfluidic chips, which offer precise fluid control and manipulation at the microscale. Nevertheless, chip design or operation for existing platforms is rather cumbersome, with some even heavily depending on external drivers or devices, impeding their broader utilization. This study develops a unique programmable gravity self-driven microfluidic chip (PGSMC) capable of simultaneous multi-reagent sequential release, multi-target analysis, and multi-chip operation. All necessary reagents are introduced in a single step, and the process is initiated simply by flipping the PGSMC vertically, eliminating the need for additional steps or devices. Additionally, it demonstrates successful immunoassays in less than 60 min for antinuclear antibodies testing, compared to more than 120 min by traditional methods. Assessment using 25 clinically diagnosed cases showcases remarkable sensitivity (96%), specificity (100%), and accuracy (99%). These outcomes underscored its potential as a promising platform for POCT with high accuracy, speed, and reliability, highlighting its capability for automated fluid control.

Desarrollo de arquitectura SoPC para robot móvil basado en FPGA

In the context of the rapid progress in the field of mobile robotics, the need for efficient systems with high embedded processing power has emerged as a fundamental challenge. This paper addresses this issue by using FPGAs, devices underutilized in the literature for the development of architectures with H/S (hardware/software) co-design in mobile robots. The suitability of FPGAs for this purpose is highlighted, as they offer a balance between efficiency and low power consumption. The paper focuses on the implementation of a SoPC (System on Programmable Chip) based architecture designed specifically for an FPGA-based differential drive mobile robot. The most relevant aspects of the design are presented by means of diagrams illustrating the layout and interconnection of key components. The practical implementation of this architecture was carried out on a mobile robot whose processing unit is a DE0 Nano development board equipped with a Cyclone® IV FPGA. The results obtained reveal a successful behavior of the architecture in terms of interfacing with sensors, actuators, and data processing. The efficiency of the design is reflected in the balanced occupation of resources in the FPGA, highlighting the 67% of logical area still available for future implementations of modules for hardware acceleration. This paper demonstrates the feasibility and efficiency of FPGAs in the design of advanced architectures for mobile robots, providing a solid foundation for future research and development in the field of robotics.

Evolutionary Optimization of Fuzzy Reinforcement Learning and Its Application to Time-Varying Tracking Control of Industrial Parallel Robotic Manipulators

This paper contributes to the development of evolutionary optimization of fuzzy reinforcement learning and its application to time-varying tracking control for industrial parallel robotic manipulators. An improved evolutionary social spider optimization (SSO) paradigm with Cauchy mutation is presented to address the optimal fuzzy reinforcement learning problem. The SSO swarm intelligence incorporated with the fuzzy Q-learning strategy, called SSOFQ, is applied to the time-varying tracking control of parallel robotic Stewart manipulators with six degrees of freedom (DOFs). Having the derived kinematics and dynamics of six-DOF Stewart platforms, the SSOFQ is employed to synthesize an intelligent real-time tracking control scheme. More importantly, a custom experimental Stewart platform is constructed using hardware/software codesign and the system-on-a- programmable chip (SoPC) technique. Finally, the simulations, experimental results and comparative works are provided to validate the efficacy and superiority of the presented SSOFQ control method.

On-chip multifunctional self-configurable quadrilateral MZI network

Photonic integrated circuits have garnered significant attention in recent years. To enhance the functional versatility of these devices, researchers have introduced the concept of reconfiguration into photonic integrated circuits. Inspired by field programmable gate arrays in the electrical domain, programmable photonic chips employing various topologies have been developed. However, users still encounter challenges when utilizing these devices, as they need to understand the internal structure and principles of the chip and individually adjust the tunable basic units within the topology network. In this paper, we employ the quadrilateral topological network based on the on-chip Mach–Zehnder interferometer as a black box to realize a highly self-reconfigurable optical signal processor. By leveraging this approach, we achieve positive real-valued matrix computation, optical routing, and low-loss optical energy splitting. Our demonstration effectively showcases the immense potential of on-chip programmable photonic waveguide meshes.

Design and research of wireless optical power meter based on IoT big data and physical quantity

In response to the problems of low accuracy, high radiation, and high power consumption in industrial UV power detection, the author proposes a design scheme based on a low-power microcontroller MSP430 as the core controller, two UV photoelectric sensors as detectors, and wireless LoRa as the data transmission method. This scheme adopts dual sensors and achieves photoelectric conversion and ambient light filtering through a subtractive amplification circuit. It also uses high-precision programmable AD acquisition chips to achieve controllable amplification of the signal and convert analog signals into digital quantities for transmission to the main controller MSP430. The improved sliding average filtering method is used to perform digital filtering on the collected data and calculate the corresponding power value, data is transmitted to the upper computer for real-time display through wireless Lora. Research and experiments have shown that the dual sensors have a good agreement with the standard values. The difference between the measured values after digital filtering and the standard values is small, and the linearity of digital filtering is good. It can be seen from the two figures that the higher the power value, the higher the lighting temperature. It has been proven that the entire system operates stably, with high accuracy, low power consumption, and can remotely and real-time detect changes in ultraviolet light power. It can be widely used in the field of industrial ultraviolet light detection.

Optimal Design of Electromagnetic Tomography Flaw Detection System for Train Wheel Based on FPGA

Electromagnetic tomography (EMT) is a new type of nondestructive testing technology that can be used for metal flaw detection. The implementation of the signal demodulation and filtering algorithm of the current electromagnetic tomography flaw detection system relies on the microprocessor MCU, and the reliability is low in real time. To improve the reliability and system integration of signal processing and transmission of the electromagnetic tomography flaw detection system, this paper uses the field programmable gate array chip to integrate the excitation signal generation module and the digital demodulation module based on the EMT train wheel flaw detection system. A digital filter is designed, and the filter parameters are adjusted to achieve a signal-to-noise ratio of 15 dB. UDP communication protocol is utilized to realize Ethernet communication between FPGA and upper computer. Using three algorithms on the host computer for image reconstruction, the train wheel defect information is visualized. The experimental results show that the FPGA chip improves the immunity of the train wheel flaw detection system, realizes the high integration of the system, and achieves the purpose of train wheel defect detection.

Quantum generative adversarial learning in photonics.

Quantum generative adversarial networks (QGANs), an intersection of quantum computing and machine learning, have attracted widespread attention due to their potential advantages over classical analogs. However, in the current era of noisy intermediate-scale quantum (NISQ) computing, it is essential to investigate whether QGANs can perform learning tasks on near-term quantum devices usually affected by noise and even defects. In this Letter, using a programmable silicon quantum photonic chip, we experimentally demonstrate the QGAN model in photonics for the first time to our knowledge and investigate the effects of noise and defects on its performance. Our results show that QGANs can generate high-quality quantum data with a fidelity higher than 90%, even under conditions where up to half of the generator's phase shifters are damaged, or all of the generator and discriminator's phase shifters are subjected to phase noise up to 0.04π. Our work sheds light on the feasibility of implementing QGANs on the NISQ-era quantum hardware.

IRIS: An embedded secure boot for IoT devices

This study proposes a hardware secure boot solution, an instant retrieval information system (IRIS) that is suitable for integrating Internet of Things (IoT) devices. IRIS can boot a Linux kernel image pre-stores in removable media and comprises a data verifier securing the authenticity, integrity, and confidentiality of the boot process. IRIS is fully developed as a hardware module and the results reveal short boot-up times and a small hardware footprint when implemented on field programmable gate array chips. In addition, IRIS is an open-source generic solution that can be adapted to multiple architectures and includes a crypto-core called E-LUKS that can be used outside the boot-loading process to add confidentiality, integrity, and authenticity to data stored on off-chip storage like a flash device.IRIS shows a reduction in lookup tables footprint when compared to other IoT solutions consuming from 90% to 750% less resources and only slightly greater, around 30%, with solutions that only cover authentication and integrity.

Experimental quantum natural gradient optimization in photonics.

Variational quantum algorithms (VQAs) combining the advantages of parameterized quantum circuits and classical optimizers, promise practical quantum applications in the noisy intermediate-scale quantum era. The performance of VQAs heavily depends on the optimization method. Compared with gradient-free and ordinary gradient descent methods, the quantum natural gradient (QNG), which mirrors the geometric structure of the parameter space, can achieve faster convergence and avoid local minima more easily, thereby reducing the cost of circuit executions. We utilized a fully programmable photonic chip to experimentally estimate the QNG in photonics for the first time, to the best of our knowledge. We obtained the dissociation curve of the He-H+ cation and achieved chemical accuracy, verifying the outperformance of QNG optimization on a photonic device. Our work opens up a vista of utilizing QNG in photonics to implement practical near-term quantum applications.

High-Precision Dead-Time Intellectual Property Core and Its Compensation for Inverters

In the inverter circuit, there exists a specific on-off time in each power transistor. As such, to prevent a short circuit of the two switch devices on the upper and lower bridge arms, a specific dead time must be set in the pulse width modulation (PWM) and the sinusoidal pulse width modulation (SPWM) signals. In this paper, an intellectual property (IP) core that can introduce a high-precision dead time of arbitrary length into PWM or SPWM signals of the inverter is designed to increase the precision, convenience and generalization of dead time control, resulting in a boosted control accuracy of up to 10 ns. Moreover, the added Avalon bus enables IP cores to be accessed by the field programmable gate array (FPGA) processor in a standard manner and multiple IP cores of the same class can be easily incorporated. In addition, an application for setting and compensating for dead time in a three-phase inverter based on system on programmable chip (SOPC) technology is presented. With the Nios II CPU as its core, the system adopts the mean voltage compensation method to calculate the compensation voltage, and performs dead-time compensation in a feed-forward manner. The three dead-time IP cores are controlled by Avalon bus. These allow the dead time of three groups of power transistors to be accurately controlled and flexibly adjusted. The system also features the master computer communication function while boasting the advantages of flexible control, high precision and low cost.

Unequal Duty-Ratio Feedforward Control to Extend Balanced-Currents Input Voltage Range for Series-Capacitor-Based Boost PFC Converter

In this letter, the series-capacitor-based boost power factor correction (PFC) converter (or called the voltage doubler PFC converter) is studied. It possesses the voltage doubler and intrinsic current balancing characteristics only when their equal duty ratios are larger than 0.5. Thus, for PFC application, the balanced-currents input voltage should be smaller than the quarter (1/4) output dc voltage. To extend the balanced-currents input voltage range, the unequal duty-ratio feedforward control is proposed in this letter. For the case of dc output voltage 400 V, the maximum input voltage with balanced inductor currents increased from 100 V (the quarter output dc voltage) to 200 V. The proposed control method is implemented in the field programmable gate array chip to evaluate its performance.

Designing Photoelectric Sensor Module in Infrared Communication and Applying Wireless Sensor Network in Leakage Cable Detection

With technological advancement, Near-infrared (NIR) spectroscopy instruments have gradually entered people’s daily life and production with their unique performance. Therefore, it has a positive significance in researching NIR spectroscopy analysis technology. This work designs a refrigerating Lead Sulfide (PbS) NIR photoelectric sensor P2664-05 and its photoelectric signal conversion circuit. The converted voltage signal is used for subsequent circuit processing through the amplification and frequency selection circuit. The aim is to ensure the sensor’s corresponding detectable spectral wavelength, sensitivity, and signal-to-noise ratio are improved under low temperatures. To this end, the refrigeration current generation circuit is designed. The refrigerating temperature is set below −15 °C, and the refrigerating current is 500 mA. At the same time, it is necessary to monitor whether the sensor’s temperature state meets the system stability requirements during the refrigeration process. The designed sensor module is connected to the instrument system in the test, and the whiteboard without spectral absorption is scanned. The results show that the designed NIR sensor’s shortcomings in noise processing performance have been improved using a System on a Programmable Chip (SoPC) as a processor. An infrared communication node is designed using its built-in digital resources and TFDU infrared communication chip. The designed NIR sensor and communication node are added to the 485 bus to build a communication network. In leakage cable detection, the communication network has higher security, lower error rate, and lower power consumption.