Program Portability Research Articles

Parallelism Reduction Methods in the High-Level VLSI Synthesis Implementation

The problems and solutions in the field of ensuring architectural independence and implementation of digital integrated circuits end-to-end design processes are considered. The paper focuses on the need to find a solution to the problem of program portability during the development of integrated circuits. A review of the main software and tools used to design digital circuits (Verilog, System-C, Handel-C, Lava, Hydra, Wired, COLAMO, Chisel and etc.) is presented. The method and language of parallel programming for functional flow synthesis of design solutions PIFAGOR is presented. The example of the source and generated code in the PIFAGOR and Verilog languages is given. During the method implementation, the tasks of reducing parallelism and estimating the occupied resources were highlighted. The main feature of the developed method is the introduction of the additional layer (HDL graph) into the synthesis process. Algorithms for the parallelism reduction have been developed. This method is demonstrated on the example of parallelism reduction while going to the FPGA platform solving the problem of calculating a 4-point FFT (Fast Fourier Transform). As part of the solution of this task, an assessment of memory resources and an assessment of computing resources were carried out. The results of software tools development for design support including the parallelism reduction preprocessor and resource estimation preprocessor and practical VLSI projects are presented.

HDNN: a cross-platform MLIR dialect for deep neural networks

This paper presents HDNN, a proof-of-concept MLIR dialect for cross-platform computing specialized in deep neural networks. As target devices, HDNN supports CPUs, GPUs and TPUs. In this paper, we provide a comprehensive description of the HDNN dialect, outlining how this novel approach aims to solve the P^3 problem of parallel programming (portability, productivity, and performance). An HDNN program is device-agnostic, i.e., only the device specifier has to be changed to run a given workload in one device or another. Moreover, HDNN has been designed to be a domain-specific language, which ultimately helps programming productivity. Finally, HDNN relies on optimized libraries for heavy, performance-critical workloads. HDNN has been evaluated against other state-of-the-art machine learning frameworks on all the hardware platforms achieving excellent performance. We conclude that the ideas and concepts used in HDNN can be crucial for designing future generation compilers and programming languages to overcome the challenges of the forthcoming heterogeneous computing era.

Fuzzy classification of OpenCL programs targeting heterogeneous systems

Heterogeneous systems featuring multiple kinds of processors are becoming increasingly attractive due to their high performance and energy savings over their homogeneous counterparts. With the OpenCL as a unified programming language providing program portability across different types of accelerators, finding the best task-to-device mapping will be the key to achieve such a high performance. We introduce in this work the design of a fuzzy logic classifier and the evaluation of its performance in classifying OpenCL workloads in a CPU-GPU-FPGA heterogeneous environment based on carefully analyzed kernel features. The classifier is designed as part of a scheduling scheme. Results demonstrate substantial improvement in accuracy when compared to other classifiers such as the K-Nearest- Neighbor (KNN), Support-Vector-Machine (SVM), Random-Forest (RF), Naïve-Bayes (NB) and the Bayes-Network (BN) with low computational complexity, facilitating run-time operation.

Solution of radiative intensity with high directional resolution in heterogeneous participating media and irregular geometries by the null-collision reverse Monte Carlo method

Radiative intensity with high directional resolution is very useful for many inverse analyses. In this work, the null-collision algorithm is combined with the reverse Monte Carlo method to calculate radiative intensity with high directional resolution in heterogeneous participating media and irregular geometries. A convergence criterion by monitoring the standard deviation of Monte Carlo weights is proposed to determine the required number of energy bundles and to estimate the accuracy of the Null-Collision Reverse Monte Carlo (NC-RMC) method. Then, directional radiative intensity in heterogeneous participating media of three-dimensional cubic and irregular geometries is calculated. Results show that the accuracy of the NC-RMC method is well predicted by the proposed convergence criterion and very good accuracy is achieved by setting strict convergence condition. Meanwhile, with the same obtained accuracy, the NC-RMC method has better computing efficiency than the standard reverse Monte Carlo method. For the radiative system with heterogeneous participating medium and irregular geometry, the NC-RMC method shows a distinct advantage in ease of programming and program portability. Results in this work show that the NC-RMC method is a good choice to solve radiative intensity in heterogeneous media and/or radiative systems with irregular geometries, which is very useful for inverse analysis in combustion systems.

In Search of the Original Fortran Compiler

In Search of the Original Fortran Compiler Paul McJones (bio) In April 2002, Grady Booch sent out an email with the subject “Preserving classic software products.” His appeal to provide top 10 lists and to suggest where to look for the source code received an enthusiastic response. Grady and the Computer History Museum organized a workshop in October 2003.1 As a result, a month later, a group of Computer History Museum trustees, staff and volunteers (including me) established the Software Collection Committee2 (SCC) to explore the software side of the museum’s mission: “To preserve and present for posterity the artifacts and stories of the information age.” I decided to take on the project of collecting Fortran materials. John Backus’s Fortran project at IBM developed one of the first higher-level programming languages as well as a set of techniques for code optimization that allowed Fortran to compete with hand-tuned assembly language.3 The combination of ease-of-use and efficiency led to Fortran’s rapid adoption and lasting impact on programming language design and implementation. Fortran’s success on the IBM 704/709 led to Fortran compilers for many brands and models of computers, making it possible to port Fortran programs among different computers; Fortran program portability also made Fortran useful for non-numerical projects. While Fortran’s popularity waned as other languages grew up to fill various niches, some high-performance computing users continued to use Fortran, with periodic updates, to the present. The history of the Fortran project is well documented in papers by Backus and others, covering the project, its impact, and technical analysis of the compiler itself.4 However, the artifact itself—the source code for the original Fortran compiler—seemed to me an appropriate starting point to gain experience with collecting, preserving, and presenting historic software. By spring 2006, I had assembled a collection including listings, source and executable code, documentation, and more and had made the collection publicly accessible via a website. Take a look at that website now (http://www.softwarepreservation.org/projects/FORTRAN/)5 to have it mind as you read this article, which describes my collection efforts. I hope my experience will be useful to other computing history researchers from the practitioner world considering similar efforts. Getting Started I started my search for Fortran by calling John Backus, with whom I had worked in the mid-1970s (on functional programming) but had not seen for about 25 years. He did not have a copy of the source code and directed me to Irv Ziller, who had been his first hire on the project. Irv responded to my request, saying that he didn’t have the source code, but he recalled material being sent to the Smithsonian to become part of their collection. I visited the website of the Smithsonian National Museum of American History (NMAH) and located the group that had created the Computer History Collection,6 but my initial attempts to establish communication with the staff were unsuccessful.7 One day I was chatting with a coworker, Jim King, who had worked at IBM Research for many years. Jim had used Fortran II and the Fortran Monitor System on an IBM 709 in college in the early 1960s and had some interesting anecdotes.8 Jim suggested IBM’s SHARE user group library as a potentially interesting source of material, and he also recalled the extensive IBM 7094-related library at Boeing when he worked there in the 1960s. Another member of the SCC, Dick Sites, recalled having seen “handwritten Fortran I documentation in a basement of the Sloan building at MIT in 1965 .… As I remember, it described the overall compiler design and optimizing algorithms. I remember a fairly neat but slightly small handwriting with hand-drawn boxes and arrows for some of the algorithms.” Also, Len Shustek, Computer History Museum founder, pointed out this sentence in Backus’s article9 about Fortran at the first History of Programming Languages conference: “Shortly after the distribution of the system, we distributed—one copy per installation—what was fondly known as the ‘Tome,’ the complete symbolic listing of the entire compiler plus other system and diagnostic information...

Parallel viewshed analysis on a PC cluster system using triple-based irregular partition scheme

Using digital elevation models (DEMs), viewshed analysis algorithms determine the visibility of each point on the terrain at a given location in space. As a data-parallel algorithm, real-time viewshed analysis from grid DEM poses a practical challenge to personal computer (PC) users, particularly when dealing with higher resolution and accuracy of large terrain data. Therefore, this paper presents a universal domain decomposition algorithm based on an equal-area strategy for the parallel viewshed analysis on a PC cluster system. The approach uses a scan-line filling method for data partitioning of the irregular bounding polygon of the terrain. The terrain data are divided into sectors of the same area that are connected by the viewpoint and the region vertices, ignoring the null value (or NODATA) points. Furthermore, each sector is assigned to one processor and is organized in the form of triples composed of location and elevation at one point. An index of triples is built to store all of the locations of terminal vertices row-by-row and thus the random access of any point is achieved by using the offsets in each row. Two commonly applied viewshed algorithms, namely, “reference plane” and “Xdraw” algorithms are employed to verify the performance. In addition, two experiments focus on evaluating the efficiency performance and comparing traditional implementation, respectively. Experimental results demonstrate a significant performance improvement compared with the sequential computing method. The memory usage gradually decreases as the number of processors increases. Based on the equal-area decomposition, partitions in terms of sectors can guarantee a suitable load balance. Additional benefits of the proposed solution also include high storage efficiency and program portability.

The Functional Design on Fault Recorder of μC/OS-II-Based Intelligent Substation

Regarding the functional requirements for smart substation in fault recorder, this paper introduced μC / OS-II, an embedded real-time multitasking operating system as the functional design. The program works with the embedded operating system, the state machine theory and new methods for embedded development, whilst tasking full use of the advantages of such functions as task scheduling, message queues, etc., aiming to achieve a fault recorder function of intelligent substation. More than taking care of the difficulty of programming, it could improve the program reliability and portability. The program has been applied in an intelligent substation protection in centralized control unit, which has brought back a good fault recorder performance. On this basis, more functions can be integrated, including network log analysis, state estimation, etc., in order to truly meet the application requirements of the smart substations.

A New Design Method of Automotive Electronic Real-time Control System

Abstract Structure and functionality of automotive electronic control system is becoming more and more complex. The traditional manual programming development mode to realize automotive electronic control system can’t satisfy development needs. So, in order to meet diversity and speedability of development of real-time control system, combining model-based design approach and auto code generation technology, this paper proposed a new design method of automotive electronic control system based on Simulink/RTW. Fristly, design algorithms and build a control system model in Matlab/Simulink. Then generate embedded code automatically by RTW and achieve automotive real-time control system development in OSEK/VDX operating system environment. The new development mode can significantly shorten the development cycle of automotive electronic control system, improve program's portability, reusability and scalability and had certain practical value for the development of real-time control system.

From CUDA to OpenCL: Towards a performance-portable solution for multi-platform GPU programming

In this work, we evaluate OpenCL as a programming tool for developing performance-portable applications for GPGPU. While the Khronos group developed OpenCL with programming portability in mind, performance is not necessarily portable. OpenCL has required performance-impacting initializations that do not exist in other languages such as CUDA. Understanding these implications allows us to provide a single library with decent performance on a variety of platforms. We choose triangular solver (TRSM) and matrix multiplication (GEMM) as representative level 3 BLAS routines to implement in OpenCL. We profile TRSM to get the time distribution of the OpenCL runtime system. We then provide tuned GEMM kernels for both the NVIDIA Tesla C2050 and ATI Radeon 5870, the latest GPUs offered by both companies. We explore the benefits of using the texture cache, the performance ramifications of copying data into images, discrepancies in the OpenCL and CUDA compilers' optimizations, and other issues that affect the performance. Experimental results show that nearly 50% of peak performance can be obtained in GEMM on both GPUs in OpenCL. We also show that the performance of these kernels is not highly portable. Finally, we propose the use of auto-tuning to better explore these kernels' parameter space using search harness.

A Refactoring Approach to Parallelism

In the multicore era, a major programming task will be to make programs more parallel. This is tedious because it requires changing many lines of code; it's also error-prone and nontrivial because programmers need to ensure noninterference of parallel operations. Fortunately, interactive refactoring tools can help reduce the analysis and transformation burden. The author describes how refactoring tools can improve programmer productivity, program performance, and program portability. The article also describes a toolset that supports several refactorings for making programs thread-safe, threading sequential programs for throughput, and improving scalability of parallel programs.

Digital Power Amplifier of Active Magnetic Bearing

The three-level pulse width modulation(PWM)type digital power amplifier of the active magnetic bearing based on digital signal processor(DSP)and filed programmable gate array(FPGA)is developed.The DSP chip is used to replace the analog circuit to carry out proportion-integration regulation,generate triangle carrier and generate PWM wave which is the driving signal of the load winding.Through the internal program of DSP,on-line adjustment of PWM duty cycle is realized and the line of current in the load winding of active magnetic bearing is controlled in real time,thus controlling the rotor to stably suspend in the balance position.The method of using FPGA to carry out 180°phase shift of the driving signal,i.e.PWM wave,is given,thus realizing three-level digital power amplifier.This amplifier is used in the 5-DOF active magnetic bearing test bed,so that the rotor suspends statically and stably while its peak value of vibration is less than 5μm.The approach of digital design can optimize the performance of the power amplifier,moreover it will have advantages such as small volume,strong program portability and high reliability.

Parallel modal analysis with concurrent distributed objects

This paper presents a novel object-oriented implementation of component mode synthesis and mode superposition for dynamic finite element analysis. Interfaces are used extensively to maximize program maintainability and flexibility. Parallelization is achieved using ‘concurrent distributed objects’ (facilitated by Microsoft.NET) instead of the message passing approach. The methodology allows consistency in modelling and implementation; this eases program development. It also results in better program portability across memory architectures. Tests on a cluster of computers and on a shared memory multi-core machine demonstrate the effectiveness of the proposed implementation.

Chinese Rooms and Program Portability

I argue in this article that there is a mistake in Searle's Chinese room argument that has not received sufficient attention. The mistake stems from Searle's use of the Church-Turing thesis. Searle assumes that the Church-Turing thesis licences the assumption that the Chinese room can run any program. I argue that it does not, and that this assumption is false. A number of possible objections are considered and rejected. My conclusion is that it is consistent with Searle's argument to hold onto the claim that understanding consists in the running of a program.1Searle's Argument1.1The Church-Turing thesis2Criticism of Searle's Argument3Objections and Replies3.1The virtual brain machine objection3.2The brain-based objection3.3The syntax/physics objection3.4The abstraction objection3.5The ‘same conclusion’ objection3.6The ‘unnecessary baggage’ objection3.7The Chinese gym objection3.8The syntax/semantics objection3.9Turing's definition of algorithm3.9.1Consequences3.9.2Criticism of the defence4Conclusion

A System for Evaluating Performance and Cost of SIMD Array Designs

SIMD arrays are likely to become increasingly important as coprocessors in domain specific systems as architects continue to leverage RAM technology in their design. The problem this work addresses is the efficient evaluation of SIMD arrays with respect to complex applications while accounting for operating frequency and chip area. The underlying issues include the size of the architecture space, the lack of portability of the test programs, and the inherent complexity of simulating up to hundreds of thousands of processing elements. The overall method we use is to combine architecture level and Electronic Design Automation (EDA) level modeling by using an EDA-based tool to calibrate architectural simulations. The resulting system retains much of the high throughput of the architecture level simulator but it also has accuracy similar to that of an early pass EDA synthesis and circuit simulation. The particular problem of computational cost of the architectural level simulation is addressed with a novel approach to trace-based simulation (we call it trace compilation), which we find to be one to two orders of magnitude faster than instruction level simulation while still retaining much of the accuracy of the model. Furthermore, traces must be generated for only a small fraction of the possible parameter combinations. Using trace compilation also addresses program portability by allowing the user to code in a single data parallel language with a single compiler, regardless of the target architecture. We have used our system to evaluate thousands of potential SIMD array designs with respect to real applications and present some sample results.

Self-Simulation for the Passive Optical Star

Optical technology offers simple interconnection schemes with straightforward layouts that support complex logical interconnection patterns. The passive optical star (pos), in which communication takes place via optical wavelengths agreed upon between senders and receivers, is often suggested as a platform for implementing the optical network: Logically it offers an all-to-all broadcast capability. We investigate the use of pos optical technology as the communication medium for parallel computing, focusing on the scalability or self-simulation issue, which is a fundamental concern of great importance to the simplicity of algorithm design and program portability. A family of parallel machines is scalable or self-simulating if any member of the family can simulate any larger member with k times as many processors with a slowdown close to k; i.e., scalability states that if a certain efficiency is achievable on a large machine, then it is achievable on any smaller machine as well. A pos is balanced if the number of available wavelengths equals the number of processors. We show that the balanced pos is highly scalable by presenting a universal randomized simulation of a kn-processor balanced pos on an n-processor balanced pos, for arbitrary integers n,k≥1, with an expected slowdown of O(k+log*n). We also describe a deterministic simulation with a slowdown of O(min{k2,k+logn}) and show that a slowdown of O(k) is achievable if the communication pattern of each step is known in advance and available for preprocessing. For a certain restricted class of self-simulations we establish matching upper and lower bounds of Θ(k2). We also show that the balanced pos is equivalent to a balanced version of the well-known collision crcw pram, where we now take the balance condition to mean that the number of shared memory cells is the same as the number of processors.

Preprototyping SIMD coprocessors using virtual machine emulation and trace compilation

The use of massively parallel SIMD array architectures is proliferating in the area of domain specific coprocessors. Even so, they have undergone few systematic empirical studies. The underlying problems include the size of the architecture space, the lack of portability of the test programs, and the inherent complexity of simulating up to hundreds of thousands of processing elements. We address the computational cost problem with a novel approach to trace-based simulation. Code is run on an abstract virtual machine to generate a coarse-grained trace, which is then refined through a series of transformations (a process we call trace compilation ) wherein greater resolution is obtained with respect to the details of the target machine. We have found this technique to be one to two orders of magnitude faster than instruction-level simulation while still retaining much of the accuracy of the model. Furthermore, abstract machine traces must be regenerated for only a small fraction of the possible parameter combinations. Using virtual machine emulation and trace compilation also addresses program portability by allowing the user to code in a single data parallel language with a single compiler, regardless of the target architecture. This technique has already been used to generate significant results with respect to SIMD array architectures, a sample of which are presented here.

Distributed shared abstractions (DSA) on multiprocessors

Any parallel program has abstractions that are shared by the program's multiple processes. Such shared abstractions can considerably affect the performance of parallel programs, on both distributed and shared memory multiprocessors. As a result, their implementation must be efficient, and such efficiency should be achieved without unduly compromising program portability and maintainability. The primary contribution of the DSA library is its representation of shared abstractions as objects that may be internally distributed across different nodes of a parallel machine. Such distributed shared abstractions (DSA) are encapsulated so that their implementations are easily changed while maintaining program portability across parallel architectures. The principal results presented are: a demonstration that the fragmentation of object state across different nodes of a multiprocessor machine can significantly improve program performance; and that such object fragmentation can be achieved without compromising portability by changing object interfaces. These results are demonstrated using implementations of the DSA library on several medium scale multiprocessors, including the BBN Butterfly, Kendall Square Research, and SGI shared memory multiprocessors. The DSA library's evaluation uses synthetic workloads and a parallel implementation of a branch and bound algorithm for solving the traveling salesperson problem (TSP).

Developing static reactive power compensators in a power system simulator for power education

This paper describes a newly installed laboratory module microcomputer-based static reactive power compensator (SVC) in detail to teach students how an SVC affects system voltage, load balancing, power factor, and transmission line losses. The SVC is merged into an old power system simulator for extensive power engineering education. The structure of the SVC is thyristor controlled reactors with fixed capacitors (TCR-FC). Two control algorithms, feedback control and feedforward control, are developed and compared. For the purpose of program flexibility and portability, a VME-Bus based microcomputer is used to synthesize the controller of the SVC. Several suggested experiments are given to show the effects of the SVC on distribution system compensation. The SVC greatly promotes the performance of the power system simulator.

An investigation of the performance characteristics of an i860 processor within a Meiko computing surface

This paper presents an implementation of the BLAS 1 subroutine library in i860 assembly code. The target machine is an MK086 high performance dual-node in a Meiko Computing Surface, however this library of routines has been designed to run on any i860 processor. The inherent deficiencies of the generic Fortran compilers are addressed and program portability is still retained. The use of techniques such as dual-instruction mode and pipelined operations have enabled execution times of all routines to be reduced compared to the Fortran equivalents.

Architecture of a graphics processor (abstract)

The design principles that were applied in the design of the integer-RISC machine, are applied to the design of the Reduced Instruction Set Graphics Processor. The processor instruction is defined after critical evaluation of the common graphics operations. Single cycle operation (in a pure RISC style) are performed through instructions for primitive graphics as well as general purpose computations. This processor is envisioned to become the CPU of choice for the ergonomic applications that rely heavily on graphics capabilities for user interface bandwidth improvement. The motivation for integrating graphics with general-purpose computations stems from the performance enhancement acheived due to increased integration levels, and the program portability offered by a single processor based systems.