An investigation of the performance characteristics of an i860 processor within a Meiko computing surface

Abstract

This paper presents an implementation of the BLAS 1 subroutine library in i860 assembly code. The target machine is an MK086 high performance dual-node in a Meiko Computing Surface, however this library of routines has been designed to run on any i860 processor. The inherent deficiencies of the generic Fortran compilers are addressed and program portability is still retained. The use of techniques such as dual-instruction mode and pipelined operations have enabled execution times of all routines to be reduced compared to the Fortran equivalents.