Processor Voltage Research Articles

A Scalable High-Current High-Accuracy Dual-Loop Four-Phase Switching LDO for Microprocessors

High-performance microprocessors need high current (ampere-level), high accuracy, and fast-response power supplies. Comparing to analog and digital low-dropout (LDO) regulators, the switching LDO can be a better candidate for such requirements, as it can drive large power transistor(s) fast and accurately. However, conventional switching LDOs need large load capacitance to reduce the output ripple, which restricts their applications. This article presents a 1.5-A fully-integrated switching LDO for microprocessors, with an easily scalable load capability. Here, we introduce three techniques together to relief the output capacitance requirement: 1) four-phase 500-MHz pulsewidth modulation (PWM) with inherent current balancing; 2) current-limited power cells resisting processor voltage and temperature (PVT) variations; and 3) hybrid fast-slow power transistors. Therefore, we reduce significantly the load capacitance to maximum load current ratio <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$C_{\mathrm {L}} / I_{\mathrm {MAX}}$ </tex-math></inline-formula> when compared with the prior switching LDOs. Also, the proposed dual-loop architecture not only achieves a fast transient response, but also provides high-accuracy regulation. In addition, we design the tunable active voltage positioning (AVP). Fabricated in 28-nm CMOS, the proposed switching LDO measures a maximum 70-mV undershoot with a 1-A load current step with 10-ns edge time. The measured load regulation is 1 mV/A and the line regulation is 1.5 mV/V. Also, we obtain a good power supply rejection (PSR) of −63 dB at 10 kHz and −20 dB at 1 MHz. The PWM automatically moves to a pulse-skipping mode at light load, reducing the quiescent current to 1.8 mA, while the peak current efficiency is 99.27%.

Optimal Real-Time Scheduling Algorithm for Wireless Sensors with Regenerative Energy

Abstract Dynamic voltage and frequency scaling (DVFS) is a promising and broadly used energy-efficient technique to overcome the main problems arising from using a finite energy reservoir capacity and uncertain energy source in real-time embedded systems. This work investigates an energy management scheme for real-time task scheduling in variable voltage processors located in sensor nodes and powered by ambient energy sources. We use DVFS technique to decrease the energy consumption of sensors at the time when the energy sources are limited. In particular, we develop and prove an optimal real-time scheduling framework with speed stretching, namely energy guarantee DVFS (EG-DVFS), that jointly accounts not only for the timing constraints, but also for the energy state incurred by the properties of the system components. EG-DVFS relies on the well-known earliest deadline-harvesting scheduling algorithm combined with DVFS technique where the sensor processing frequency is fine tuned to further minimize energy consumption and to achieve an energy autonomy of the system. Further, an exact feasibility test for a set of periodic, aperiodic or even sporadic tasks is presented.

Integrated Scheduling of Real-Time and Interactive Tasks for Configurable Industrial Systems

With the recent advances in Internet of Things and cyber-physical systems technologies, smart industrial systems support configurable processes consisting of human interactions as well as hard real-time functions. This implies that irregularly arriving interactive tasks and traditional hard real-time tasks coexist. As the characteristics of the tasks are heterogeneous, it is not an easy matter to schedule them all at once. To cope with this situation, this article presents a new task scheduling policy that uses the notion of “virtual real-time task” and two-phase scheduling. As hard real-time tasks must keep their deadlines, we perform offline scheduling based on genetic algorithms beforehand. This determines the processor's voltage level and memory location of each task and also reserves the virtual real-time tasks for interactive tasks. When interactive tasks arrive during the execution, online scheduling is performed on the time slot of the virtual real-time tasks. As interactive workloads evolve over time, we monitor them and periodically update the offline scheduling. Experimental results show that the proposed policy reduces the energy consumption by 66.8% on average without deadline misses and also supports the waiting time of less than 3 (s) for interactive tasks.

VoltJockey

Based on the concept of hardware separation, ARM introduced TrustZone to build a trusted execution environment for applications. It has been quite successful in defending against various software attacks and forcing attackers to explore vulnerabilities in interface designs and side channels. In this article, we propose an innovative software-controlled hardware fault-based attack, VoltJockey, on multi-core processors that adopt dynamic voltage and frequency scaling (DVFS) techniques for energy efficiency. We deliberately manipulate the processor voltage via DVFS to induce hardware faults into the victim cores, and therefore breaking TrustZone. The entire attack process is based on software without any involvement of hardware, which makes VoltJockey stealthy and hard to prevent.

VoltJockey: A New Dynamic Voltage Scaling-Based Fault Injection Attack on Intel SGX

Intel software guard extensions (SGX) increase the security of applications by enabling them to be performed in a highly trusted space (called enclave). Most state-of-the-art attacks on SGX focus on either mining the software vulnerabilities in the enclave or speculating the secret data with side channels. In this study, we report our recent work on breaking SGX by inducing voltage-oriented hardware faults. The novelty and importance of this attack are that it is completely controlled by software and does not require any security vulnerability in the software. Our proposed attack, called VoltJockey, exploits a vulnerability in the implementation of dynamic voltage and frequency scaling (DVFS) that achieves energy saving by dynamically adjusting the processor's operating voltage and thus clock frequency. However, if the operating voltage is lower than a certain critical level, the circuit's timing constraint will fail and hardware fault would be created. We propose to deliberately trigger such voltage-oriented hardware faults by a loadable kernel module that can set the processor's voltage through Intel's undocumented model-specific register (MSR). We first utilize the module to furnish the processor with a transient low voltage with controlled timing to inject a temporal fault into the target location of the program running in the enclave. Then, we perform a differential fault attack on the outputs before and after the injection of faults. For demonstration, we successfully deploy the proposed attack to extract the key of an AES executed in the enclave and lead an SGX-protected RSA to output our specified result.

Energy-cognizant scheduling for preference-oriented fixed-priority real-time tasks

Abstract Energy management is one of the crucial design issues when executing real-time applications with stringent timing requirements. Dynamic slowdown of processor voltage if accompanied with processor shutdown method, helps in better saving energy. Traditionally, energy management has been applied to real-time scheduling algorithms that prioritize tasks based on timing parameters only, however, recently applications having tasks with different execution-preferences on the same computing unit found significant importance in various areas. In this paper, dynamic voltage scaling (DVS) and dynamic power management (DPM) techniques are used for energy management while scheduling preference-oriented fixed-priority periodic real-time tasks. Preference-oriented energy-aware rate-monotonic scheduling (PER) and preference-oriented extended energy-aware rate-monotonic scheduling (PEER) algorithms are proposed that maximize energy savings while fulfilling preference-value of tasks. Extensive simulations show that PER and PEER outperforms in terms of energy savings when compared to several related studies.

A 12- or 48-V Input, 0.9-V Output Active-Clamp Forward Converter Power Block for Servers and Datacenters

DC-to-DC power supplies are critical components for processors in high performance computing and datacenter servers. Conversion from an intermediate bus voltage (e.g., 12 or 48 V) to the core voltage (∼0.9 V) of processors must be efficient, compact, and cost effective. This paper proposes two versions of active-clamp forward converter (ACFC) power blocks to supply core voltage from either 12 or 48 V intermediate bus voltage. The ACFC power block can be individually tested prior to assembly and vertically soldered onto the motherboard to fit in a standard 1U server. A low loss, compact planar transformer is designed into the ACFC power block printed circuit board (PCB). A custom, standing slab inductor not only provides high inductance and high saturation current but also helps to mechanically support the power block. A one-piece copper winding connects the transformer to the inductor, thereby reducing the dc loss in the current path. Thorough analysis is performed to model the conversion loss of the proposed power block. Experimental results show a peak efficiency of 90.4% (12 V input) and 89.5% (48 V input) with 0.9-V output.

Tight Evaluation of Real-Time Task Schedulability for Processor's DVS and Nonvolatile Memory Allocation.

A power-saving approach for real-time systems that combines processor voltage scaling and task placement in hybrid memory is presented. The proposed approach incorporates the task’s memory placement problem between the DRAM (dynamic random access memory) and NVRAM (nonvolatile random access memory) into the task model of the processor’s voltage scaling and adopts power-saving techniques for processor and memory selectively without violating the deadline constraints. Unlike previous work, our model tightly evaluates the worst-case execution time of a task, considering the time delay that may overlap between the processor and memory, thereby reducing the power consumption of real-time systems by 18–88%.

Dynamic scheduling of tasks for multi‐core real‐time systems based on optimum energy and throughput

One of the critical design issues in real-time systems is energy consumption, especially in battery-operated systems. Generally higher processor voltage generates higher throughput of the system while decreasing voltage can perform energy minimisation. Instead of lowering processor voltage, this paper presents an optimum energy efficient real-time scheduling to adjust voltage dynamically to achieve optimum throughput. Earlier research works have considered random new tasks, which have been divided into jobs using pfair scheduling to fit into idle times of different cores of the system. In this paper we consider each job has different power levels and execution time at each power level can be found using normalised execution time. Based on the power levels and their corresponding execution time, we find different combinations of energy signature of the system and derive the optimum state of the system using a weighted average of the energy of the system and corresponding throughput. We verify the proposed model using generated task sets and the results show that the model performs excellently in all the cases and significantly reduced the total energy consumption of the system with respect to some popular and relatively new scheduling schemes.

Energy-Efficient Application Mapping and Scheduling for Lifetime Guaranteed MPSoCs

Energy optimization is one of the most critical objectives for the synthesis of multiprocessor system-on-chip (MPSoC). Besides, to ensure a long processor lifetime and to maintain a safe chip temperature are also important for multiprocessor manufactures under deep submicrometer process technologies. This paper presents a mixed integer linear programming (MILP) model to determine the mapping and scheduling of real-time applications onto embedded MPSoC platforms, such that the total energy consumption is minimized with the lifetime reliability constraint and the temperature threshold constraint satisfied. We develop a lightweight temperature model that can be integrated in the MILP model to predict the chip temperature accurately and efficiently. By exploiting the dynamic voltage and frequency scaling capability of modern processors, processor voltage/frequency assignment is also considered in our MILP model. Extensive performance evaluations on synthetic and real-world applications demonstrate the effectiveness of the proposed approach. Our MILP model achieves an average reduction of 19.09% and 28.53% total energy in comparison with two state-of-the-art techniques on the basis of guaranteeing the safe chip temperature and system lifetime reliability.

Energy-aware dynamic resource management in elastic cloud datacenters

In clouds, placement of on-demand applications on heterogeneous machines, has turned out to be a crucial research problem, particularly, in terms of performance and energy consumption. Techniques like Dynamic Voltage and Frequency Scaling (DVFS), processor speed adjustment and features such as turning off displays, activating sleep modes, etc. are only useful for decreasing the energy consumption of a single machine, at marginal loss in performance. They cannot be used to achieve significant power optimization in High Performance Computing (HPC) systems such as grids, and cloud datacenters; because power saved by scaling down the processor voltage is far less than switching off a machine. Resource management, using dynamic consolidation of VMs, allows cloud service providers to optimize resource usability, performance and decrease power consumption. This paper investigates various resource management techniques, and suggests several heuristic approaches to optimise energy consumption and performance in elastic datacenters. Using real workload datasets, our evaluation suggests that a combination of the proposed VM allocation and consolidation with migration control technique could save approximately 1.96%–9.38% energy, and improve 0.32%–5.96% performance, as compared to its closest rivals.

사물인터넷 환경에서 프로세서와 메모리의 저전력 기술을 결합하는 실시간 태스크 스케줄링 기법

최근 사물인터넷의 급부상으로 배터리 기반 사물인터넷 기기를 위한 전력절감 기술이 주목받고 있다. 사물인터넷 기기는 일종으로 실시간시스템으로, 전력절감을 위해 프로세서의 전압을 동적으로 조절하는 방법이 각광받아왔으나, 최근 연구에 따르면 전력소모 중 메모리가 차지하는 비중이 급격히 증가한 것으로 분석되고 있다. 이에 본 논문은 프로세서의 전압조절 기법에 저전력 비휘발성메모리 기술을 결합하여 실시간시스템의 전력소모를 더욱 줄이고자 한다. 이는 낮은 전압의 프로세서로 태스크의 스케줄링이 가능한 시점에는 메모리의 성능이 낮아지더라도 여전히 스케줄링이 가능성할 것이라는 점에 착안한 것이다. 본 논문은 이기종메모리 상의 태스크 할당 문제를 프로세서의 전압조절 기법과 결합한 후 두 기법의 전력절감 효과를 분석하고, 이들을 결합하여 전력절감을 극대화한다. Due to the recent advances in IoT technologies, reducing power consumption in battery-based IoT devices becomes an important issue. An IoT device is a kind of real-time systems, and processor voltage scaling is known to be effective in reducing power consumption. However, recent research has shown that power consumption in memory increases dramatically in such systems. This paper aims at combining processor voltage scaling and low-power NVRAM technologies to reduce power consumption further. Our main idea is that if a task is schedulable in a lower voltage mode of a processor, we can expect that the task will still be schedulable even on slow NVRAM memory. We incorporate the NVRAM memory allocation problem into processor voltage scaling, and evaluate the effectiveness of the combined approach.

DEP+BURST: Online DVFS Performance Prediction for Energy-Efficient Managed Language Execution

Making modern computer systems energy-efficient is of paramount importance. Dynamic Voltage and Frequency Scaling (DVFS) is widely used to manage the energy and power consumption in modern processors; however, for DVFS to be effective, we need the ability to accurately predict the performance impact of scaling a processor's voltage and frequency. No accurate performance predictors exist for multithreaded applications, let alone managed language applications. In this work, we propose DEP+BURST, a new performance predictor for managed multithreaded applications that takes into account synchronization, interthread dependencies, and store bursts, which frequently occur in managed language workloads. Our predictor lowers the performance estimation error from 27 percent for a state-of-the-art predictor to 6 percent on average, for a set of multithreaded Java applications when the frequency is scaled from 1 to 4 GHz. We also novelly propose an energy management framework that uses DEP+BURST to reduce energy consumption. We first target reducing the processor's energy consumption by lowering its frequency and hence its power consumption, while staying within a user-specified maximum slowdown threshold. For a slowdown of 5 and 10 percent, our energy manager reduces on average 13 and 19 percent of energy consumed by the memory-intensive benchmarks. We then use the energy manager to optimize total system energy, achieving an average reduction of 15.6 percent for a set of Java benchmarks. Accurate performance predictors are key to achieving high performance while keeping energy consumption low for managed language applications using DVFS.

Energy Optimization With Dynamic Task Scheduling Mobile Cloud Computing

The smartphone is a typical cyberphysical system (CPS). It must be low energy consuming and highly reliable to deal with the simple but frequent interactions with the cloud, which constitutes the cloud-integrated CPS. Dynamic voltage scaling (DVS) has emerged as a critical technique to leverage power management by lowering the supply voltage and frequency of processors. In this paper, based on the DVS technique, we propose a novel Energy-aware Dynamic Task Scheduling (EDTS) algorithm to minimize the total energy consumption for smartphones, while satisfying stringent time constraints and the probability constraint for applications. Experimental results indicate that the EDTS algorithm can significantly reduce energy consumption for CPS, as compared to the critical path scheduling method and the parallelism-based scheduling algorithm.

A Power-Scalable Three-Dimensional Streaming Playback Mechanism on Heterogeneous System Architectures

In today’s world, mobile device technologies are advancing with each passing day. People use them to watch videos and deal with important business anywhere. Furthermore, the vigorous development of 3-D streaming technology makes possible the 3-D video conferencing, live broadcast, and online gaming, which made people feel like they were standing right in the scene themselves. However, higher qualities of multimedia streaming are demanded more and more, which necessitates that the content decoding capability of handheld devices be also relatively improved. This is the reason why some handheld devices can execute parallel processing and accelerate decoding processing with extra processes, such as central processing unit, digital signal processor, and graphics processing unit. However, power limitation is one of the inherent restrictions to handheld devices that makes providing high efficiency and energy-saving multimedia streaming service an urgent and interesting challenge. Therefore, a power-scalable 3-D streaming playback mechanism is proposed for the heterogeneous system architecture that is able to adjust the processor frequency or voltage to 3-D streaming service dynamically. In this paper, an immediate and accurate dynamic voltage–frequency scaling prediction mechanism with the properties of dependence for 3-D multimedia streaming decoding features is proposed for power-scalable 3-D streaming playback.

Ultra low overhead error mask flip‐flop in near threshold voltage processor design

Reducing circuit supply voltage to near-threshold (NT) region is an effective technique for achieving better energy efficiency in current ultra-low power circuit design. However, circuit variation problem becomes extremely worse in NT region and requires more design margin. Error detection and correction (EDAC) designs can remove circuit margin by solving transient error dynamically, but many of the traditional EDAC designs cause large area overhead and cycle per instruction (CPI) penalty. A compact timing error mask flip-flop (EMFF) based on error masking with ultra-low overhead by only adding six transistors (four for error detection and two for error correction) to the conventional flip-flop with 0 CPI penalty is presented. The proposed EMFF reduces system area overhead significantly. Therefore, the timing error tolerance ability is expanded and higher energy efficiency can be archived. EMFF is realised in an industrial processor in SMIC 40 nm CMOS with only 6.8% area overhead, compared with the original processor. At 0.5 V, the EMFF system gains 18.6% performance increasing than the most compact previous work with 3% higher efficiency.

Exploiting dynamic timing slack for energy efficiency in ultra-low-power embedded systems

Many emerging applications such as the internet of things, wearables, and sensor networks have ultra-low-power requirements. At the same time, cost and programmability considerations dictate that many of these applications will be powered by general purpose embedded microprocessors and microcontrollers, not ASICs. In this paper, we exploit a new opportunity for improving energy efficiency in ultra-low-power processors expected to drive these applications -- dynamic timing slack. Dynamic timing slack exists when an embedded software application executed on a processor does not exercise the processor's static critical paths. In such scenarios, the longest path exercised by the application has additional timing slack which can be exploited for power savings at no performance cost by scaling down the processor's voltage at the same frequency until the longest exercised paths just meet timing constraints. Paths that cannot be exercised by an application can safely be allowed to violate timing constraints. We show that dynamic timing slack exists for many ultra-low-power applications and that exploiting dynamic timing slack can result in significant power savings for many ultra-low-power processors. We also present an automated methodology for identifying dynamic timing slack and selecting a safe operating point for a processor and a particular embedded software. Our approach for identifying and exploiting dynamic timing slack is non-speculative, requires no programmer intervention and little or no hardware support, and demonstrates potential power savings of up to 32%, 25% on average, over a range of embedded applications running on a common ultra-low-power processor, at no performance cost.

Cross-matching caches: Dynamic timing calibration and bit-level timing-failure mask caches to reduce timing discrepancies with low voltage processors

Voltage scaling is an effective technique to reduce power consumption in processor systems. Unfortunately, timing discrepancies between L1 caches and cores occur with the scaling down of voltage. These discrepancies are primarily caused by the severe process variations of a few slow SRAM cells. Most previous designs tolerated slow cells by adjusting access latency based on a coarse-grained track of cache blocks. However, these methods become insufficient when the amount of slow cells increases. This paper addresses the issue for an 8T SRAM cache and proposes a cross-matching cache that includes dynamic timing calibration and actual bit-level timing-failure toleration.

Time and Energy Efficient DVS Scheduling for Real-Time Pinwheel Tasks

Dynamic voltage/frequency scaling (DVFS) is one of the most effective techniques for reducing energy use. In thispaper, we focus on the pinwheel task model to develop a variable voltage processor with d discrete voltage/speedlevels. Depending on the granularity of execution unit to which voltage scaling is applied, DVFS scheduling can bedefined in two categories: (i) inter-task DVFS and (ii) intra-task DVFS. In the periodic pinwheel task model, wemodified the definitions of both intra- and inter-task and design their DVFS scheduling to reduce the powerconsumption of DVFS processors. Many previous approaches have solved DVFS problems by generating a canonicalschedule in advance and thus require pseudo polynomial time and space because the length of a canonical scheduledepends on the hyperperiod of the task periods and is generally of exponential length. To limit the length of thecanonical schedules and predict their task execution, tasks with arbitrary periods are first transformed into harmonicperiods and their key features are profiled. The proposed methods have polynomial time and space complexities, andexperimental results show that, under identical assumptions, the proposed methods achieve more energy savingsthan the previous methods.

Energy Saving EDF Scheduling for Wireless Sensors on Variable Voltage Processors

Advances in micro technology has led to the development of miniaturized sensor nodes with wireless communication to perform several real-time computations. These systems are deployed wherever it is not possible to maintain a wired network infrastructure and to recharge/replace batteries and the goal is then to prolong as much as possible the lifetime of the system. In our work, we aim to modify the Earliest Deadline First (EDF) scheduling algorithm to minimize the energy consumption using the Dynamic Voltage and Frequency Selection. To this end, we propose an Energy Saving EDF (ES-EDF) algorithm that is capable of stretching the worst case execution time of tasks as much as possible without violating deadlines. We prove that ES-EDF is optimal in minimizing processor energy consumption and maximum lateness for which an upper bound on the processor energy saving is derived. In order to demonstrate the benefits of our algorithm, we evaluate it by means of simulation. Experimental results show that ES-EDF outperforms EDF and Enhanced EDF (E-EDF) algorithms in terms of both percentage of feasible task sets and energy savings.