Network Of Processors Research Articles

Embedded multi-processor system-on-programmable chip for smart camera pose estimation using nonlinear optimization methods

The PanoraMOS prototype is a complete localization system targeting Simultaneous Localization and Mapping applications. It is a panoramic camera that uses a single rotating linear sensor to capture cylindrical panoramic images at up to 3 frames per second. A complete localization algorithm has been implemented into the hardware architecture of the system. It has the ability to estimate its 3D pose in an indoor or an outdoor environment. This estimation is performed using a feature extractor and the Levenberg---Marquardt (LM) algorithm with the Random Sample Consensus (RANSAC) algorithm to perform detection. In this paper, we present the whole system particularly emphasize the localization algorithm and its implementation on a hardware architecture which is our main contribution. The implementation was done on a Multi-Processor System-on-Chip architecture. We present both software and hardware implementations with performance results on an ALTERA System-on-Programmable Chip target. The experimental results including processing times and application speed up show that our homogeneous network of processors is efficient for embedding the proposed image processing application.

A workflow task scheduling algorithm based on the resources' fuzzy clustering in cloud computing environment

SummaryCloud computing is the key and frontier field of the current domestic and international computer technology, workflow task scheduling plays an important part of cloud computing, which is a policy that maps tasks to appropriate resources to execute. Effective task scheduling is essential for obtaining high performance in cloud environment. In this paper, we present a workflow task scheduling algorithm based on the resources' fuzzy clustering named FCBWTS. The major objective of scheduling is to minimize makespan of the precedence constrained applications, which can be modeled as a directed acyclic graph. In FCBWTS, the resource characteristics of cloud computing are considered, a group of characteristics, which describe the synthetic performance of processing units in the resource system, are defined in this paper. With these characteristics and the execution time influence of the ready task in the critical path, processing unit network is pretreated by fuzzy clustering method in order to realize the reasonable partition of processor network. Therefore, it largely reduces the cost in deciding which processor to execute the current task. Comparison on performance evaluation using both the case data in the recent literature and randomly generated directed acyclic graphs shows that this algorithm has outperformed the HEFT, DLS algorithms both in makespan and scheduling time consumed. Copyright © 2014 John Wiley & Sons, Ltd.

Hybrid Algorithm Based on Ant and Genetic Algorithms for Task Allocation on a Network of Homogeneous Processors

In the field of parallel computing, there is an essential problem which is called Task Allocation Problem(TAP). The task allocation problem (TAP) is a problem where many of tasks require to be allocated to a set of processors.The number of m tasks that is needed to be allocated with number of n processors where (m>n) so that the time needed to process all the tasks is minimized. This paper presents an efficient algorithm (TAP_ACO_GA) to solve the task allocation problem. The proposed algorithm is based on the idea of Ant Colony Optimization Algorithm(ACO) and the idea of Genetic Algorithm (GA) .The proposed algorithm is tested in different dataset and its results are compared with the results in[2] and the results show that TAP_ACO_GA is better than the other algorithm.

Networks of polarized evolutionary processors

In this paper, we consider a new variant of networks of evolutionary processors which seems to be more suitable for a software and hardware implementation. Each processor as well as the data navigating throughout the network are now considered to be polarized. While the polarization of every processor is predefined, the data polarization is dynamically computed by means of a valuation mapping. Consequently, the protocol of communication is naturally defined by means of this polarization. This new variant is investigated here as a problem solver. We propose solutions based on networks of polarized evolutionary processors to two computationally hard problems, namely the “3-colorability problem”, and a more general one known as the “Common Algorithmic Problem”. Our solutions are uniform (they work for all instances of the same size) and time efficient (they work in linear time).

Accepting Networks of Evolutionary Picture Processors

We extend the study of networks of evolutionary processors accepting words to a similar model, processing rectangular pictures. To this aim, we introduce accepting networks of evolutionary picture processors and investigate their computational power. We show that these networks can accept the complement of any local picture language as well as picture languages that are not recognizable. Some open problems regarding decidability issues and closure properties are finally discussed.

Remarks on dynamic load balancing of integer loads and integral graphs

Cvetković et al. (2010) [3] presented an algorithm for dynamic load balancing in discrete load model based on the eigenvectors of the adjacency matrix of the processor network. In case of integral graphs, whose eigenvalues are integers and whose eigenvector basis may be chosen to consist of integers only, this algorithm executes in integer arithmetic, providing an argument for the use of integral graphs as suitable candidates for processor networks. It is observed here that this algorithm, however, is not capable of balancing all integer load distributions.After specifying a necessary and sufficient condition for properly managing all integer load distributions, it becomes apparent that the proposed algorithm does not actually depend on the integrality of eigenvectors, but on employing a set of balancing flows carrying a unit load from a fixed vertex to each of the remaining vertices in the graph. Such sets exist for every connected graph and, thus, yield a simple load balancing algorithm that can be executed in integer arithmetic for every processor network.

DVS scheduling in a line or a star network of processors

Dynamic voltage scaling (DVS) is a technique which allows the processors to change speed when executing jobs. Most of the previous works study either single processor or multiple parallel processors. In this paper, we consider a network of DVS enabled processors. Every job needs to go along a certain path in the network and has a certain workload finished on any processor it goes through before it moves on to the next processor. Our objective is to minimize the total energy consumption while finishing every job before its deadline. Due to the intrinsic complexity of this problem, we only focus on line networks with two nodes and a simple one-level tree network (a star). We show that in some of these simple cases, the optimal schedule can be computed efficiently and interleaving is not needed to achieve optimality. However, in both types of networks, how to find the optimal sequence of execution remains a big challenge for jobs with general workloads.

Accepting Networks of Evolutionary Processors with Subregular Filters

We propose a new variant of Accepting Networks of Evolutionary Processors, in which the operations are applied at arbitrary positions to the processed words (rather than at the ends of words only) and where the filters are languages from several special classes of regular sets. More precisely, we show that the use of filters from the class of non-counting, ordered, power-separating, suffix-closed regular, union-free, definite and combinational languages is as powerful as the use of arbitrary regular languages and yields networks that can accept all the recursively enumerable languages. On the other hand, by using filters that are only finite languages, monoids, nilpotent languages, commutative regular languages, or circular regular languages, one cannot generate all recursively enumerable languages. These results seem interesting as they provide both upper and lower bounds on the classes of languages that one can use as filters in an accepting network of evolutionary processors in order to obtain a complete computational model.

Automated design of networks of transport-triggered architecture processors using dynamic dataflow programs

Modern embedded systems show a clear trend towards the use of Multiprocessor System-on-Chip (MPSoC) architectures in order to handle the performance and power consumption constraints. However, the design and validation of dedicated MPSoCs is an extremely hard and expensive task due to their complexity. Thus, the development of automated design processes is of highest importance to satisfy the time-to-market pressure of embedded systems.This paper proposes an automated co-design flow based on the high-level language-based approach of the Reconfigurable Video Coding framework. The designer provides the application description in the RVC-CAL dataflow language, after which the presented co-design flow automatically generates a network of heterogeneous processors that can be synthesized on FPGA chips. The synthesized processors are Very Long Instruction Word-style processors. Such a methodology permits the rapid design of a many-core signal processing system which can take advantage of all levels of parallelism.The toolchain functionality has been demonstrated by synthesizing an MPEG-4 Simple Profile video decoder to two different FPGA boards. The decoder is realized into 18 processors that decode QCIF resolution video at 45 frames per second on a 50MHz FPGA clock frequency. The results show that the given application can take advantage of every level of parallelism.

Oblivious algorithms for multicores and networks of processors

We address the design of algorithms for multicores that are oblivious to machine parameters. We propose HM, a multicore model consisting of a parallel shared-memory machine with hierarchical multi-level caching, and we introduce a multicore-oblivious approach to algorithms and schedulers for HM. A multicore-oblivious algorithm is specified with no mention of any machine parameters, such as the number of cores, number of cache levels, cache sizes and block lengths. However, it is equipped with a small set of instructions that can be used to provide hints to the run-time scheduler on how to schedule parallel tasks. We present efficient multicore-oblivious algorithms for several fundamental problems including matrix transposition, FFT, sorting, the Gaussian Elimination Paradigm, list ranking, and connected components. The notion of a multicore-oblivious algorithm is complementary to that of a network-oblivious algorithm, introduced by Bilardi et al. (2007) [8] for parallel distributed-memory machines where processors communicate point-to-point. We show that several of our multicore-oblivious algorithms translate into efficient network-oblivious algorithms, adding to the body of known efficient network-oblivious algorithms.

Interconnection system for the SpiNNaker biologically inspired multi‐computer

SpiNNaker is a large-scale multi-core computing engine designed to model heavily distributed fine-grain problems. The machine is constructed hierarchically: 1 monitor and 16 worker processors form a single node of a toroidal compute ‘surface’. The six high-speed bi-directional links of each node are used for triangular edge connections that provide alternative routes around problematic links. The system itself is scalable from one node up to 216 resulting in a maximum of 220 worker processors. SpiNNaker is an isotropic homogeneous network of processors that deliberately includes no central overseer. A consequence of this isotropy is an absence of perimeter and hence no natural position for peripheral I/O connections. This study describes the practical techniques and details employed in two components of the system: (a) SpiNNlink is the proposed board-to-board interconnection system that multiplexes 48 separate 250 Mbps SpiNNaker links through six off-board connections without compromising the overall system bisection bandwidth, forms an isotropic meta-network on top of SpiNNaker without requiring any cooperation from system software, and remains transparent to the SpiNNaker network; and (b) SpiNNterceptor is the proposed peripheral I/O subsystem developed as a layer on top of SpiNNlink that provides over 18 Gbps of minimally disruptive communication between SpiNNaker applications and externally connected equipment.

Task graph pre-scheduling, using Nash equilibrium in game theory

Prescheduling algorithms are targeted at restructuring of task graphs for optimal scheduling. Task graph scheduling is a NP-complete problem. This article offers a prescheduling algorithm for tasks to be executed on the networks of homogeneous processors. The proposed algorithm merges tasks to minimize their earliest start time while reducing the overall completion time. To this end, considering each task as a player attempting to reduce its earliest time as much as possible, we have applied the idea of Nash equilibrium in game theory to determine the most appropriate merging. Also, considering each level of a task graph as a player, seeking for distinct parallel processors to execute each of its independent tasks in parallel with the others, the idea of Nash equilibrium in game theory can be applied to determine the appropriate number of processors in a way that the overall idle time of the processors is minimized and the throughput is maximized. The communication delay will be explicitly considered in the comparisons. Our experiments with a number of known benchmarks task graphs and also two well-known problems of linear algebra, LU decomposition and Gauss---Jordan elimination, demonstrate the distinguished scheduling results provided by applying our algorithm. In our study, we consider ten scheduling algorithms: min---min, chaining, A ?, genetic algorithms, simulated annealing, tabu search, HLFET, ISH, DSH with task duplication, and our proposed algorithm (PSGT).

Towards a Bio-Inspired Theoretical Linguistics to Model Man-Machine Communication

The paper provides an overview of what could be a new biological-inspired linguistics. The authors discuss some reasons for attempting a more natural description of natural language, lying on new theories of molecular biology and their formalization within the area of theoretical computer science. The authors especially explore three bio-inspired models of computation –DNA computing, membrane computing and networks of evolutionary processors (NEPs) – and their possibilities for achieving a simpler, more natural, and mathematically consistent theoretical linguistics.

Priority based Distributed Job Processing System

paper proposes a framework for implementing a Priority Based Job processing system that has the capability to specify the priority of a job at the time of submission, execute the job at as per the priority at the job processor end. The framework will scale horizontally as well as vertically without any change in the components. This feature is achieved through simple configuration. The advantages of such a framework over other implementations is that we are using a global queue where in the processors can be dynamically added or removed without affecting the overall processing of jobs. This makes it flexible enough for any processor to handle any type of job without any restriction. While, it is still possible to impose restrictions on specific processors handling special type of jobs that is implemented as a configuration option and does not in any way impose restrictions on the processors. Therefore, new types of processors can seamlessly added to the entire network of processors without affecting the existing processors.

Networks of evolutionary processors: the power of subregular filters

In this paper, we propose a hierarchy of families of languages generated by networks of evolutionary processors where the filters belong to several special classes of regular sets. More precisely, we show that the use of filters from the class of ordered, non-counting, power-separating, circular, suffix-closed regular, union-free, definite, and combinational languages is as powerful as the use of arbitrary regular languages and yields networks that can generate all the recursively enumerable languages. On the other hand, the use of filters that are only finite languages allows only the generation of regular languages, but not every regular language can be generated. If we use filters that are monoids, nilpotent languages, or commutative regular languages, we obtain one and the same family of languages which contains non-context-free languages but not all regular languages. These results seem to be of interest because they provide both upper and lower bounds on the families of languages that one can use as filters in a network of evolutionary processors in order to obtain a complete computational model.

Software-Defined Sphere Decoding for FPGA-Based MIMO Detection

Sphere Decoding (SD) is a highly effective detection technique for Multiple-Input Multiple-Output (MIMO) wireless communications receivers, offering quasi-optimal accuracy with relatively low computational complexity as compared to the ideal ML detector. Despite this, the computational demands of even low-complexity SD variants, such as Fixed Complexity SD (FSD), remains such that implementation on modern software-defined network equipment is a highly challenging process, and indeed real-time solutions for MIMO systems such as 4 × 4 16-QAM 802.11n are unreported. This paper overcomes this barrier. By exploiting large-scale networks of fine-grained software-programmable processors on Field Programmable Gate Array (FPGA), a series of unique SD implementations are presented, culminating in the only single-chip, real-time quasi-optimal SD for 4 × 4 16-QAM 802.11n MIMO. Furthermore, it demonstrates that the high performance software-defined architectures which enable these implementations exhibit cost comparable to dedicated circuit architectures.

Independent Task Scheduling in Grid Computing Based on Queen Bee Algorithm

Article history: th , 2012 Grid computing is a new model that uses a network of processors connected together to perform bulk operations allows computations. Since it is possible to run multiple applications simultaneously may require multiple resources but often do not have the resources; so there is a scheduling system to allocate resources is essential. In view of the extent and distribution of resources in the grid computing, task scheduling is one of the major challenges in grid environment. Scheduling algorithms must be designed according to the current challenges in grid environment and they assign tasks to resource to decrease makespan which is generated. Because of the complex issues of scheduling tasks on the grid is deterministic algorithms work best for this offer. In this Paper, the Queen-bee algorithm is presented to solve the problem and the results have been compared to several other meta-heuristic algorithms. Also, it is shown that the proposed algorithm decline calculation time beside decreasing makespan compared to other algorithms. Keyword: Grid computing Scheduling Queen-Bee PSO Genetic SA

Generating Networks of Splicing Processors

In this paper, we introduce generating networks of splicing processors (GNSP for short), a formal languages generating model related to networks of evolutionary processors and to accepting networks of splicing processors. We show that all recursively enumerable languages can be generated by GNSPs with only nine processors. We also show, by direct simulation, that two other variants of this computing model, where the communication between processors is conducted in different ways, have the same computational power.

Networks of evolutionary processors: computationally complete normal forms

Networks of evolutionary processors (NEPs, for short) form a bio-inspired language generating computational model that was shown to be equivalent to the model of phrase-structure grammars. In this paper, we analyse different restricted variants of NEPs that preserve the computational power of the general model. We prove that any recursively enumerable language can be generated by a NEP where the derivation rules can be applied at arbitrarily chosen positions, the control of the communication is done by finite automata with at most three states, and either the rule sets are singletons or the underlying graph is a complete graph. If one uses networks with arbitrary underlying graphs and allows the additional application of insertions and deletions only to the right-most or the to left-most position of the derived words for some nodes, then we only need automata with only one state to control the communication in the network. Clearly, this result is optimal; moreover, finite automata with two states are necessary and sufficient in order to generate all the recursively enumerable languages when the derivation rules can be applied only at arbitrarily chosen positions.

Complexity results for deciding Networks of Evolutionary Processors

The Accepting Networks of Evolutionary Processors (ANEPs for short) are bio-inspired computational models which were introduced and thoroughly studied in the last decade. In this paper we propose a method of using ANEPs as deciding devices. More precisely, we define a new halting condition for this model, which seems more coherent with the rest of the theory than the previous such definitions, and show that all the computability related results reported so far remain valid in the new framework. Further, we are able to show a direct and efficient simulation of an arbitrary ANEP by an ANEP having a complete underlying graph; as a consequence of this result, we conclude that the efficiency of deciding a language by ANEPs is not influenced by the network’s topology. Finally, focusing on the computational complexity of ANEP-based computations, we obtain a surprising characterisation of PNP[log] as the class of languages that can be decided in polynomial time by such networks.