Processing Elements Research Articles

SHIELD: Security-aware Schreduling for Real-Time DAGs on Heterogeneous Systems

Many control applications in real-time cyber-physical systems are represented as Directed Acyclic Graphs ( DAGs ) due to complex interactions among their functional components, and executed on distributed heterogeneous platforms. Data communication between dependent task nodes running on different processing elements are often realized through message transmission over a public network, and are hence susceptible to multiple security threats such as snooping , alteration and spoofing . Several alternative security protocols having varying security strengths and associated implementation overheads are available in the market, for incorporating confidentiality , integrity and authentication on the transmitted messages. While message size and conceptually its associated transmission overheads may be marginally increased due to the assignment of security protocols, significant computation overheads must be incurred for securing the message at the location of its source task node and for unlocking security/message extraction at the destination. Obtained security strengths and associated computation overheads vary depending on the set of protocols chosen for a given message from an available pool of protocols. Given lower bounds on the security demands of an application's messages, selecting the appropriate protocols for each message such that a system's overall security is maximized while satisfying constraints related to the resource, task precedence and deadline, is a challenging and computationally hard problem. In this paper, we propose an efficient heuristic strategy called SHIELD for security-aware real-time scheduling of DAG-structured applications to be executed on distributed heterogeneous systems. The efficacy of the proposed scheduler is exhibited through extensive simulation-based experiments using two DAG-structured application benchmarks. Our performance evaluation results demonstrate that SHIELD significantly outperforms two greedy baseline strategies SHIELDb in terms of solution generation times (i.e., run-times) and SHIELDf in terms of achieved security utility. Additionally, a case study on the Traction Control application in automotive systems has been included to exhibit the applicability of SHIELD in real-world settings.

Hardware Design Strategies Oriented to Edge Computing and AgriFood Electronics for Image Processing using Cellular Automata

There has been a growing interest from academia and industry in developing circuits and systems for edge computing and quality control tasks in food production lines, where image-processing is frequently required. This paper outlines the required considerations for designing a fruit classification system based on image-processing using Cellular Automata (CA) models and integrating it into reconfigurable hardware (HW) such as Field Programmable Gate Arrays (FPGAs). Parallel processing in CA requires numerous processing elements to be implemented and mapping CA models to HW generally comes with limitations. Homogeneous CA arrays are easier to design and implement in HW but can be resource-demanding. To fill this gap, this study explores different alternatives for the HW implementation of CA models, particularly trading computational-parallelism for a more optimized use of the available HW resources. We conducted experimental tests of the designed HW system using the Digilent Nexys development board, and the operation was validated against software-based benchmarks for image-processing, particularly concerning edge-detection. The presented study provides a broader range of design solutions for the HW implementation of two-dimensional CA models and a better understanding of their advantages and disadvantages. The results show that solutions focusing on instruction-parallelism add some complexity to the conception and require more design effort, compared to homogeneous CA models composed of identical cells. However, the instruction-parallel design solutions can significantly improve the HW resource utilization, especially when implementing computationally intensive CA rules in FPGAs.

An efficient CNN accelerator for pattern-compressed sparse neural networks on FPGA

Currently, the sparsity of weights and activations are mainly utilized to improve the energy efficiency and computational performance of CNN accelerators. However, the irregular sparsity of weights and activations can lead to problems such as mapping access conflict and imbalanced workload, which poses great challenges to the efficient computation of sparse networks. To address those problems, this paper proposes a CNN accelerator for pattern-compressed sparse neural networks on FPGA to achieve efficient inference acceleration. It mainly includes three parts: first, we propose a convolutional kernel grouping fusion method to achieve a balanced workload of weights. Second, we propose an activation hash mapping conflict reduction method to drastically reduce the mapping access conflict rate. Finally, we further propose a hierarchical mapping computing architecture to achieve efficient processing of mapping access conflicts and balanced adaptation of weight loads. To verify the effectiveness of the method proposed in this paper, our accelerator is designed and implemented on the Zynq UltraScale+ MPSoC ZCU102 evaluation board and evaluated by running VGG16 and ResNet50 networks. The experimental results show that the method proposed in this paper can reduce the mapping conflicts by more than 97 % and improve the utilization rate of processing element (PE) by 1.67×. Furthermore, the accelerator implemented in this paper can achieve 393.2 GOPs throughput, 1.40–3.25× computational performance, and 1.11–7.34× energy efficiency improvement.

A novel Real-time Control System for next generation gravitational-wave detectors

This contribution presents the INFN Pisa group research and development efforts aimed at defining and implementing a novel Real-time Control System (RCS) for next-generation interferometers, focusing on the initial phase of the Einstein Telescope (ET) gravitational wave detector. The RCS handles complex closed-loop systems, managing data collection from sensing elements, processing and actuator control within well defined time constraints. It integrates multiple spatially distributed control units, facilitating communications among them, with external systems as well as with users. Two distinct hardware approaches are explored: “Katane” and “Zancle”. These systems primarily differ in their core processing elements. The “Katane” system is built on powerful DSP processor boards, based on the Super-Attenuator control system, developed at INFN Pisa for Advanced Virgo detector. It uses the MicroTCA.4 architecture standard, ensuring flexibility, easy maintenance, and fast data exchange among the various custom modules, including several types of Front-End data converter boards, FPGA-based pre-processing boards, DSPs and standard processors. On the other hand, ”Zancle” explores GPU-based processing, aiming to use cost-effective consumer market systems and to leverage substantial computational power of these devices, also incorporating machine learning algorithms.

Development of the Combined Operations Method to Improve the Efficiency of Block Encryption

Real-time information protection requires the implementation of special methods aimed at providing reliable and fast encryption algorithms to protect personal and corporate information from unauthorized access. With the growth of data volumes and the speed of their processing, the importance of effective encryption methods increases significantly. One of the common, reliable and well-known encryption algorithms is AES (Advanced Encryption Standard), also known as Rijndael, which is a symmetric block cipher. AES has high efficiency and cryptoresistance and is suitable for processing large volumes of data. The reliability and speed of encryption and decryption using the AES algorithm depends on the size of the key and the data. This paper proposes to improve algorithm of symmetric block encryption AES to provide faster data processing. The possibility of combining mathematical operations that have a similar principle of processing elements is shown. This approach made it possible to reduce the processing time for data encryption and decryption compared to known implementations. A comparative analysis of the practical implementation of the standard and optimized AES cryptoalgorithms has been carried out. The general principles of the proposed method are to transform all two-dimensional arrays into one-dimensional arrays, add auxiliary tables for ShiftRows and MixColumns operations, and combine operations with similar element processing principles. The simulation results showed that the modified implementation of the AES algorithm demonstrates a reduction in processing time of up to 50% when encrypting and up to 75% when decrypting data compared to known results

Design and Evaluation of Real-Time Data Storage and Signal Processing in a Long-Range Distributed Acoustic Sensing (DAS) Using Cloud-Based Services.

In cloud-based Distributed Acoustic Sensing (DAS) sensor data management, we are confronted with two primary challenges. First, the development of efficient storage mechanisms capable of handling the enormous volume of data generated by these sensors poses a challenge. To solve this issue, we propose a method to address the issue of handling the large amount of data involved in DAS by designing and implementing a pipeline system to efficiently send the big data to DynamoDB in order to fully use the low latency of the DynamoDB data storage system for a benchmark DAS scheme for performing continuous monitoring over a 100 km range at a meter-scale spatial resolution. We employ the DynamoDB functionality of Amazon Web Services (AWS), which allows highly expandable storage capacity with latency of access of a few tens of milliseconds. The different stages of DAS data handling are performed in a pipeline, and the scheme is optimized for high overall throughput with reduced latency suitable for concurrent, real-time event extraction as well as the minimal storage of raw and intermediate data. In addition, the scalability of the DynamoDB-based data storage scheme is evaluated for linear and nonlinear variations of number of batches of access and a wide range of data sample sizes corresponding to sensing ranges of 1-110 km. The results show latencies of 40 ms per batch of access with low standard deviations of a few milliseconds, and latency per sample decreases for increasing the sample size, paving the way toward the development of scalable, cloud-based data storage services integrating additional post-processing for more precise feature extraction. The technique greatly simplifies DAS data handling in key application areas requiring continuous, large-scale measurement schemes. In addition, the processing of raw traces in a long-distance DAS for real-time monitoring requires the careful design of computational resources to guarantee requisite dynamic performance. Now, we will focus on the design of a system for the performance evaluation of cloud computing systems for diverse computations on DAS data. This system is aimed at unveiling valuable insights into performance metrics and operational efficiencies of computations on the data in the cloud, which will provide a deeper understanding of the system's performance, identify potential bottlenecks, and suggest areas for improvement. To achieve this, we employ the CloudSim framework. The analysis reveals that the virtual machine (VM) performance decreases significantly the processing time with more capable VMs, influenced by Processing Elements (PEs) and Million Instructions Per Second (MIPS). The results also reflect that, although a larger number of computations is required as the fiber length increases, with the subsequent increase in processing time, the overall speed of computation is still suitable for continuous real-time monitoring. We also see that VMs with lower performance in terms of processing speed and number of CPUs have more inconsistent processing times compared to those with higher performance, while not incurring significantly higher prices. Additionally, the impact of VM parameters on computation time is explored, highlighting the importance of resource optimization in the DAS system design for efficient performance. The study also observes a notable trend in processing time, showing a significant decrease for every additional 50,000 columns processed as the length of the fiber increases. This finding underscores the efficiency gains achieved with larger computational loads, indicating improved system performance and capacity utilization as the DAS system processes more extensive datasets.

Modeling and Controlling Many-Core HPC Processors: an Alternative to PID and Moving Average Algorithms

The race towards performance increase and computing power has led to chips with heterogeneous and complex designs, integrating an ever-growing number of cores on the same monolithic chip or chiplet silicon die. Higher integration density, compounded with the slowdown of technology-driven power reduction, implies that power and thermal management become increasingly relevant. Unfortunately, existing research lacks a detailed analysis and modeling of thermal, power, and electrical coupling effects and how they have to be jointly considered to perform dynamic control of complex and heterogeneous mpsoc. To close the gap, in this work, we first provide a detailed thermal and power model targeting a modern hpc mpsoc. We consider real-world coupling effects such as actuators’ non-idealities and the exponential relation between the dissipated power, the temperature state, and the voltage level in a single processing element. We analyze how these factors affect the control algorithm behavior and the type of challenges that they pose. Based on the analysis, we propose a thermal capping strategy inspired by Fuzzy control theory to replace the state-of-the-art PID controller, as well as a root-finding iterative method to optimally choose the shared voltage value among cores grouped in the same voltage domain. We evaluate the proposed controller with model-in-the-loop and hardware-in-the-loop co-simulations. We show an improvement over state-of-the-art methods of up to \(5\times\) the maximum exceeded temperature while providing an average of \(3.56\%\) faster application execution runtime across all the evaluation scenarios.

Grapher: A Reconfigurable Graph Computing Accelerator with Optimized Processing Elements

In recent years, various graph computing architectures have been proposed to process graph data that represent complex dependencies between different objects in the world. The designs of the processing element (PE) in traditional graph computing accelerators are often optimized for specific graph algorithms or tasks, which limits their flexibility in processing different types of graph algorithms, or the parallel configuration that can be supported by their PE arrays is inefficient. To achieve both flexibility and efficiency, this paper proposes Grapher, a reconfigurable graph computing accelerator based on an optimized PE array, efficiently supporting multiple graph algorithms, enhancing parallel computation, and improving adaptability and system performance through dynamic hardware resource configuration. To verify the performance of Grapher, this paper selected six datasets from the Stanford Network Analysis Project (SNAP) database for testing. Compared with the existing typical graph frameworks Ligra, Gemini, and GraphBIG, the processing time for the six datasets using the BFS, CC, and PR algorithms was reduced by up to 39.31%, 35.43%, and 27.67%, respectively. The energy efficiency has also been improved by 1.8× compared to Hitgraph and 4.7× compared to ThunderGP.

Tailoring Deformation Homogeneity of WE43 Alloy through Strain Rate Sensitivity and Back Pressure during Equal Channel Angular Pressing

AbstractEqual channel angular pressing (ECAP) of the magnesium alloys at room temperature owing to their limited workability is challenging. Successful ECAP processing of WE43 magnesium faces two main difficulties, heterogeneous distribution of the strain rate and also tensile strain accommodation on the top surface of the workpiece, leading to catastrophic segmentation of the alloy. In this paper, strain rate sensitivity (SRS) was studied to adopt a proper preprocessing of the material before ECAP processing. The SRS exponents, obtained from compression tests, revealed that solution treatment reduced the SRS of the alloy. To mitigate strain accommodation, an ECAP core-sheath configuration was used to induce back pressure for the sake of deformation homogeneity improvement. A combination of experimental processing and 3D finite element method simulations was applied to the solution-treated WE43 alloy with different core sizes and sheath materials. By finding the optimized core sizes and sheath materials with higher strengths, the differences in microhardness and equivalent plastic strain were reduced. Besides, the adequate magnitude of back pressure and the imposed fully compressive stress prevent fragmentation of the WE43 core during ECAP. After stepwise modifications, the plastic strain inhomogeneity index decreased from 1.340 to 0.671.

HashGrid: An optimized architecture for accelerating graph computing on FPGAs

Large-scale graph processing poses challenges due to its size and irregular memory access patterns, causing performance degradation in common architectures, such as CPUs and GPUs. Recent research includes accelerating graph processing using Field Programmable Gate Arrays (FPGAs). FPGAs can provide very efficient acceleration thanks to reconfigurable on-chip resources. Although limited, these resources offer a larger design space than CPUs and GPUs.We propose an approach in which data are preprocessed in small chunks with an optimized graph partitioning technique for execution on FPGA accelerators. The chunks, located on the host, are streamed directly into a customized memory layer implemented in the FPGA, which is tightly coupled with the processing elements responsible for the graph algorithm execution. This improves application memory access latency, which is crucial in large-sale graph computing performance.This work presents a hardware design that, combined with graph partitioning, enables us to achieve high-performance and potentially scalable handling of large graphs (i.e., graphs with millions of vertices and billions of edges in current scenarios) while using popular graph algorithms. The proposed framework accelerates performance 56 times compared with CPU (multicore with 16 logical cores in our reference experiments), 2.5 times and 4 times faster compared to state-of-the-art FPGA and GPU solutions (FPGA has 15 compute units, and GPU reference has 128 streaming-multiprocessors in our experiments), respectively, when using the PageRank algorithm. For the Single-Source-Shortest-Past (SSSP) algorithm, we achieve speedups of up to 65x, 26x, and 18x compared to CPU, GPU, and FPGA works, respectively. Lastly, in the context of the Weakly Connected Component (WCC) algorithm, our framework achieves a speedup of up to 403 times compared to the CPU, 7.4x against the GPU, and it is faster than the FPGA alternatives up to 10.3x.

An efficient ANN SoC for detecting Alzheimer's disease based on recurrent computing

Alzheimer's Disease (AD) is an irreversible, degenerative condition that, while incurable, can have its progression slowed or impeded. While there are numerous methods utilizing neural networks for AD detection, there is a scarcity of High-performance AD detection chips. Moreover, excessively complex neural networks are not conducive to on-chip implementation and clinical applications. This study addresses the challenges of high misdiagnosis rates and significant hardware costs inherent in traditional AD detection techniques. A novel and efficient AD detection framework based on a recurrent computational strategy is proposed. The framework harnesses an Artificial Neural Network (ANN) embedded within a System on Chip (SoC) to perform sophisticated Electroencephalogram (EEG) analysis. The approach began by employing a reduced IEEE754 single-precision encoding method to hardware-encode the preprocessed EEG data, thereby minimizing the memory storage area. Next, data remapping techniques were utilized to ensure the continuity of the input data read addresses and reduce the memory access pressure during neural network computations. Subsequently, hierarchical and Processing Element (PE) reuse technologies were leveraged to perform the multiply-accumulate operations of the ANN. Finally, a step function was chosen to establish binary classification circuits dedicated to AD detection. Experimental results indicate that the optimized SoC achieves a 70 % reduction in area and a 50 % reduction in power consumption compared to traditional designs. For various neural network models, the detection model proposed in this paper incurs less overhead, with a training speed 3 to 4 times faster than other traditional models, and a high accuracy rate of 98.53 %.

Software Optimization and Design Methodology for Low Power Computer Vision Systems

This tutorial paper addresses a low power computer vision system as an example of a growing application domain of neural networks, exploring various technologies developed to enhance accuracy within the resource and performance constraints imposed by the hardware platform. Focused on a given hardware platform and network model, software optimization techniques, including pruning, quantization, low-rank approximation, and parallelization, aim to satisfy resource and performance constraints while minimizing accuracy loss. Due to the interdependence of model compression approaches, their systematic application is crucial, as evidenced by winning solutions in the Lower Power Image Recognition Challenge (LPIRC) of 2017 and 2018. Recognizing the typical heterogeneity of processing elements in contemporary hardware platforms, the effective utilization through parallelizing neural networks emerges as increasingly vital for performance enhancement. The paper advocates for a more impactful strategy—designing a network architecture tailored to a specific hardware platform. For detailed information on each technique, the paper provides corresponding references.

A Novel Two-Level Protection Scheme against Hardware Trojans on a Reconfigurable CNN Accelerator

With the boom in artificial intelligence (AI), numerous reconfigurable convolution neural network (CNN) accelerators have emerged within both industry and academia, aiming to enhance AI computing capabilities. However, this rapid landscape has also witnessed a rise in hardware Trojan attacks targeted at CNN accelerators, thereby posing substantial threats to the reliability and security of these reconfigurable systems. Despite this escalating concern, there exists a scarcity of security protection schemes explicitly tailored to counteract hardware Trojans embedded in reconfigurable CNN accelerators, and those that do exist exhibit notable deficiencies. Addressing these gaps, this paper introduces a dedicated security scheme designed to mitigate the vulnerabilities associated with hardware Trojans implanted in reconfigurable CNN accelerators. The proposed security protection scheme operates at two distinct levels: the first level is geared towards preventing the triggering of the hardware Trojan, while the second level focuses on detecting the presence of a hardware Trojan post-triggering and subsequently neutralizing its potential harm. Through experimental evaluation, our results demonstrate that this two-level protection scheme is capable of mitigating at least 99.88% of the harm cause by three different types of hardware Trojan (i.e., Trojan within RI, MAC and ReLU) within reconfigurable CNN accelerators. Furthermore, this scheme can prevent hardware Trojans from triggering whose trigger signal is derived from a processing element (PE). Notably, the proposed scheme is implemented and validated on a Xilinx Zynq XC7Z100 platform.

A fast and efficient data reuse scheme for HEVC Integer Motion Estimation hardware architecture

ABSTRACT High-Efficiency Video Coding (HEVC) is a video compression standard designed to improve video compression efficiency compared to its predecessor, Advanced Video Coding (AVC). HEVC provides approximately twice the compression efficiency compared to the AVC. In the HEVC system, the most computational complexity module is the Motion Estimation (ME). ME module helps reduce redundancy by compensating for motion during video compression. However, the computational complexity makes it a bottleneck in the design of high-resolution video encoders. This paper proposes an efficient architecture for the Integer ME (IME) module of the HEVC encoder. The proposed architecture introduces an efficient memory usage scheme to support the Full Search motion search algorithm. The full pipeline architecture includes 4096 Processing Elements (PE) and an adder tree to compute the Sum of Absolute Difference (SAD) for every Prediction Unit (PU) partition. The proposed architecture was designed and implemented on Xilinx Virtex-7 XC7VX550T FPGA. Our design achieved up to 275 FPS and approximately 10 FPS at 4 K video for the Search Regions of 32 × 16 and 128 × 128 pixels, respectively.

Building an Analog Circuit Synapse for Deep Learning Neuromorphic Processing

In this article, we propose a circuit to imitate the behavior of a Reward-Modulated spike-timing-dependent plasticity synapse. When two neurons in adjacent layers produce spikes, each spike modifies the thickness in the shared synapse. As a result, the synapse’s ability to conduct impulses is controlled, leading to an unsupervised learning rule. By introducing a reward signal, reinforcement learning is enabled by redirecting the growth and shrinkage of synapses based on signal feedback from the environment. The proposed synapse manages the convolution of the emitted spike signals to promote either the strengthening or weakening of the synapse, represented as the resistance value of a memristor device. As memristors have a conductance range that may differ from the available current input range of typical CMOS neuron designs, the synapse circuit can be adjusted to regulate the spike’s amplitude current to comply with the neuron. The circuit described in this work allows for the implementation of fully interconnected layers of neuron analog circuits. This is achieved by having each synapse reconform the spike signal, thus removing the burden of providing enough power from the neurons to each memristor. The synapse circuit was tested using a CMOS analog neuron described in the literature. Additionally, the article provides insight into how to properly describe the hysteresis behavior of the memristor in Verilog-A code. The testing and learning capabilities of the synapse circuit are demonstrated in simulation using the Skywater-130 nm process. The article’s main goal is to provide the basic building blocks for deep neural networks relying on spiking neurons and memristors as the basic processing elements to handle spike generation, propagation, and synaptic plasticity.

An In-Memory-Computing Structure with Quantum-Dot Transistor Toward Neural Network Applications: From Analog Circuits to Memory Arrays

The rapid advancements in artificial intelligence (AI) have demonstrated great success in various applications, such as cloud computing, deep learning, and neural networks, among others. However, the majority of these applications rely on fast computation and large storage, which poses significant challenges to the hardware platform. Thus, there is a growing interest in exploring new computation architectures to address these challenges. Compute-in-memory (CIM) has emerged as a promising solution to overcome the challenges posed by traditional computer architecture in terms of data transfer frequency and energy consumption. Non-volatile memory, such as Quantum-dot transistors, has been widely used in CIM to provide high-speed processing, low power consumption, and large storage capacity. Matrix-vector multiplication (MVM) or dot product operation is a primary computational kernel in neural networks. CIM offers an effective way to optimize the performance of the dot product operation by performing it through an intertwining of processing and memory elements. In this paper, we present a novel design and analysis of a Quantum-dot transistor (QDT) based CIM that offers efficient MVM or dot product operation by performing computations inside the memory array itself. Our proposed approach offers energy-efficient and high-speed data processing capabilities that are critical for implementing AI applications on resource-limited platforms such as portable devices.

Blockchain based secret key management for trusted platform module standard in reconfigurable platform

SummaryThe growing sophistication of cyber attacks, vulnerabilities in high computing systems and increasing dependency on cryptography to protect our digital data, make it more important to keep secret keys safe and secure. A few major issues of secret keys, like incorrect use of keys, inappropriate storage of keys, inadequate protection of keys, insecure movement of keys, lack of audit logging, insider threats and nondestruction of keys can compromise the whole security system severely. In this work, we propose a field programmable gate array (FPGA)‐based trusted platform module (TPM) framework for operating system companies and OS users, utilizing blockchain to address NIST‐recommended secret key management issues. The security processor used in OS user machines is partitioned into three areas such that processor area, confidential area, and crypto area. The isolated secret key memory in confidential area, along with a private blockchain (BC) can log the life cycle of secret keys of TPM standard. We have also implemented a special custom bus interconnect, which receives custom crypto instructions from Processing Element (PE). During the execution of crypto instructions, the architecture ensures that secret keys are present in confidential area and crypto area but never in the processor area. The movements of secret keys between confidential area, and crypto area are recorded cryptographically after the proper authentication process controlled by the proposed hardware‐based private BC framework. To the best of our knowledge, this work is the first attempt to implement a blockchain‐based framework between OS company and OS users to address NIST recommended secret key management issues of TPM standard hardware environment. The additional cost of resource usage and timing complexity we spent to implement the proposed idea is nominal. The proposed architecture is implemented with Xilinx EDA tool using FPGA board.

Edge2LoRa: Enabling edge computing on long-range wide-area Internet of Things

Long-Power Wide Area Networks (LPWAN) is a low-cost solution to deploy very-large scale Internet of Things (IoT) infrastructures with minimal requirements following a classic producer/consumer model. Inevitably such deployments will require a shift towards low-latency, distributed and collaborative data aggregation models. The cloud edge computing continuum (CECC) has been proposed as an evolution of the traditional central ultra-high-end processing cloud into a continuum of collaborative processing elements distributed from the cloud to the network edge. Until today, incorporating existing centralized and monolithic LPWAN architectures in the CECC faces multiple security-related implications. We propose Edge2LoRa, a complete secure solution to incorporate LPWAN architectures in CECC enabling faster data processing while reducing the transmission of sensitive data. It improves network performance through data pre-processing, traffic flow optimization, and real-time local analysis. Edge2LoRa gradually transform existing LPWAN deployments into agile and versatile infrastructures that enable the seamless and efficient processing of data throughout the CECC while guaranteeing service continuity and full-backwards compatibility. We implement Edge2LoRa in hardware compliant with the Things Stack and the LoRaWAN v1.0.4 and v1.1. We evaluate the performance in terms of networking and computing resource utilization, quality of service and security. The results provide a clear indication of the improvements to public and private LoRaWAN infrastructures without any disruption or service degradation for existing legacy services. In public LoRaWAN deployments where large-scale IoT data streams drive big data analytics, we demonstrate core network bandwidth usage reductions of up to 90% and data processing latency improvements by a ×10 factor.

A Novel Instruction Driven 1-D CNN Processor for ECG Classification.

Electrocardiography (ECG) has emerged as a ubiquitous diagnostic tool for the identification and characterization of diverse cardiovascular pathologies. Wearable health monitoring devices, equipped with on-device biomedical artificial intelligence (AI) processors, have revolutionized the acquisition, analysis, and interpretation of ECG data. However, these systems necessitate AI processors that exhibit flexible configuration, facilitate portability, and demonstrate optimal performance in terms of power consumption and latency for the realization of various functionalities. To address these challenges, this study proposes an instruction-driven convolutional neural network (CNN) processor. This processor incorporates three key features: (1) An instruction-driven CNN processor to support versatile ECG-based application. (2) A Processing element (PE) array design that simultaneously considers parallelism and data reuse. (3) An activation unit based on the CORDIC algorithm, supporting both Tanh and Sigmoid computations. The design has been implemented using 110 nm CMOS process technology, occupying a die area of 1.35 mm2 with 12.94 µW power consumption. It has been demonstrated with two typical ECG AI applications, including two-class (i.e., normal/abnormal) classification and five-class classification. The proposed 1-D CNN algorithm performs with a 97.95% accuracy for the two-class classification and 97.9% for the five-class classification, respectively.

Enhancing Computation-Efficiency of Deep Neural Network Processing on Edge Devices through Serial/Parallel Systolic Computing

In recent years, deep neural networks (DNNs) have addressed new applications with intelligent autonomy, often achieving higher accuracy than human experts. This capability comes at the expense of the ever-increasing complexity of emerging DNNs, causing enormous challenges while deploying on resource-limited edge devices. Improving the efficiency of DNN hardware accelerators by compression has been explored previously. Existing state-of-the-art studies applied approximate computing to enhance energy efficiency even at the expense of a little accuracy loss. In contrast, bit-serial processing has been used for improving the computational efficiency of neural processing without accuracy loss, exploiting a simple design, dynamic precision adjustment, and computation pruning. This research presents Serial/Parallel Systolic Array (SPSA) and Octet Serial/Parallel Systolic Array (OSPSA) processing elements for edge DNN acceleration, which exploit bit-serial processing on systolic array architecture for improving computational efficiency. For evaluation, all designs were described at the RTL level and synthesized in 28 nm technology. Post-synthesis cycle-accurate simulations of image classification over DNNs illustrated that, on average, a sample 16 × 16 systolic array indicated remarkable improvements of 17.6% and 50.6% in energy efficiency compared to the baseline, with no loss of accuracy.