Processor Design Research Articles

Thermal design of a frequency hopping processor

Abstract To solve the difficult problems in the thermal design of a new frequency-hopping processor, such as high heat consumption, concentrated local heat flux of the device, and large thermal resistance, a thermal design scheme was proposed to optimize the structure design and enhance the thermal conductivity of PCB board. At the same time, a combined scheme of copper water heat pipe-thermal expansion plate was used. Flotherm was used for thermal simulation and a thermal balance experiment under vacuum conditions was designed. Then the temperature of the frequency-hopping processor was measured experimentally to further verify the rationality of the design scheme. The combined scheme of copper water heat pipe-thermal expansion plate will guide the thermal design of this type of frequency hopping processor.

Design of Low Power Control Unit for RISC-V Processor Core

This research work focuses on the development of a low-power decode logic for a RISC-V processor core with specifications. The goal is to create a controller that performs all six groups of instruction formats outlined in the RV32I Base Integer Instruction Set. The control unit is designed to decode a total of 13 instruction sets, allowing for a comprehensive range of operations. A single instruction pipeline approach is implemented in the design to optimize performance. The synthesis of the design is carried out using the 32 nm standard library, resulting in a maximum operating frequency of 666.67 MHz. To further enhance power efficiency, clock gating techniques are employed, leading to a reduction in power consumption by 18.72 % from 112.15 µW to 91.45 µW. Additionally, the layout of the design is optimized, resulting in an area of 354.74 mm2. The successful development of this low-power decode logic demonstrates its potential for integration into larger RISC-V processor cores. Future enhancements can include expanding the instruction decoding capability to encompass the full range of 47 instructions in the RV32I Base Integer Instruction Set, as well as exploring additional pipeline stages to further improve performance. The results achieved in this project contribute to the ongoing pursuit of power-efficient and high-performance processor designs based on the RISC-V architecture.

Design of Variation Tolerant Near Threshold Processor Using Artificial Ecosystem Optimizer with Hybrid Deep Learning

Recently, several applications of data mining and pattern recognition require statistical signal processing (SP) to be used and machine learning (ML) techniques for processing massive data volumes in energy-constrained contexts. It is developing interest in executing difficult ML techniques like convolutional neural network (CNN) on lesser power embedding environments to allow on-device learning and inference. Several of these platforms are that utilized as lower power sensor nodes with lower to medium throughput conditions. Near threshold processor (NT) proposals are appropriate for these applications where as affected by a vital enhancement in variants. This research offers an Artificial Ecosystem Optimizer with Hybrid Deep Learning for Variation-Tolerant Near-Threshold Processor (AEOHDL-VTNT). The inference of embedded systems at the network edge serves as the foundation for the AEOHDL-VTNT approach that is being discussed. In the described AEOHDL-VTNT approach involves two primary processes: HDL-based VTNT design and hyper parameter tweaking. Initially, the HDL model is used to develop the VTNT. Next, in the second step, the AEO method is used for hyper parameter tweaking of the HDL model, which improves the HDL's overall performance. A number of simulations were carried out to show how the AEOHDL-VTNT approach improved performance. The simulation results showed that the AEOHDL-VTNT approach outperformed other models.

Structural design and thermodynamic analysis of high heat dissipation on board computers based on VPX architecture

Abstract Due to the excellent compatibility of VPX in the international aerospace embedded specifications, VPX specifications are often employed in the design of payload processors for space applications. This paper introduces the design features of a 3U hot-swappable chassis based on the VPX specification, focusing on overall layout and thermal design. To fully utilize the performance of the VPX platform, a modular design is adopted in the overall layout, allowing different functional modules to be freely combined to meet various requirements. The chassis reserves a position for a computing module, facilitating future expansions. In the thermal design, considering the high-density modules inside the chassis, heat pipes are employed to rapidly transfer heat to the chassis rails and outer shell, enhancing the overall heat dissipation capability. Thermal simulation analysis using FLOTHERM software validates that the optimized thermal design meets the first-level derating standards for spacecraft. The finite element analysis results show that the fundamental frequency of the entire machine is 215 Hz, and all indicators meet the design requirements.

Integrating error correction and detection techniques in RISC-V processor microarchitecture for enhanced reliability

An essential consideration in processor design is ensuring reliability, particularly in demanding environments such as outer space and nuclear plants. To mitigate the effects of errors and enable error recovery, processors need to incorporate fault tolerance techniques. One common type of error is SEU (Single Event Upset), which affects various microelectronic devices including microprocessors, microcontrollers, and semiconductor memory devices. While error mitigation techniques have been developed for processors based on architectures like ARM (Advanced RISC Machine) and MIPS (Million Instructions Per Second), there is a gap in research for open-source ISAs (Instruction Set Architecture) like RISC-V, which this paper aims to address. This paper focuses on designing a fault-tolerant microarchitecture for a RISC-V processor that can correct one-bit errors, detect up to two-bit errors, and integrate lockstep and pipeline rollback features at a lower LUTs (Look Up Tables) consumption by re-using the same hardware pipeline for error mitigation and recovery through instruction mimicking. By incorporating these features, the proposed approach enhances the system’s fault tolerance by detecting and correcting errors caused by transient events and achieves a lower effective die size upon realization compared to contemporary works. The proposed microarchitecture design was simulated and synthesized using the Vivado Design Suite 2023.1 and implemented on a Zynq 7000 SoC ZC702 Evaluation Kit.

Implementation of Application Specific Instruction set Processor for Approximate Computing

The performance, energy efficiency, power dissipation, and cost of the processors used in Internet of Things edge devices can be improved by introducing approximate computing. In this paper, the design and synthesis of an application-specific instruction set processor for approximate computing is proposed. Approximate computing can also be defined by using Artificial Intelligence-based technique like the Fractal theory and Inconsistent Information System. Application Specific Instruction Set Processor is a new processor design area and is used to design a new instruction set using existing processor configuration available on the EDA tool. From the results, it is observed that significant improvement is achieved in processor performance using the TIE application as compared to without the TIE application which is applied to user-designed instruction.

Design and Implementation of a Novel Hybrid Quantum-Classical Processor for Enhanced Computation Speed

Design and Implementation of a Novel Hybrid Quantum-Classical Processor for Enhanced Computation Speed

Enhanced CPU Design for SDN Controller.

Software-Defined Networking (SDN) revolutionizes network management by decoupling control plane functionality from data plane devices, enabling the centralized control and programmability of network behavior. This paper uses the ternary system to improve the Central Processing Unit (CPU) inside the SDN controller to enhance network management. The Multiple-Valued Logic (MVL) circuit shows remarkable improvement compared to the binary circuit regarding the chip area, propagation delay, and energy consumption. Moreover, the Carbon Nanotube Field-Effect Transistor (CNTFET) shows improvement compared to other transistor technologies regarding energy efficiency and circuit speed. To the best of our knowledge, this is the first time that a ternary design has been applied inside the CPU of an SDN controller. Earlier studies focused on Ternary Content-Addressable Memory (TCAM) in SDN. This paper proposes a new 1-trit Ternary Full Adder (TFA) to decrease the propagation delay and the Power-Delay Product (PDP). The proposed design is compared to the latest 17 designs, including 15 designs that are 1-trit TFA CNTFET-based, 2-bit binary FA FinFET-based, and 2-bit binary FA CMOS-based, using the HSPICE simulator, to optimize the CPU utilization in SDN environments, thereby enhancing programmability. The results show the success of the proposed design in reducing the propagation delays by over 99% compared to the 2-bit binary FA CMOS-based design, over 78% compared to the 2-bit binary FA FinFET-based design, over 91% compared to the worst-case TFA, and over 49% compared to the best-case TFAs.

CAL: Core-Aware Lock for the big.LITTLE Multicore Architecture

The concept of “all cores are created equal” has been popular for several decades due to its simplicity and effectiveness in CPU (Central Processing Unit) design. The more cores the CPU has, the higher performance the host owns and the higher the power consumption. However, power-saving is also one of the key goals for servers in data centers and embedded devices (e.g., mobile phones). The big.LITTLE multicore architecture, which contains high-performance cores (namely big core) and power-saved cores (namely little core), has been developed by ARM (Advanced RISC Machine) and Intel to trade off performance and power efficiency. Facing the new heterogeneous computing architecture, the traditional lock algorithms, which are designed to run on homogeneous computing architecture, cannot work optimally as usual and drop into the performance issue for the difference between big core and little core. In our preliminary experiment, we observed that, in the big.LITTLE multicore architecture, all these lock algorithms exhibit sub-optimal performance. The FIFO-based (First In First Out) locks experience throughput degradation, while the performance of competition-based locks can be divided into two categories. One of them is big-core-friendly, so their tail latency increases significantly; the other is little-core-friendly. Not only does the tail latency increase, but the throughput is also degraded. Motivated by this observation, we propose a Core-Aware Lock for the big.LITTLE multicore architecture named CAL, which keeps each core having an equal opportunity to access the critical section in the program. The core idea of the CAL is to take the slowdown ratio as the matric to reorder lock requests of these big and little cores. By evaluating benchmarks and a real-world application named LevelDB, CAL is confirmed to achieve fairness goals in heterogeneous computing architecture without sacrificing the performance of the big core. Compared to several traditional lock algorithms, the CAL’s fairness has increased by up to 67%; and Its throughput is 26% higher than FIFO-based locks and 53% higher than competition-based locks, respectively. In addition, the tail latency of CAL is always kept at a low level.

An energy-efficient 32-bit bit-parallel superconducting SFQ specialized processor

As the demand for energy efficiency rises, researchers are increasingly prioritizing the quest for energy-efficient chip design. Superconducting SFQ circuit technology has garnered attention due to its ultra-high speed and low power consumption characteristics. In this paper, we propose a layout method called Maximum Operating Frequency Constraint (MOFC) for SFQ circuit design. Using this method, we demonstrated a 32-bit bit-parallel string-matching processor fabricated based on SIMIT-Nb03P technology, which holds practical value. The MOFC method focuses on achieving high bit-width processor design within constrained area cost in SFQ circuits, contributing to less energy consumption. To the best of our knowledge, this represents the first demonstrated instance of a superconducting SFQ chip achieving successful internal 32-bit data parallel processing. Our chip has been fabricated and tested, revealing not only its capability for 32-bit bit-parallel processing at a high speed of 12 GHz but also its achievement of an energy efficiency ratio of up to 251 GOPS/W.

FPGA-Based Acceleration of Polar-Format Algorithm for Video Synthetic-Aperture Radar Imaging

This paper presents a polar-format algorithm (PFA)-based synthetic-aperture radar (SAR) processor that can be mounted on a small drone to support video SAR (ViSAR) imaging. For drone mounting, it requires miniaturization, low power consumption, and high-speed performance. Therefore, to meet these requirements, the processor design was based on a field-programmable gate array (FPGA), and the implementation results are presented. The proposed PFA-based SAR processor consists of both an interpolation unit and a fast Fourier transform (FFT) unit. The interpolation unit uses linear interpolation for high speed while occupying a small space. In addition, the memory transfer is minimized through optimized operations using SAR system parameters. The FFT unit uses a base-4 systolic array architecture, chosen from among various fast parallel structures, to maximize the processing speed. Each unit is designed as a reusable block (IP core) to support reconfigurability and is interconnected using the advanced extensible interface (AXI) bus. The proposed PFA-based SAR processor was designed using Verilog-HDL and implemented on a Xilinx UltraScale+ MPSoC FPGA platform. It generates an image 2048 × 2048 pixels in size within 0.766 s, which is 44.862 times faster than that achieved by the ARM Cortex-A53 microprocessor. The speed-to-area ratio normalized by the number of resources shows that it achieves a higher speed at lower power consumption than previous studies.

Lightweight ASIP Design for Lattice-Based Post-quantum Cryptography Algorithms

AbstractLattice-based cryptography (LBC) algorithms are considered suitable candidates for post-quantum cryptography (PQC), as they dominate the standardization process put forward by the National Institute of Standards and Technology (NIST). Indeed, three of the four key encapsulation mechanism (KEM) algorithms in the third round of the process are based on computationally hard lattice problems. On the other hand, there is an urgent need for processor designs that can run PQC algorithms efficiently, especially for embedded systems. This study presents an application-specific instruction set processor (ASIP) design for the Kyber, Saber, and NewHope algorithms based on transport triggered architecture (TTA). Custom hardware accelerators are added to the baseline processor architecture for computation-intensive steps without applying any software optimization to the reference code. We compared FPGA and ASIC implementations of our design with the prominent RISC-V cores and instruction set extension studies in the literature. According to the results, the proposed design offers greater efficiency, better performance, and lower resource utilization than its competitors in most cases.

Design and implementation of a configurable parallel FFT processor in onboard SAR imaging system based on FPGA

Design and implementation of a configurable parallel FFT processor in onboard SAR imaging system based on FPGA

THE DESIGN OF THE PIPELINED RISC-V PROCESSOR WITH THE HARDWARE COPROCESSOR OF DIGITAL SIGNAL PROCESSING

Context. The digital signal processing is applied in many fields of science, technology and human activity. One of the ways of implementing algorithms of digital signal processing is the development of coprocessors as an integral part of well-known architectures.
 In the case of developing a pipelined device, the presented approach will allow to use software and hardware tools of the appropriate architecture, provide the faster execution of signal processing algorithms, reduce the number of cycles and memory accesses.
 Objective. Objectives are design and characterization study of a pipelined RISC-V processor and coprocessor of digital signal processing which performs fast Fourier transform.
 Method. Analyzing technical literature and existing decisions allow to assess advantages and disadvantages of modern developments and on the basis of which to form the relevance of the selected topic. Model designing and simulation results allow to examine a model efficiency, to determine weak components’ parts and to improve model parameters.
 Results. The pipelined RISC-V processor has been designed which executes a basic set of instructions. Execution time of assembly program on the single-cycled and the pipelined processors have been analyzed. According to the results, the test program on the pipelined processor is executed in 29 cycles, while on the single-cycle processor it takes 60 cycles. The structure of the coprocessor for the fast Fourier transform algorithm and a set of processor instructions that allow working with the coprocessor have been developed. The number of cycles of the coprocessor based on Radix-2 fast Fourier transform algorithm for 512 points is 2358 cycles, and for 1024 points is 5180 cycles.
 Conclusions. Conducted researches and calculations have showed that the application of the developed hardware coprocessor reduces the fast Fourier transform algorithm execution time and the load of the pipelined processor during calculations.

Technological Prerequisites and Consequences of Ubiquitous Computing and Networking in Resurrecting Extinct Computers

The passage discusses the previous days of computing, highlighting the experiment of alternative processor designs, such as the Connection Machine (CM1). The CM1 was a unique architecture consisting of 65536 individual one-bit processors interconnected as a 12dimensional hyper-cube. Despite its innovative design, the machine faced challenges and eventually faded into obscurity. To preserve this piece of computing history, efforts have been made to develop a cycle accurate simulator of the Connection-Machine and create an RTL (Register Transfer Level) hardware description of its building block chip. These preservation steps are crucial in ensuring that the legacy of the Connection Machine is not forgotten. The evaluate of the Connection Machine performance yields mixed result. While it demonstrates impressive performance on certain tasks such as a breadth first search algorithm with a remarkably low cycle-per-element ratio, its limitations become apparent in other applications, particularly those in linear algebra. Factors like the 1 bit word size and latency of messages passing impose constraints on performance, especially in traditionally parallelizable applications. Overall, the passage underscores the importance of understanding and preserving the history of computing, including the exploration of alternative architectures like the Connection Machine, despite their eventual challenges and limitations.

Design and Implementation of a Real-Time Imaging Processor for Spaceborne Synthetic Aperture Radar With Configurability

Design and Implementation of a Real-Time Imaging Processor for Spaceborne Synthetic Aperture Radar With Configurability

Vision Transformer-based overlay processor for Edge Computing

Accelerating Visual Neural Networks in Edge Computing environments is crucial for processing image and video data. Visual Neural Networks, including Convolutional Neural Networks and Vision Transformers, are central to image recognition, video analysis, and object detection tasks. Deploying these networks on edge devices and accelerating them can significantly enhance data processing speed and efficiency. The large number of parameters, complex computational flows, and various structural variants of Transformer models present both opportunities and challenges. We propose Vis-TOP (Vision Transformer Overlay Processor), an overlay processor designed for all types of Vision Transformer models. Vis-TOP, distinct from coarse-grained general-purpose accelerators like GPUs and fine-grained custom designs, encapsulates Vision Transformer characteristics into a three-layer, two-level mapping structure, enabling flexible model switching without hardware architecture modifications. Concurrently, we designed a corresponding instruction bundle and hardware architecture within this mapping structure. We implemented the overlay processor design on the ZCU102 after quantizing the Swin Transformer model to 8-bit fixed points (fix_8). Experimentally, our throughput surpasses GPU implementation by 1.5 times. Our throughput per DSP is 2.2 to 11.7 times higher than that of existing Transformer-like accelerators. Overall, our approach satisfies real-time AI requirements in resource consumption and inference speed. Vis-TOP offers a cost-effective image processing solution for Edge Computing on reconfigurable devices, enhancing computational resource utilization, saving data transfer time and costs, and reducing latency.

Basic Computer Architecture and Quantitative Techniques in Computer Design Instruction Pipeline ,Arithmetic Pipeline, Hazards ,Exception and Interrupts

We talk about the quantitative approach to computer architecture in this paper. We also go over Amdahl's Law, scalability, parallelism, and the principle of locality in relation to quantitative measurement. We also demystify computer architecture by focusing on smart technical design and cost- performance-power trade-offs. In the context of computer architecture, we think the field has continued to develop and move toward the exacting quantitative foundation of venerable scientific and technical disciplines. The pipelining principles in processor design are the focus of this study.The fundamentals of the instruction pipeline are covered, and an example-based explanation of how to reduce a pipeline delay is provided.The primary goal is to comprehend how a processor's pipeline functions.The different risks that lead to pipeline deterioration are described, along with ways to reduce them. Architecture-based development environments are emerging as a useful tool for building reliable distributed systems. By means of the abstract characterization of intricate software Software reuse and evolution are encouraged in terms of system topologies that involve the interface- level interaction of software parts. Furthermore, as evidenced by research findings in the field of software architecture, it becomes possible to offer formal annotations for the accurate characterization of configuration behavior together with related CASE tools for automated analysis. Nevertheless, while being essential to attaining software resilience, software fault tolerance—and specifically exception management in that context—has received little attention. Keywords: Instruction Pipeline ,Arithmetic Pipeline, Hazards

Multi-Voltage Design of RISC Processor for Low Power Application: A Survey

Multi-Voltage Design of RISC Processor for Low Power Application: A Survey

Design and Evaluation of Open-Source Soft-Core Processors

The advantage of FPGAs lies in their ability to implement a fully hardware solution for interfacing with various input/output (I/O) devices. Each block can work in parallel with all the others, simplifying the satisfaction of timing constraints. However, this hardware utilization consumes FPGA resources that could otherwise be allocated to the primary project. An alternative involves employing a small “soft-core” processor to implement I/O in software. With the goal of designing and evaluating a new tiny soft-core processor optimized for FPGA resources in I/O, a novel processor named Baby8 is developed. It is an 8-bit CISC soft-core processor optimized for reduced FPGA resources, including program size for 8-bit applications. The number of instructions is not large, but any instruction can access arbitrary memory locations. The performance and resource utilization of the newly designed processor are evaluated and compared with a variety of other soft-core processors. The results demonstrate its competitive performance, achieving an average maximum clock frequency of approximately 57 MHz and a power consumption of around 2 mW. Furthermore, it conserves nearly half of the FPGA resources in implementation.