Processor Cycles Research Articles

Towards a Lightweight Classifier to Detect Hypovolemic Shock.

Predicting the ability of an individual to compensate for blood loss during hemorrhage and detect the likely onset of hypovolemic shock is necessary to permit early clinical intervention. Towards this end, the compensatory reserve metric (CRM) has been demonstrated to directly correlate with an individual's ability to maintain compensatory mechanisms during loss of blood volume from onset (one-hundred percent health) to exsanguination (zero percent health). This effort describes a lightweight, three-class predictor (good, fair, poor) of an individual's compensatory reserve using a linear support-vector machine (SVM) classifier. A moving mean filter of the predictions demonstrates a feasible model for implementation of real-time hypovolemia monitoring on a wearable device, requiring only 408 bytes to store the models' coefficients and minimal processor cycles to complete the computations.

A Comparative Study of Smart THD-Based Fault Protection Techniques for Distribution Networks

The integration of Distributed Generators (DGs) into distribution systems (DSs) leads to more reliable and efficient power delivery for customers. However, the possibility of bi-directional power flow creates new technical problems for protection schemes. This poses a threat to conventional strategies because the relay settings have to be adjusted depending on the network topology and operational mode. As a solution, it is important to develop novel fault protection techniques to ensure reliable protection and avoid unnecessary tripping. In this regard, Total Harmonic Distortion (THD) can be used as a key parameter for evaluating the grid’s waveform quality during fault events. This paper presents a comparison between two DS protection strategies that employ THD levels, estimated amplitude voltages, and zero-sequence components as instantaneous indicators during the faults that function as a kind of fault sensor to detect, identify, and isolate faults. The first method uses a Multiple Second Order Generalized Integrator (MSOGI) to obtain the estimated variables, whereas the second method uses a single SOGI for the same purpose (SOGI-THD). Both methods rely on communication lines between protective devices (PDs) to facilitate coordinated protection. The effectiveness of these methods is assessed by using simulations in MATLAB/Simulink considering various factors such as different types of faults and DG penetrations, different fault resistances and fault locations in the proposed network. Moreover, the performance of these methods is compared with conventional overcurrent and differential protections. The results show that the SOGI-THD method is highly effective in detecting and isolating faults with a time interval of 6–8.5 ms using only three SOGIs while requiring only 447 processor cycles for execution. In comparison to other protection methods, the SOGI-THD method exhibits a faster response time and a lower computational burden. Furthermore, the SOGI-THD method is robust to harmonic distortion, as it considers pre-existing harmonic content before the fault and avoids interference with the fault detection process.

GENERATION OF PSEUDORANDOM SEQUENCES ON MICROCONTROLLERS WITH LIMITED COMPUTATIONAL RESOURCES, ENTROPY SOURCES, AND STATISTICAL PROPERTIES TESTING

Traditional encryption algorithms cannot be implemented on Internet of Things (IoT) devices due to their constrained computational resources. This necessitates the search and development of cryptographic solutions for securing data processed and transmitted by such devices. When encrypting data on devices with limited computational resources, simple encryption algorithms based on elementary bitwise operations, such as bitwise modulo-2 addition (XOR), can be utilized since these operations execute in a single processor cycle and do not require complex computations. However, a drawback of such operations is their invertibility—knowing the encryption key enables easy decryption by applying the same operation to the ciphertext. Ensuring the reliability of such ciphers requires continuous generation of random encryption keys.This work explores the functionality of the linear congruential method for generating sequences of random numbers. Several entropy sources available on microcontrollers are presented for the initial generator value, along with proposed algorithms for collecting initial data from these sources. The use of noise from unconnected pins of the analog-to-digital converter is suggested as the primary entropy source, while the uninitialized area of the microcontroller’s random-access memory serves as an additional source. A method for generating random sequences using the specified entropy sources is implemented and the algorithm’s performance is evaluated, specifically the key characteristic—randomness of the encryption key. The NIST STS 800-22 test suite is employed for evaluation. In all tests, the random sequence generation algorithm demonstrated results confirming the hypothesis that the sequence can be considered random.

A hardware accelerator for IEEE 802.15.4 Time-Slotted Channel Hopping transceiver

Time-Slotted Channel Hopping (TSCH), an operational mode of the IEEE 802.15.4e standard, imposes a high workload on the embedded processor, mainly due to its precise timing. The limited embedded processor of an edge device cannot satisfy the considerable memory footprint and computational complexity caused by functions that need precise timing in the protocol stack. Moving such duties to hardware seems to be a viable path towards offloading the processor and releasing its resource to be used for running firmware related to the implementation of the upper layers of the protocol stack as well as the application. In this work, a TSCH protocol hardware accelerator is designed and integrated within the digital baseband processor of an IEEE 802.15.4 transceiver. The whole system is implemented targeting the TSMC 65 nm technology. The designed TSCH accelerator has an efficient interface and is totally configurable by the software. It efficiently controls the transceiver, frees up embedded processor cycles, and reduces the interrupt callback to the processor. Therefore, the TSCH hardware accelerator makes it possible to use a cheaper embedded processor or to operate the processor on a lower clock speed which results in lower power consumption. The power analysis of the implemented system shows that, in the minimal setting of the TSCH accelerator, only 0.1% is added to the power consumption of the digital baseband processor. The power overhead increases to 5.6% for supporting three parallel slotframes which is a widely used TSCH setting in multi-hop networks. In return, the embedded processor is relaxed of processing TSCH timing related interrupts that are required for software-based TSCH implementation.

Gated-CNN: Combating NBTI and HCI aging effects in on-chip activation memories of Convolutional Neural Network accelerators

Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI) are two of the main reliability threats in current technology nodes. These aging phenomena degrade the transistor’s threshold voltage (Vth) over the lifetime of a digital circuit, resulting in slower transistors that eventually lead to a faulty operation when the critical paths become longer than the processor cycle time. Among all the transistors on a chip, the most vulnerable transistors to such wearout effects are those used to implement SRAM storage, since memory cells are continuously degrading. In particular, NBTI ages PMOS cell transistors when a given logic value is stored for a long period (i.e., a long duty cycle), whereas HCI ages NMOS cell transistors not only when the stored value flips but also when it is accessed. This work focuses on mitigating aging in the on-chip SRAM memories of Convolutional Neural Network (CNN) accelerators storing activations. This paper makes two main contributions. At the software level, we quantify the aging induced by current CNN benchmarks with a characterization study of duty cycle, flip, and access patterns in every activation memory cell. Based on the insights from this study, this work proposes a novel microarchitectural technique, Gated-CNN, that ensures a uniform aging degradation of every memory cell. To do so, Gated-CNN exploits power-gating and address rotation techniques tailored to the memory demands and temporal/spatial localities exhibited by CNN applications, as well as the memory organization and management of CNN accelerators. Experimental results show that, compared to a conventional design, the average Vth degradation savings are at least as much as 49% depending on the type of transistor.

Resource Allocation in 4G and 5G Networks: A Review

The advent of 4G and 5G broadband wireless networks brings several challenges with respect to resource allocation in the networks. In an interconnected network of wireless devices, users, and devices, all compete for scarce resources which further emphasizes the fair and efficient allocation of those resources for the proper functioning of the networks. The purpose of this study is to discover the different factors that are involved in resource allocation in 4G and 5G networks. The methodology used was an empirical study using qualitative techniques by performing literature reviews on the state of art in 4G and 5G networks, analyze their respective architectures and resource allocation mechanisms, discover parameters, criteria and provide recommendations. It was observed that resource allocation is primarily done with radio resource in 4G and 5G networks, owing to their wireless nature, and resource allocation is measured in terms of delay, fairness, packet loss ratio, spectral efficiency, and throughput. Minimal consideration is given to other resources along the end-to-end 4G and 5G network architectures. This paper defines more types of resources, such as electrical energy, processor cycles and memory space, along end-to-end architectures, whose allocation processes need to be emphasized owing to the inclusion of software defined networking and network function virtualization in 5G network architectures. Thus, more criteria, such as electrical energy usage, processor cycle, and memory to evaluate resource allocation have been proposed. Finally, ten recommendations have been made to enhance resource allocation along the whole 5G network architecture.

Resource Allocation in 4G and 5G Networks: A Review

The advent of 4G and 5G broadband wireless networks brings several challenges with respect to resource allocation in the networks. In an interconnected network of wireless devices, users, and devices, all compete for scarce resources which further emphasizes the fair and efficient allocation of those resources for the proper functioning of the networks. The purpose of this study is to discover the different factors that are involved in resource allocation in 4G and 5G networks. The methodology used was an empirical study using qualitative techniques by performing literature reviews on the state of art in 4G and 5G networks, analyze their respective architectures and resource allocation mechanisms, discover parameters, criteria and provide recommendations. It was observed that resource allocation is primarily done with radio resource in 4G and 5G networks, owing to their wireless nature, and resource allocation is measured in terms of delay, fairness, packet loss ratio, spectral efficiency, and throughput. Minimal consideration is given to other resources along the end-to-end 4G and 5G network architectures. This paper defines more types of resources, such as electrical energy, processor cycles and memory space, along end-to-end architectures, whose allocation processes need to be emphasized owing to the inclusion of software defined networking and network function virtualization in 5G network architectures. Thus, more criteria, such as electrical energy usage, processor cycle, and memory to evaluate resource allocation have been proposed. Finally, ten recommendations have been made to enhance resource allocation along the whole 5G network architecture.

Factoring 2048-bit RSA Integers in 177 Days with 13 436 Qubits and a Multimode Memory.

We analyze the performance of a quantum computer architecture combining a small processor and a storage unit. By focusing on integer factorization, we show a reduction by several orders of magnitude of the number of processing qubits compared with a standard architecture using a planar grid of qubits with nearest-neighbor connectivity. This is achieved by taking advantage of a temporally and spatially multiplexed memory to store the qubit states between processing steps. Concretely, for a characteristic physical gate error rate of 10^{-3}, a processor cycle time of 1 microsecond, factoring a 2 048-bit RSA integer is shown to be possible in 177days with 3D gauge color codes assuming a threshold of 0.75% with a processor made with 13 436 physical qubits and a memory that can store 28million spatial modes and 45 temporal modes with 2hours' storage time. By inserting additional error-correction steps, storage times of 1second are shown to be sufficient at the cost of increasing the run-time by about 23%. Shorter run-times (and storage times) are achievable by increasing the number of qubits in the processing unit. We suggest realizing such an architecture using a microwave interface between a processor made with superconducting qubits and a multiplexed memory using the principle of photon echo in solids doped with rare-earth ions.

HRM: Merging Hardware Event Monitors for Improved Timing Analysis of Complex MPSoCs

The performance monitoring unit (PMU) in multiprocessor system-on-chips (MPSoCs) is at the heart of the latest measurement-based timing analysis techniques in critical embedded systems. In particular, hardware event monitors (HEMs) in the PMU are used as building blocks in the process of budgeting and verifying software timing by tracking and controlling access counts to shared resources. While the number of HEMs in current MPSoCs reaches hundreds, they are read via performance monitoring counters whose number is usually limited to 4-8, thus requiring multiple runs of each experiment in order to collect all desired HEMs. Despite the effort of engineers in controlling the execution conditions of each experiment, the complexity of current MPSoCs makes it arguably impossible to completely remove the noise affecting each run. As a result, HEMs read in different runs are subject to different variability, and hence, those HEMs captured in different runs cannot be “blindly” merged. In this work, we focus on the NXP T2080 platform where we observed up to 59% variability across different runs of the same experiment for some relevant HEMs (e.g., processor cycles). We develop a HEM reading and merging (HRM) approach to join reliably HEMs across different runs as a fundamental element of any measurement-based timing budgeting and verification technique. Our method builds on order statistics and the selection of an anchor HEM read in all runs to derive the most plausible combination of HEM readings that keep the distribution of each HEM and their relationship with the anchor HEM intact.

Method for detecting and counteracting Virus Detection in BMP images

The aim of the article is to develop a method for protecting modern systems against attacks using BMP image files and HID attacks. This article describes the features of BMP format images. The method of injecting computer viruses in BMP image and attacks to overcome the means of protection. HID attacks and the possibility of combining these attacks are also considered. Features of functioning of modern means of protection IDS, IPS, antiviruses, firewalls and their shortcomings are presented. Such attacks are possible due to the fact that security tools will only analyze executable files, DLLs, Word documents, Java applets. Most of the protection tools simply do not pay attention to images or another secure file type. Because they believe, that there is no reason to spend the processor cycle on image analysis. HID devices are perceived by security tools as a simple interface between a computer and a user, therefore they are trusted. The article suggests methods for detecting viruses in BMP image files based on checking reserved fields that should be zero, matching the real file size with the value in the file header, matching the pixel size specified in the header with real. The article also offers a method to counteract HID attacks based on analysis of text input speed. Developed programs demonstrate the effectiveness of protection against the considered attacks.

Real-Time Event Handling and Preemptive Hardware RTOS Scheduling on a Custom CPU Implementation

The rapid evolution of field-programmable gate array (FPGA) devices has strongly influenced both the design methodology and development tools. This article describes an original implementation based on a hardware structure used for static and dynamic task scheduling. The proposed custom processor has hardware-implemented RTOS (HW-RTOS) features and is verified using an FPGA circuit. The solution replaces the classical stack save concept with a resource remapping mechanism that enables a new task to be executed starting with the next processor cycle. The proposed hardware scheduler enables unified management of events and interrupts, by implementing a method of attaching interrupts to tasks while ensuring the requirements of real-time systems. The robustness and performance of the proposed platform are guaranteed by the context switch operations, presence of the intertask synchronization and communication mechanisms, and by the efficient use of the multiplexed resources. Instead of saving and restoring general-purpose registers into the memory, the latency is removed by directly commuting the datapath task resources.

Adaptive Hybrid Synchronization Primitives: A Reinforcement Learning Approach

The choice of synchronization primitive used to protect shared resources is a critical aspect of application performance and scalability, which has become extremely unpredictable with the rise of multicore machines. Neither of the most commonly used contention management strategies works well for all cases: spinning provides quick lock handoff and is attractive in an undersubscribed situation but wastes processor cycles in oversubscribed scenarios, whereas blocking saves processor resources and is preferred in oversubscribed cases but adds up to the critical path by lengthening the lock handoff phase. Hybrids, such as spin-then-block and spin-then-park, tackle this problem by switching between spinning and blocking depending on the contention level on the lock or the system load. Consequently, threads follow a fixed strategy and cannot learn and adapt to changes in system behavior. To this end, it is proposed to use principles of machine learning to formulate hybrid methods as a reinforcement learning problem that will overcome these limitations. In this way, threads can intelligently learn when they should spin or sleep. The challenges of the suggested technique and future work is also briefly discussed.

Improving Correctness of Logic Circuit using Self-Healing Built-In Logic Test Module in FPGA using Dynamic Partial Reconfiguration

As cloud servers continue to receive more and more applications and data, it starts using ASIC and FPGAs as accelerators for processor intensive applications. Because of the reconfiguration nature of FPGAs, it become a good choice rather than ASIC on cloud. Encryption is an application which happens frequently on cloud and takes lot of processor cycles which can be shifted to hardware accelerator for execution. The security of hardware circuit which is transferred as bitstream to the FPGA board is of major concern for security critical applications. The article proposes a novel logic authentication module that can check the authentication or correctness of selected parts of logic circuit any time after the circuit is burned into FPGA. In the proposed work, Advanced Encryption Standard (AES) circuit parts are checked for correctness by using in-built Secure Hash Algorithm (SHA) and corrected by Dynamic Partial Reconfiguration (DPR). After the bitstream is burned into FPGA, a proposed software module can select a part or entire circuit for checking authentication with multiple sample inputs. Without the proposed method, any error after the circuit creation cannot be identified or corrected. Additionally, small faults in the circuit is corrected by DPR without loading the entire module. Totally 16 Benchmarks were created to check the correctness of the proposed system. Usage of DPR for circuit correction saves about 97% of time compared to reconfiguring the entire module.

A top down approach to enumerate α-maximal cliques in uncertain graphs

A graph is a network that can represent the communication between a variety of data elements. The data can have uncertainty, primarily due to the heterogeneity of data sources. Moreover, it is sometimes difficult to assure the existence of a link between data elements; compelling to consider the da ta as a probabilistic entity. Extracting densely connected regions from a graph is a key task of the intelligent systems. The enumeration of dense substructures in a graph can help to identify important patterns. This can have many applications in medical image processing, accident analysis, and surveillance, to name a few. One such dense substructure is a clique, where all nodes are directly connected to each other. An α-maximal clique in an uncertain graph is a clique with a minimum probability α, such that it is not a subset of any other clique of the same weight. Extracting all α-maximal cliques is an NP-Complete problem. This work focuses on reducing the time consumed to enumerate all α-maximal cliques in a graph. Another focus of this work is to reduce the CPU (Central Processing Unit) cycles for efficient enumeration of all α-maximal cliques. An algorithm is proposed that computes all weighted maximal cliques in an uncertain graph. The worst-case asymptotic time complexity of the algorithm is O(n2n). The proposed algorithm utilizes the h-index concept to form cliques with vertex degree greater than h. The algorithm builds cliques at two levels of enumeration. The first level finds the α-maximal cliques with a descending order in sizes. On each successive α-maximal clique iteration of the first level, the second level tracks and deletes all subsets of the clique. The second level is to ensure the fact that all subsets of an α-maximal clique are cliques. The proposed algorithm is compared with two recent maximal clique enumeration algorithms, namely: MULE (Maximal Uncertain Clique Enumeration) and LMC (Listing all maximal cliques in large sparse real-world graphs). Real-world benchmark uncertain graphs are utilized for the experimental evaluation. The results suggest better performance of the proposed approach in terms of the time consumption.

Application-Adaptive Performance Improvement in Mobile Systems by Using Persistent Memory

In this article, we present a performance enhancement scheme for mobile applications by adopting persistent memory. The proposed scheme supports the deadline guarantee of real-time applications like a video player, and also provides reasonable performances for non-real-time applications. To do so, we analyze the program execution path of mobile software platforms and find two sources of unpredictable time delays that make the deadline-guarantee of real-time applications difficult. The first is the irregular activation of garbage collection in flash storage and the second is the blocking and time-slice based scheduling used in mobile platforms. We resolve these two issues by adopting high performance persistent memory as the storage of real-time applications. By maintaining real-time applications and their data in persistent memory, I/O latency can become predictable because persistent memory does not need garbage collection. Also, we present a new scheduler that exclusively allocates a processor core to a real-time application. Although processor cycles can be wasted while a real-time application performs I/O, we depict that the processor utilization is not degraded significantly due to the acceleration of I/O by adopting persistent memory. Simulation experiments show that the proposed scheme improves the deadline misses of real-time applications by 90% in comparison with the legacy I/O scheme used in mobile systems.

Tight Bounds for Online Vector Scheduling

Modern data centers face a key challenge of effectively serving user requests that arrive online. Such requests are inherently multidimensional and characterized by demand vectors over multiple resources such as processor cycles, storage space, and network bandwidth. Typically, different resources require different objectives to be optimized, and $L_r$ norms of loads are among the most popular objectives considered. Furthermore, the server clusters are also often heterogeneous making the scheduling problem more challenging. To address these problems, we consider the online vector scheduling problem in this paper. Introduced by Chekuri and Khanna in 2006, vector scheduling is a generalization of classical load balancing, where every job has a vector load instead of a scalar load. The scalar problem, introduced by Graham in 1966, and its many variants (identical and unrelated machines, makespan and $L_r$ norm optimization, offline and online jobs, etc.) have been extensively studied over the last 50 years. In this paper, we resolve the online complexity of the vector scheduling problem and its important generalizations---for all $L_r$ norms and in both the identical and unrelated machines settings. For an instance with $m$ machines and $d$ dimensions, our main results are: For identical machines, we show that the optimal competitive ratio is $\Theta(\log d / \log \log d)$ by giving an online lower bound and an algorithm with an asymptotically matching competitive ratio. The lower bound is technically challenging, and is obtained via an online lower bound for the minimum monochromatic clique problem using a novel online coloring game and randomized coding scheme. Our techniques also extend to asymptotically tight upper and lower bounds for general $L_r$ norms. For unrelated machines, we show that the optimal competitive ratio is $\Theta(\log m + \log d)$ by giving an online lower bound that matches a previously known upper bound. Unlike identical machines, however, extending these results, particularly the upper bound, to general $L_r$ norms requires new ideas. In particular, we use a carefully constructed potential function that balances the individual $L_r$ objectives with the overall (convexified) min-max objective to guide the online algorithm and track the changes in potential to bound the competitive ratio.

New-age Supercomputers: Hi-Speed Networks and Information Security

The author describes computing strategic tasks that are used for ensuring defense and national security, the most important scientific, technical, biomedical and sociology tasks. Most typically, these are capability-based tasks. Supercomputers for their solution are respectively called Technical Capability, i.e. machines of extreme technical capabilities. Machines of this segment are also called High End Computers (HEC), and in our terminology - strategic supercomputers (SCs). Moving to the engineering level, author says that for tasks with good spatio-temporal work with memory, cache memory and schemes for automatically pre-loading data into the cache memory can be effectively used. This can significantly reduce the average memory access time of several hundred processor cycles to fractions of a processor cycle. Such tasks are usually called computational or cache-friendly (cach-friendly) - CF tasks. On tasks with poor spatio-temporal work with memory, the cache memory is useless, so each memory access is hundreds of processor cycles, the processor is idle because of this, and therefore the real performance is in units or even a fraction of a percent of the peak. Such tasks are historically called tasks with intensive irregular work with memory – Data intensive tasks (DIS-tasks). The given examples of spatially-temporal work with task memory and real characteristics of equipment operation in such different modes are given in order to illustrate that in practice different types of supercomputers are needed, for example, for CF- and DIS-tasks.

Analysis of World Experience in Creating Parallel Computing Systems Designed to Effectively Solve DIS-tasks

Author describes world experience in creating parallel computing systems by example Cray XE6 and network chip Gemini, designed to effectively solve Data intensive tasks (DIS-tasks). Most often, in modern supercomputers (SC), architecture options with shared (shared) memory are used to provide effective solutions to problems of high capacitive complexity, including those that contain mostly irregular work with memory. It is possible to provide support for a programming model with shared (shared) memory in various ways using hardware, as well as using virtualization software. Different options for implementing a shared memory programming model may vary in functionality and timing of memory accesses. The problem of the “<i>memory wall</i>” is that if arithmetic-logical operations take several processor cycles, then operations directly with the memory take several hundred cycles. If the memory is formed from the memories of computing nodes connected by a communication network, then the execution time of such a call includes the time of operation with the network to transfer addresses and data. This already increases the memory access time to several thousand cycles. The problem is that such delays in accessing data cause idle functional units of the processor - they cannot perform arithmetic and logical operations on data, because they simply do not exist due to the large delays in performing operations with memory.

An Aging-Aware GPU Register File Design Based on Data Redundancy

Nowadays, GPUs sit at the forefront of high-performance computing thanks to their massive computational capabilities. Internally, thousands of functional units, architected to be fed by large register files, fuel such a performance. At deep nanometer technologies, the SRAM memory cells that implement GPU register files are very sensitive to the Negative Bias Temperature Instability (NBTI) effect. NBTI ages cell transistors by degrading their threshold voltage $V_{th}$ over the lifetime of the GPU. This degradation, which manifests when a cell keeps the same logic value for a relatively long period of time, compromises the cell read stability and increases the transistor switching delay, which can lead to wrong read values and eventually exceed the processor cycle time, respectively, so resulting in faulty operation. This work proposes architectural mechanisms leveraging the redundancy of the data stored in GPU register files to attack NBTI aging. The proposed mechanisms are based on data compression, power gating, and register address rotation techniques. All these mechanisms working together balance the distribution of logic values stored in the cells along the execution time, reducing both the overall $V_{th}$ degradation and the increase in the transistor switching delays. Experimental results show that a conventional GPU register file suffers the worst case for NBTI, since a significant fraction of the cells maintain the same logic value during the entire application execution (i.e., a 100 percent ‘0’ and ‘1’ duty cycle distributions). On average, the proposal reduces these distributions by 58 and 68 percent, respectively, which translates into $V_{th}$ degradation savings by 54 and 62 percent, respectively.

Cost-Efficient Dependent Task Offloading for Multiusers

The extensive use of mobile intelligent devices, such as smart phones and tablets, induces new opportunity and challenge for computation offloading. Task offloading is an important issue in a system consisting of multiple types of devices, such as mobile intelligent devices, local edge hosts and a remote cloud server. In this paper, we study the offloading assignment of multiple applications, each one comprising several dependent tasks, in such a system. To evaluate the total cost in the offloading process, a new metric is introduced to take into account features of different devices. The remote server and local hosts are more concerned about their processors utilization, while mobile devices pay more attention to their energy. Therefore, this metric uses relative energy consumption to denote the cost of mobile devices, and evaluates the cost of the remote server and local hosts by the processor cycle number of task execution. We formulate the offloading problem to minimize the system cost of all applications within each application's completed time deadline. Since this problem is NP-hard, the heuristic algorithm is proposed to offload these dependent tasks. At first, our algorithm arranges all tasks from different applications in a priority queue considering both completed time deadline and task-dependency requirements. Then, based on the priority queue, all tasks are initially assigned to devices to protect mobile devices with low energy and make them survive in the assignment process as long as possible. At last, to obtain a better schedule realizing lower system cost, based on the relative remaining energy of mobile devices, we reassign tasks from high-cost devices to low-cost devices to minimize the system cost. Simulation results show that our proposed algorithm increases the successfully completed probability of whole applications and reduces the system cost effectively under time and energy constraints.