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Abstract
Author describes world experience in creating parallel computing systems by example Cray XE6 and network chip Gemini, designed to effectively solve Data intensive tasks (DIS-tasks). Most often, in modern supercomputers (SC), architecture options with shared (shared) memory are used to provide effective solutions to problems of high capacitive complexity, including those that contain mostly irregular work with memory. It is possible to provide support for a programming model with shared (shared) memory in various ways using hardware, as well as using virtualization software. Different options for implementing a shared memory programming model may vary in functionality and timing of memory accesses. The problem of the “<i>memory wall</i>” is that if arithmetic-logical operations take several processor cycles, then operations directly with the memory take several hundred cycles. If the memory is formed from the memories of computing nodes connected by a communication network, then the execution time of such a call includes the time of operation with the network to transfer addresses and data. This already increases the memory access time to several thousand cycles. The problem is that such delays in accessing data cause idle functional units of the processor - they cannot perform arithmetic and logical operations on data, because they simply do not exist due to the large delays in performing operations with memory.
Highlights
Most often, in modern supercomputers (SC), architecture options with shared memory are used to provide effective solutions to problems of high capacitive complexity, including those that contain mostly irregular work with memory
If the memory is formed from the memories of computing nodes connected by a communication network, the execution time of such a call includes the time of operation with the network to transfer addresses and data
The problem is that such delays in accessing data cause idle functional units of the processor - they cannot perform arithmetic and logical operations on data, because they do not exist due to the large delays in performing operations with memory
Summary
In modern supercomputers (SC), architecture options with shared (shared) memory are used to provide effective solutions to problems of high capacitive complexity, including those that contain mostly irregular work with memory. Let me briefly explain the problems of implementing shared globally addressable memory (GAS/PGAS) and ensuring its effective operation in an irregular access mode This will be required to understand and evaluate the architectural solutions of this implementation considered below. Massive multi-thread architecture is considered to be a promising processor option It provides a large stream of simultaneously accessed memory accesses, which, when executed in parallel with pipelines, will allow to achieve. The communication network must provide the ability to transmit to the memory modules a large number of short messages - requests for memory operations, and the memory must ensure their execution These solutions simultaneously take into account the need for increased resiliency, including security against information attacks. The problems of energy efficiency are mainly associated with the storage and movement of data, their solution is possible with the use of a new architecture, but, for the most part, with the use of new technologies of optoelectronics and 3D-, 4D-assembly
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