Process Window Qualification Research Articles

Systematic Hot Spots Finding By Pattern Search with Similarity

As device rule shrinks, the finding of systematic hot spots is no longer just relied on design rule checking (DRC) and lithography rule checking (LRC). There still have some unexpected systematic hot spots impact the yield of production. Using image contour extraction technique to extract the images of issued failure sites into unit clipped patterns and then do the patterns search with a similarity algorithm. Transfer these specific pattern search care areas into an in-line inspection recipe, and then prevent the failure issues happening again. Through regrouping the seed patterns after hot scan on focus exposure matrix (FEM) or process window qualification (PWQ) wafers, the exactly or similar pattern search of these seed patterns can help us to find out the unknown risky similar pattern of interests.

Application of SEM API on PWQ Wafer SEM Review

Process Window Qualification (PWQ) is a good and well-established method to find systematic defects with high sensitivity and to qualify new masks and OPC revisions. The PWQ methodology is utilized to provide an extensive defectivity characterization to determine the absolute best conditions for focus and dose. This is achieved by taking into account the defectivity in the whole die and capturing all potential systematic defects. [1] This in turn had driven to more and more SEM review on this kind of PWQ wafer in wafer foundry. Manual SEM review of this PWQ wafer is time consuming and spending a lot of man power. In this paper, a new method of reviewing the PWQ wafer with API method and how it helps to resolve the current manual SEM review limitations is introduced.

Process Window Centering for 22 nm Lithography

Process window centering (PWC) is an efficient methodology to validate or adjust and center the overall process window for a particular lithography layer by detecting systematic and random defects. The PWC methodology incorporates a defect inspection and analysis of the entire die that can be automated to provide timely results. This makes it a good compromise between focus exposure matrix, where centering is based only on critical dimension measurements of a few specific structures and process window qualification which provides very detailed defect inspection and analysis, but is more time consuming for lithography centering. This paper describes the application of the PWC methodology for 22 nm lithography centering in IBM's Albany, NY, and East Fishkill, NY, development facilities using KLA-Tencor's 28xx brightfield defect inspection system.

Accurate Systematic Hot-Spot Scoring Method and Score-Based Fixing Guidance Generation

The researches on predicting and removing of lithographic hot-spots have been prevalent in recent semiconductor industries, and known to be one of the most difficult challenges to achieve high quality detection coverage. To provide physical design implementation with designer's favors on fixing hot-spots, in this paper, we present a noble and accurate hot-spot detection method, so-called “leveling and scoring” algorithm based on weighted combination of image quality parameters (i.e., normalized image log-slope (NILS), mask error enhancement factor (MEEF), and depth of focus (DOF)) from lithography simulation. In our algorithm, firstly, hot-spot scoring function considering severity level is calibrated with process window qualification, and then least-square regression method is used to calibrate weighting coefficients for each image quality parameter. In this way, after we obtain the scoring function with wafer results, our method can be applied to future designs of using the same process. Using this calibrated scoring function, we can successfully generate fixing guidance and rule to detect hot-spot area by locating edge bias value which leads to a hot-spot-free score level. Finally, we integrate the hot-spot fixing guidance information into layout editor to facilitate the user-favorable design environment. Applying our method to memory devices of 60nm node and below, we could successfully attain sufficient process window margin to yield high mass production.