Process Latitude Research Articles

Effects of lithographic and pattern parameters on stability of feature-edge location in electron beam lithography

As the feature size continues to decrease, a high level of accuracy in achieving the feature boundary (“edge”) as designed becomes more essential. One of the reasons for any deviation in the feature-edge location is the proximity effect due to electron scattering in the resist. However, even with a perfect proximity effect correction (PEC), the nonideal process of resist development can still lead to a deviation in the edge location. In general, a higher exposure contrast over the feature edge leads to a smaller deviation in the edge location. In this study, an analytic model is employed in understanding the effects of the lithographic and pattern parameters on the deviation in the edge location due to the uncertainty in the lithographic process. Specifically, the closed-form mathematical expression of the deviation is derived in terms of the parameters that determine the exposure contrast. The results reported in this paper should be helpful in understanding better the deviation in the edge location without time-consuming repetitive simulation and developing a PEC method that enhances the stability of the feature boundaries in the written pattern, improving the process latitude.

Wide‐Bandgap Nickel Oxide with Tunable Acceptor Concentration for Multidimensional Power Devices

AbstractMultidimensional power devices can achieve performance beyond conventional limits by deploying charge‐balanced p‐n junctions. A key obstacle to developing such devices in many wide‐bandgap (WBG) and ultra‐wide bandgap (UWBG) semiconductors is the difficulty of native p‐type doping. Here the WBG nickel oxide (NiO) as an alternative p‐type material is investigated. The acceptor concentration (NA) in NiO is modulated by oxygen partial pressure during magnetron sputtering and characterized using a p‐n+ heterojunction diode fabricated on gallium oxide (Ga2O3) substrate. Capacitance and breakdown measurements reveal a tunable NA from < 1018 cm−3 to 2×1018 cm−3 with the practical breakdown field (EB) of 3.8 to 6.3 MV cm−1. This NA range allows for charge balance to n‐type region with reasonable process latitude, and EB is high enough to pair with many WBG and UWBG semiconductors. The extracted NA is then used to design a multidimensional Ga2O3 diode with NiO field‐modulation structure. The diodes fabricated with two different NA both achieve 8000 V breakdown voltage and 4.7 MV cm−1 average electric field. This field is over three times higher than the best report in prior multi‐kilovolt lateral devices. These results show the promise of p‐type NiO for pushing the performance limits of power devices.

Fabricating process-electrochemical property correlation of laser-scribed graphene and smartphone-based electrochemical platform for portable and sensitive biosensing

Laser-scribed graphene (LSG), a promising electrode material has attracted special research interest in recent years. Here, the fabricating process-electrochemical property correlation of laser-scribed graphene (LSG) devices was discussed emphatically and a pertinent optimization was performed to achieve better electroanalytical performance. Experiment results indicated that the laser scribing technique possessed great process latitude and reducing laser power and scribing speed facilitated fabricating high-quality graphene electrodes. Benefiting from its binder-free 3D porous network structure and high active/geometric area ratio, the optimized LSG electrode was superior to the screen-printed carbon electrode (SPCE) on electrochemical performance in the [Fe(CN)6]3-/4- redox system. Integrating the LSG electrode with a homemade hand-held detector, a portable electrochemical sensing platform with smartphone readout was developed. It realized a specific detection of H2O2 (linear range: 0.02–3.4 mM, sensitivity: 24.56 μA mM−1 cm−2), glucose (linear range: 0.04–4.0 mM, sensitivity: 16.35 μA mM−1 cm−2) by directly decorating biological enzymes without artificial redox mediator and featured a satisfactory comprehensive performance. The constructed immunosensor for tumor necrosis factor-α exhibited a wide linear range (2–500 pg mL−1) and a 4.3-fold enhancement in sensitivity compared with that of SPCE. With satisfactory selectivity, reproducibility, and sensitivity, the developed smartphone-based electrochemical sensing platform held great promise in accurate detection on the spot. This work also provided a significant reference for tailoring binder-free carbonaceous electrode materials toward the desired application.

NiO junction termination extension for high-voltage (>3 kV) Ga2O3 devices

Edge termination is the enabling building block of power devices to exploit the high breakdown field of wide bandgap (WBG) and ultra-wide bandgap (UWBG) semiconductors. This work presents a heterogeneous junction termination extension (JTE) based on p-type nickel oxide (NiO) for gallium oxide (Ga2O3) devices. Distinct from prior JTEs usually made by implantation or etch, this NiO JTE is deposited on the surface of Ga2O3 by magnetron sputtering. The JTE consists of multiple NiO layers with various lengths to allow for a graded decrease in effective charge density away from the device active region. Moreover, this surface JTE has broad design window and process latitude, and its efficiency is drift-layer agnostic. The physics of this NiO JTE is validated by experimental applications into NiO/Ga2O3 p–n diodes fabricated on two Ga2O3 wafers with different doping concentrations. The JTE enables a breakdown voltage over 3.2 kV and a consistent parallel-plate junction field of 4.2 MV/cm in both devices, rendering a power figure of merit of 2.5–2.7 GW/cm2. These results show the great promise of the deposited JTE as a flexible, near ideal edge termination for WBG and UWBG devices, particularly those lacking high-quality homojunctions.

Wide process latitude, Pb-free low temperature co-fired ceramic (LTCC)

Low temperature co-fired ceramics, LTCC, are an established material platform for making high-quality, high-performance, and high-reliability electronic devices; however, systems exhibiting a sufficiently wide processing window have traditionally employed Pb-containing glasses. Micromax™ GreenTape™ LF95C has been introduced as a Pb-free LTCC system with a host of attractive physical, thermal, and electronic properties including repeatable shrinkage, dielectric loss of <0.005 at 10 GHz, refire stability, and a full Ag-based metallization system. The ceramic densifies by glass viscous flow which provides the ability to co-fire over a wide process window. The high-conductivity Ag metallization, low Df, and repeatable shrinkage and Dk make LF95C an excellent material platform for producing high-reliability electronic devices while advancing sustainability goals and working to satisfy the spirit of the REACH and RoHS initiatives.

Implementation Reserve Geocoding on Mobile Application

Reverse geocoding is the conversion of coordinates into an address that allows you to find an address. In this study, the coordinates in question are latitude and longitude points on a mobile device that uses an Android-based operating system. The default feature of Android devices for obtaining latitude and longitude data is Assisted – GPS (Global Positioning System) while the tool for processing latitude and longitude data in order to obtain location and place names from the Assisted – GPS (Global Positioning System) data that has been obtained is the nominal API. .org. the stages of work in the research are making a flow system, designing a system with use case diagrams, designing a database, coding, implementing it on android based and web based. The results of this study are that using Cordova can be an alternative for making Android-based mobile applications without the need for the relatively heavy Android Studio program if it is run on standard or low specification hardware, 2). With this mobile absence application, it is able to make it easier for employees to take attendance when outside the office with information about working or out of town service, 3). With this application it can be a means of facilitating superiors in assessing employee performance, 4). With this application can handle the problem solved.

All-Printed Ultrahigh-Responsivity MoS2 Nanosheet Photodetectors Enabled by Megasonic Exfoliation.

Printed 2Dmaterials, derived from solution-processed inks, offer scalable and cost-effective routes to mechanically flexible optoelectronics. With micrometer-scale control and broad processing latitude, aerosol-jet printing (AJP) is of particular interest for all-printed circuits and systems. Here, AJP is utilized to achieve ultrahigh-responsivity photodetectors consisting of well-aligned, percolating networks of semiconducting MoS2 nanosheets and graphene electrodes on flexible polyimide substrates. Ultrathin (≈1.2nm thick) and high-aspect-ratio (≈1μm lateral size) MoS2 nanosheets are obtained by electrochemical intercalation followed by megasonic atomization during AJP, which not only aerosolizes the inks but also further exfoliates the nanosheets. The incorporation of the high-boiling-point solvent terpineol into the MoS2 ink is critical for achieving a highly aligned and flat thin-film morphology following AJP as confirmed by grazing-incidence wide-angle X-ray scattering and atomic force microscopy. Following AJP, curing is achieved with photonic annealing, which yields quasi-ohmic contacts and photoactive channels with responsivities exceeding 103 AW-1 that outperform previously reported all-printed visible-light photodetectors by over three orders of magnitude. Megasonic exfoliation coupled with properly designed AJP ink formulations enables the superlative optoelectronic properties of ultrathin MoS2 nanosheets to be preserved and exploited for the scalable additive manufacturing of mechanically flexible optoelectronics.

Highly Efficient Air‐Mode Silicon Metasurfaces for Visible Light Operation Embedded in a Protective Silica Layer

AbstractDielectric metasurfaces have significant potential for delivering miniaturized optical systems with versatile functionalities, leading to applications in various fields such as orbital angular momentum generation, imaging, and holography. Among the different materials, crystalline silicon has the advantage of technological maturity and high refractive index, which increases design flexibility and processing latitude. The second, and often overlooked, advantage of silicon is that it affords embedding the metasurface in a protective material such as silica, which is essential for practical applications. The trade‐off against this high refractive index is silicon's absorption at visible wavelength, which requires new design strategies. Here, such a strategy based on metasurfaces supporting air modes is identified that can lead to a transmission efficiency as high as 87% at a wavelength of 532 nm. This exceptional efficiency is obtained by using the high index to confine the electric field in the periphery of the meta‐atoms, thereby reducing absorption losses. As an example, the design of a fully embedded metasurface is described that can generate vortex beams with various orders of orbital angular momentum. It is envisioned that the proposed strategy paves the way for practical applications of high‐efficiency metasurfaces based on crystalline silicon.

Design, Fabrication and Characterization of a 4.5kV / 50A 4H-SiC PiN Rectifiers

In this work, a 4.5kV/50A 4H-SiC PiN rectifiers with mesa combined with double-JTE structures is successfully developed for high power applications. Two-dimension numerical device simulator Silvaco-TCAD is applied to optimizing the electrical performance of fabricated rectifiers. Mesa-combined double-JTE structure is utilized to achieve a high blocking voltage with a wider optimum process latitude. A forward current is 50 A at room temperature when SiC PiN device bias 4.1 V, while the maximum blocking voltage achieved is 4.7 kV, reaching up to 86% of parallel-plane junction bulk breakdown.

Novel Low Temperature Curable Photo-Patternable Polyamide with High Planarity for Wafer Level Fan-Out Packaging (WLFO)

Abstract As Wafer Level Fan-Out Packaging (WLFO) designs continue to evolve, higher pattern densities for Cu lines and interconnects continue to increase while thickness continues to decrease. As Cu densities increase, the patterning resolution of the RDL dielectric needs to shrink to allow increased bump density. The higher Cu density in turn requires enhanced dielectric performance to minimize Cu migration, whilst utilizing lower temperature and shorter cure times which result in lower levels of wafer warpage. Minimizing mechanical stress, continues to be a critical function of the RDL dielectric. Warpage leads to poor yields, distorting the planarity of the package and ultimately leading to stress induced failure from cracking and delamination. Reduction of the thermal budget is the primary means of reducing mechanical stress in WLFO designs. The amount of Cu in the package continues to increase. Differences in thermal expansions of such and the dielectric increase with temperature. Further, conventional solder reflow processes and set points will continue to be used, therefore the RDL dielectric must continue to be thermally and mechanically stable but capable of being cured at lower temperatures, 180–200 °C to minimize overall mechanical stresses from thermal expansion. We present a novel polyamide based RDL dielectric, KMRD, designed to achieve current and future WLFO design requirements. KMRD is a low temperature curable, aqueous (2.38%TMAH) developable dielectric capable of meeting industry standards for mechanical and electrical requirements, with a high level of reliability while utilizing a single stage cure at 185 °C. KMRD provides clear advantages over incumbent materials, with low temperature cure, improved pattern resolution, wide process latitudes, superior adhesion, chemical compatibility, and cost benefits using standard processing equipment and chemistry.

High-voltage 4H-SiC PiN diodes with the etched implant junction termination extension**Project supported by the Science and Technology Development Foundation of China Academy of Engineering Physics (No. 2014A05011) and the Special Foundation of President of China Academy of Engineering Physics (No. 2014-1-100).

This paper presents the design and fabrication of an etched implant junction termination extension (JTE) for high-voltage 4H-SiC PiN diodes. Unlike the conventional JTE structure, the proposed structure utilizes multiple etching steps to achieve the optimum JTE concentration range. The simulation results show that the etched implant JTE method can improve the blocking voltage of SiC PiN diodes and also provides broad process latitude for parameter variations, such as implantation dose and activation annealing condition. The fabricated SiC PiN diodes with the etched implant JTE exhibit a highest blocking voltage of 4.5 kV and the forward on-state voltage of 4.6 V at room temperature. These results are of interest for understanding the etched implant method in the fabrication of high-voltage power devices.

Integration of Chemically Amplified Photoresist and High-Speed Copper Plating Products for Advanced Packaging Applications

Advanced packaging technologies require materials which will allow for better resolution of patterns associated with the ever more challenging device architecture, along with materials that will allow for higher throughput. Device throughput can be increased with imaging materials that have higher sensitivity and metallization chemistries with faster electrodeposition rates. Chemically amplified photoresists offer the advantages of excellent sensitivity and resolution with good process margins, coupled with excellent stripping performance and plating bath compatibility for the film thicknesses that are required in packaging applications. Electrolytic copper plating products with fast deposition rates are a key factor in decreasing wafer plating time and increasing throughput. However, it is the integration of the photoimaging material and the subsequent plating chemistry that is essential in producing metallized structures for copper pillar and solder applications. Because the profile of the resist image is directly transferred during the electroplating process, it is critical to have a well formed image that is resistant to the plating chemistry. Plating bath contamination and resist strippability are other key factors in producing void-free, defect-free structures. Dow's newly introduced chemically amplified material is capable of film thicknesses from 30um to 80um by a single coating process with good uniformity. Imaging and process latitude are demonstrated at 40um and 65um thicknesses with emphasis on sidewall profiles and sensitivity. Further, the photoresist compatibility with INTERVIA™ Cu 8540 Electroplating Copper Chemistry is shown, along with NIKAL™ BP Ni plating chemistry and SOLDERON™ BP TS 6000 SnAg plating chemistry compatibility. The improvements in product line from Dow's INTERVIA™ Cu 8540 to INTERVIA™ 9000 Electroplating Copper Chemistry is also demonstrated in the paper, with thickness uniformity, high plating speed, and tunable morphology highlighted for various applications. The power of integration has enabled the development of this suite of products designed for compatibility and superior performance for advanced packaging technologies. ™ Trademark of The Dow Chemical Company

Solid immersion optical lithography: index matching and resonant reflectors for large exposure field, high-aspect ratio imaging in the ultrahigh-numerical aperture regime

Recent work has investigated the resonant dielectric reflectors for high-aspect ratio (AR) imaging and the necessary requirements for index-matching liquids (IMLs) at the prism/sample interface when imaging using a solid immersion Lloyd’s mirror interference lithography (SILMIL) system. These past results showed that SILMIL systems require a prism/IML refractive index (RI) (real component) mismatch less than approximately ±0.02 and an imaginary RI component ≤5×10−5 to achieve good reproducibility and uniformity of high-AR resist structures in the ultrahigh-NA (UHNA) regime without system gapping control. Here, we present simulated and experimental results for an index-matched prism/IML combination and for an IML with an imaginary RI component of ∼10−5. These results present the first SILMIL system that can produce both low- and high-AR resist structures over larger exposure fields than previously reported and without gapping control. We also present simulated and experimental results that show the AR process latitude, which further highlights the improved control compared with previous SILMIL research. Finally, we present simulated results from a materials survey that show new potential candidate dielectric underlayer materials that can accommodate high-AR imaging in the UHNA regime, some of which are better geared for the semiconductor industry.

Processing study of SU-8 pillar profiles with high aspect ratio by electron-beam lithography

We report the fabrication of micro-pitched SU-8 pillar arrays with height up to 5μm and aspect ratio of 7.14:1 by electron beam lithography (EBL) at 100keV, combined with a hot developing process. Careful study of processing latitude for geometry parameters of SU-8 pillars was conducted to achieve three different profiles, vertical pillar for biosensing application, trapezoidal shape for antireflection of light in solar cells as well as in displays, and final pillars with thick residuals in the gaps. It was found in our work that SU-8 is particularly a good candidate for tall micro/nano structures with various shapes when the unavoidable proximity effect in the EBL was exploited, which was enhanced by the ultra-high sensitivity of epoxy groups in SU-8. Optical properties of the fabricated structures have been characterized. To the best of our knowledge, pillar like structures of SU-8 in the height range of 5μm have not been addressed sufficiently despite their broad potential applications in bioscience, environment protection, display and renewable energy sources etc.

Advanced lithography and electroplating approach to form high-aspect ratio copper pillars

Advanced packaging technologies continue to enable the semiconductor industry to meet the needs for ever thinner, smaller and faster components required in mobile devices and other high performance applications. In the early days of advanced packaging, C4 solder bumps were the alternative to wire bonding. Although lead-free solder remains one of the preferred methods for assembly, tall copper structures (copper pillars) are becoming the standard interconnect solution for many applications. A process of lithography and subsequent electroplating are the mainstream process for today's copper pillar formation on wafer level for high-end flip chip devices. The latest trends in advanced packaging require another technology development when it comes to copper pillars. Modern integration schemes such as 2.5D interposer as well as 3D stacking have pushed the limits of standard lithography and copper electroplating capabilities. Specifically, the need for fine-pitch high aspect ratio copper pillars represents a challenge. In addition, the trend towards rectangular panel-based packaging as seen with glass interposers or panel fan-out (P-FO) devices demands a challenging scale-up of lithography and electroplating equipment and processing capabilities. This work specifically focuses on the formation of high-aspect ratio copper pillars in excess of 100μm by means of stepper-based lithography followed by electroplating. A unique test vehicle has been created to evaluate the process latitude for lithography for different resist materials as well as the specific electroplating challenges associated with these tall and narrow structures. The paper investigates the influence of key parameters such as CD uniformity, pattern density variations and resist profile on the critically important pillar height uniformity across the wafer or panel. In addition, the resist profile behavior at the substrate interface is being examined as it influences undercut behavior during wet etch of the plating seed layer. A number of wet and dry-film resist materials and appropriate lithography processes (spin coat or laminate, expose, develop) followed by copper plating based on varying chemistries and process parameters are being explored. The paper also summarizes the current requirements for the above mentioned lithography and plating processes as seen in the industry today.

Characterization of a New and Complete Lead-Free Thick Film Resistor System for the Hybrid Circuit Market

The move to lead-free thick film technology, including resistors does not necessarily mean a move away from performance. There have been many recent developments in the area of lead-free glasses, thick film dielectrics, and conductor materials. However, the development of lead-free resistor materials has been slower to enter the market. This slower evolution is due, in part, to the need to develop a series of discrete compositions that are compatible with each other and cover a wide range of resistance values. There can be 8–10 individual members in such a series. The primary goal of this development was to achieve resistor performance on par with, or superior to an existing and popular premium lead based resistor system. This paper describes a new series of lead-free thick film resistor compositions that cover a complete range of decade values from 1 Ohm/square to 10 MegOhms/square. Each member is compatible and blendable with adjacent members to cover all possible resistivity needs. This system provides excellent environmental stability of laser trimmed resistors, tight TCR gap control, a wide processing latitude, and minimal termination effects with a wide range of lead-free conductor metallurgies including Au, Ag, Ag/Pt, and Ag/Pd. In this paper, we report the results of a characterization study that includes 1000 hours of laser trim stability in 85°C/85%RH, thermal ageing at 150°C, room temperature ageing, and thermal cycle stability at −50°C +150°C. Electrical properties are presented and include Power Handling, Quan-tech Noise, and Electrostatic Discharge stability. In addition, this paper investigates and documents: resistor length effects, fire and refire sensitivity effects, thickness behavior, and the use of lead-free encapsulation.

Bevel Junction Termination Extension—A New Edge Termination Technique for 4H-SiC High-Voltage Devices

A new edge termination method, referred to as a bevel junction termination extension (Bevel-JTE), is presented for high-voltage silicon carbide devices. The 4H-SiC PiN rectifiers, with a breakdown voltage of 1600 V ( $\sim 95$ % of the theoretical value), were fabricated using Bevel-JTEs. The Bevel-JTE technique significantly reduces the chip size by decreasing space occupied by edge termination while providing broad process latitude for parameter variations, such as implantation dose and activation anneal condition.

Versatile bilayer resist for laser lithography at 405 nm on glass substrates

We describe a simple bilayer photoresist that is particularly well suited for laser lithography at an exposure wavelength of 405 nm on glass substrates, which are often used for the fabrication of binary diffractive optics and computer-generated holograms. The resist consists of a poly-dimethyl glutarimide (PMGI) bottom layer that is used as an antireflection coating between a glass substrate and a positive or negative photoresist. The optical properties of the PMGI layer at 405 nm result in excellent suppression of reflections into the photoresist and good process latitude.

Fluorinated Polymer Yields High Organic Solar Cell Performance for a Wide Range of Morphologies

AbstractDevice performance is recognized to be generally sensitive to morphology in bulk heterojunction solar cells. Through the use of quantitative morphological measurements, it is demonstrated that devices based on benzodithiophene and fluorinated benzotriazole moieties constitute an exception to this design rule and exhibit a range of morphologies that yield similar high performance. In particular, the fill factor (FF) remains above 65% even with factor of two changes in domain size and factor of two changes in relative domain purity. Devices with active layer thicknesses of 250 nm are employed, which are capable of increasing optical absorption to produce high photocurrent. The general insensitivity to both morphology and thickness is likely related to the measured low equilibrium miscibility of fullerene in the polymer of 3‐4%. The materials and processes investigated therefore provide insights into functional material design that yield increased processing latitude and may be more amenable to roll‐to‐roll processing.

Modeling the effects of pupil-manipulated spherical aberration in optical nanolithography

An aerial image model is used to study the effects of spherical aberration applied in the lens pupil domain of a lithography projection scanner. These effects include the illumination dependency of focus exposure matrix tilt and the linear relationship between primary and higher order spherical coefficients on best focus (BF). Experimental data trends of BF through pitch and orientation have been replicated by an analytical expression. This computationally efficient formulation has the capability to provide corrective spherical aberration coefficients, which decrease the pitch-dependent BF and increase process latitude.