Problem In VLSI Design Research Articles

MOBA: Multi Objective Bat Algorithm for Combinatorial Optimization in VLSI

It has to be conceded that the complexity of any integrated chip gets abated despite of the increased complexity. Notwithstanding, the perplexity of computing escalates exponentially. Thus computational optimization scores in the scene wherein several conflicting objectives has to be optimized without any compromise. Several years, scientists have solved any optimization problem by cogitating and considering it to be a Single Objective Optimization Problem (SOOP). However, mathematics has eulogized Multi Objective Optimization (MOO) methodologies to solve the conflicting tradeoffs. Besides, there is an instigation to converge our research to biologically inspired metaheuristics to solve optimization problems as it is evident from the anthologies and research archive that these heuristics perpetually doing well in solving optimization problems and that too in extension MOO problems. Researchers are captivated in the field to observe the perplexed processes of nature and mimic it solve optimization problems. In this research work, we have contemplated on the Multi Objective Bat Algorithm (MOBA) a biologically inspired metaheuristics and have successfully applied to solve the problem of floorplanning in VLSI design. The peculiar character of echolocation of microbats are being mimicked and applied to solve the problems in VLSI design. The intriguing attributes of Bats; how it strives to take up its prey, are fathomed out and been adopted in problem solving. The problem is considered as a MOO problem wherein equal importance were given to wirelength minimization and dead space minimization. The results are discussed and rivalled with several other bio-inspired algorithms and are portrayed. To comprehend, the MOBA worked well in VLSI floorplanning optimization wherein the problems were considered with a single objective and multi objective fashion.

Steiner Trees with Bounded RC-Delay

We consider the Minimum Elmore Delay Steiner Tree Problem, which is a key problem in VLSI design: We are given a set of pins which have to be connected by a Steiner tree. One of the pins is the source. Challenging timing constraints impose tight bounds on the delay of propagating a signal from the source to the other pins. The commonly used measure is Elmore delay (Elmore in J Appl Phys 19:55---63, 1948). We consider two variants: minimizing the maximum Elmore delay or a weighted sum of Elmore delays. Both variants are strongly NP-hard even for very restricted special cases. Although it is a central problem in VLSI design (Kahng and Robins in On optimal interconnections for VLSI. Kluwer, Boston, 1995; Korte and Vygen in Building bridges--between mathematics and computer science. Springer, Berlin, pp 333---368, 2008), no approximation algorithms were known so far. In this work, we give the first constant-factor approximation algorithm. It works for both variants. The algorithm achieves an approximation ratio of 3.39 in the rectilinear plane and 4.11 in general metric spaces. We can show that our algorithm is best possible in a certain sense. We also demonstrate that our algorithm leads to improvements on real world VLSI instances compared to the currently used standard method of computing short Steiner trees.

Efficient algorithm for the vertex connectivity of trapezoid graphs

The intersection graph of a collection of trapezoids with corner points lying on two parallel lines is called a trapezoid graph. These graphs and their generalizations were applied in various fields, including modeling channel routing problems in VLSI design and identifying the optimal chain of non-overlapping fragments in bioinformatics. Using modified binary indexed tree data structure, we design an algorithm for calculating the vertex connectivity of trapezoid graph G with time complexity O(nlogn), where n is the number of trapezoids.

Novel quantum-inspired evolutionary algorithms for the quadratic knapsack problem

The Knapsack Problem assigns weights and values to each of a given set of objects, with the objective of choosing a subset no larger than some specified weight constraint in such a manner as to maximise the total value accrued thereby. The Quadratic Kapsack Problem (QKP) extends KP by associating values with not just individual objects but also with pairs of objects. The problem is known to be NP-hard and arises in several domains including finance, VLSI design and location problems. Greedy heuristics and Genetic Algorithms (GAs) for QKP exist in the literature. Quantum-inspired Evolutionary Algorithms (QEAs) are population-based probabilistic EAs that integrate concepts from quantum computing for higher representational power and robust search. This paper presents novel Quantum-inspired Evolutionary Algorithms (QEAs) that integrate concepts from quantum computing for higher representational power and robust search. The performance of the QEAs is shown to be competitive vis-a-vis two recent well known GAs over a wide range of benchmark instances.

Solving VLSI design and DNA sequencing problems using bipartization of graphs

In this paper we consider the 2-layer constrained via minimization problem and the SNP haplotype assembly problem. The former problem arises in the design of integrated and printed circuit boards, and the latter comes up in the DNA sequencing process for diploid organisms. We show that, for any maximum junction degree, the problem can be reduced to the maximum bipartite induced subgraph problem. Moreover we show that the SNP haplotype assembly problem can also be reduced to the maximum bipartite induced subgraph problem for the so-called minimum error correction criterion. We give a partial characterization of the bipartite induced subgraph polytope. Using this, we devise a branch-and-cut algorithm and report some experimental results. This algorithm has been used to solve real and large instances.

Approximation Algorithms for Treewidth

This paper presents algorithms whose input is an undirected graph, and whose output is a tree decomposition of width that approximates the optimal, the treewidth of that graph. The algorithms differ in their computation time and their approximation guarantees. The first algorithm works in polynomial-time and finds a factor-O(log OPT) approximation, where OPT is the treewidth of the graph. This is the first polynomial-time algorithm that approximates the optimal by a factor that does not depend on n, the number of nodes in the input graph. As a result, we get an algorithm for finding pathwidth within a factor of O(log OPT⋅log n) from the optimal. We also present algorithms that approximate the treewidth of a graph by constant factors of 3.66, 4, and 4.5, respectively and take time that is exponential in the treewidth. These are more efficient than previously known algorithms by an exponential factor, and are of practical interest. Finding triangulations of minimum treewidth for graphs is central to many problems in computer science. Real-world problems in artificial intelligence, VLSI design and databases are efficiently solvable if we have an efficient approximation algorithm for them. Many of those applications rely on weighted graphs. We extend our results to weighted graphs and weighted treewidth, showing similar approximation results for this more general notion. We report on experimental results confirming the effectiveness of our algorithms for large graphs associated with real-world problems.

On routing in VLSI design and communication networks

In this paper, we study the global routing problem in VLSI design and the multicast routing problem in communication networks. First we propose new and realistic models for both problems. In the global routing problem in VLSI design, we are given a lattice graph and subsets of the vertex set. The goal is to generate trees spanning these vertices in the subsets to minimize a linear combination of overall wirelength (edge length) and the number of bends of trees with respect to edge capacity constraints. In the multicast routing problem in communication networks, a graph is given to represent the network, together with subsets of the vertex set. We are required to find trees to span the given subsets and the overall edge length is minimized with respect to capacity constraints. Both problems are APX -hard. We present the integer linear programming (LP) formulation of both problems and solve the LP relaxations by the fast approximation algorithms for min–max resource-sharing problems in [K. Jansen, H. Zhang, Approximation algorithms for general packing problems and their application to the multicast congestion problem, Math. Programming, to appear, doi: 10.1007/s10107-007-0106-8] (which is a generalization of the approximation algorithm proposed by Grigoriadis and Khachiyan [Coordination complexity of parallel price-directive decomposition, Math. Oper. Res. 2 (1996) 321–340]). For the global routing problem, we investigate the particular property of lattice graphs and propose a combinatorial technique to overcome the hardness due to the bend-dependent vertex cost. Finally, we develop asymptotic approximation algorithms for both problems with ratios depending on the best known approximation ratio for the minimum Steiner tree problem. They are the first known theoretical approximation bound results for the problems of minimizing the total costs (including both the edge and the bend costs) while spanning all given subsets of vertices.

Placement and Routing in VLSI design Problem Using Single Row Routing Technique

Two major problems are involved in VLSI design, namely, the placement of components and routing between these components. Single row routing problem is a combinatorial optimization problem of significant importance for the design of complex VLSI multi layer printed circuit boards (PCB's). The design involves conductor routing that makes all the necessary wiring and interconnections between the PCB modules, such as pins, vias, and backplanes. In very large systems, the number of interconnections may exceed tens of thousands. Therefore, we have to optimize the wire routing and interconnections and thus determine the efficient designs. Kernighan-Lin algorithm, traveling salesman problem, simulated annealing algorithm and single row routing problem are used to find the best design. Included here are some simple examples to find the results. A simulation program using Microsoft Visual C++ is developed to simulate the single row routing problem using the simulated annealing algorithm. Keywords: Placement and Routing in VLSI; Single Row Routing; Kernighan-Lin Algorithm; Simulated Annealing

Minimizing Wirelength in Zero and Bounded Skew Clock Trees

An important problem in VLSI design is distributing a clock signal to synchronous elements in a VLSI circuit so that the signal arrives at all elements simultaneously. The signal is distributed by means of a clock routing tree rooted at a global clock source. The difference in length between the longest and shortest root-leaf path is called the skew of the tree. The problem is to construct a clock tree with zero skew (to achieve synchronicity) and minimal sum of edge lengths (so that circuit area and clock tree capacitance are minimized). We give the first constant-factor approximation algorithms for this problem and its variants that arise in the VLSI context. For the zero skew problem in general metric spaces, we give an approximation algorithm with a performance guarantee of 2e. For the L1 version on the plane, we give an (8/ln 2)-approximation algorithm.

Maximum weight k-independent set problem on permutation graphs

Based on a Directed Acyclic Graph approach, an O(kn 2) time sequential algorithm is presented to solve the maximum weight k-independent set problem on weighted-permutation graphs. The weights considered here are all non-negative and associated with each of the n vertices of the graph. This problem has many applications in practical problems like k-machines job scheduling problem, k-colourable subgraph problem, VLSI design and routing problem.

Exact routing with search space reduction

The layout problem in VLSI-design can be broken up into the subtasks partitioning, floorplanning, placement, and routing. In the routing phase, a large number of connections between the blocks and cells have to be established, while intersections lead to short circuits and, therefore, have to be avoided. We present an approach for exact routing of multiterminal nets that complements traditional routing techniques. It is particularly well suited for an application to dense problem instances and the completion of routing in subregions, which turn out to be difficult for routing tools based on heuristic methods. The exact router proposed uses symbolic methods, i.e., MDDs (multivalued decision diagrams) for representation of the routing space. For the necessary computations of routing solutions, we profit considerably from the efficient basic operations on MDDs. All possible solutions to the routing problem are represented by one single MDD and, once this MDD is given, routability can be decided within constant time. To reduce the search space of possible routing solutions, so-called forced cells are computed. Experimental results are given to show the feasibility and the practicability of the approach.

Genetic Algorithms for High-Level Synthesis in VLSI Design

VLSI design involves a number of steps such as system-level design, high-level synthesis (HLS), logic design, test generation, and physical design. All these steps involve combinatorial optimizations that are NP complete. Genetic algorithms (GA) have been used to solve many problems in VLSI design. HLS is the crucial step where the architecture of the system is decided upon. We have worked on several problems relating to high-level synthesis and developed GAs for them. In this article we describe our GAs for the following three problems and describe some general methods that we have used in these GAs to enhance their operation. Minimum node deletion (MND). Allocation and binding for data path synthesis. Scheduling, allocation, and binding for the synthesis of structured architectures. All of the above problems are NP complete. We have used the following techniques to enhance the operation of the GA: Population control to enforce diversity within a relatively small population size. Solution completion using approximate algorithms to generate superior valid solutions. Selection control to reduce crossover between incompatible members. These GAs have been tested on the usual benchmarks and the results have been found to be acceptably good. The enhancing techniques we describe here are of a general nature and may be used with other GAs to produce better results.

Iterative Converging Algorithms for Computing Bounds on Durations of Activities in Pert and Pert-Like Models

Since its invention in 1958, Program Evaluation and Review Technique (PERT) has been widely used during the planning, design, and implementation of projects. Pert models the activities of a project as a single source-single sink directed acyclic graph where nodes represent events (end or beginning of activities) and arcs activities. The maximum amount by which an activity can be delayed without delaying the overall project is called the slack. Critical tasks have zero slack whereas all noncritical tasks have positive slacks. Pert is a valuable tool in the management of large projects since it allows to compute the slack of each activity of the project. Such information may be crucial in avoiding cost overruns that would be caused by delays to critical activities and/or excessive delays to noncritical activities. What Pert fails to provide is how one should go about distributing remaining slack on noncritical activities while taking into consideration properties of the activities as well as precedence relationships among them, so as to have reasonable upper bounds on duration of all activities, critical or noncritical. In this paper we propose several algorithms for the distribution of slack on non-critical activities. We show that if one desires to distribute the remaining slack proportionally to the initially assigned activity durations then the problem is in P, and propose an algorithm of linear time complexity. However if one desires to use distribution functions other than the initial durations of activities, then the problem of slack distribution becomes NP-complete. Finding the maximal bounds corresponding to zero-slack solution at the sink requires iterative application of exponential algorithm. For that case we introduce an approximation algorithm of linear time complexity on each iteration. The algorithm iteratively increases bounds on durations of activities and converges to the zero-slack solution on all paths from the source node to the sink node in the Pert-like graph. The algorithms described in this paper were successfully applied to solving timing bounds problems in VLSI design.

Some polynomially solvable subcases of the detailed routing problem in VLSI design

There are plenty of NP-complete problems in very large scale integrated design, like channel routing or switchbox routing in the two-layer Manhattan model (2Mm, for short). However, there are quite a few polynomially solvable problems as well. Some of them (like the single row routing in 2Mm) are “classical” results; in a past survey [36] we presented some more recent ones, including: 1. a linear time channel routing algorithm in the unconstrained two-layer model; 2. a linear time switchbox routing algorithm in the unconstrained multilayer model; and 3. a linear time solution of the so called gamma routing problem in 2Mm. (This latter means that all the terminals to be interconnected are situated at two adjacent sides of a rectangular routing area, thus forming a Γ shape. Just like channel routing, it is a special case of switchbox routing, and contains single row routing as a special case.) In the present survey talk we also mention some results from the last three years, including 4. some negative results (NP-completeness) in the multilayer Manhattan model and a channel routing algorithm if the number of layers is even; 5. an interesting relation between channel routing and multiprocessor scheduling; and 6. some improvements of 1–3 above. We present the (positive and negative) results in a systematic way, taking into account two hierarchies, namely that of geometry (what to route) and technology (how to route) at the same time.

VLSI Routing in Polynomial Time

There are plenty of NP-complete problems in VLSI design, like channel routing or switchbox routing in the 2-layer Manhattan model. However, there are quite a few polynomially solvable problems as well, some of them (like the single row routing in the 2-layer Manhattan model) date back to the fifties. Here we survey some old and some more recent results (both polynomially solvable subcases and NP-completeness proofs) in a systematic way, taking into account two hierarchies, namely that of geometry (what to route) and technology (how to route) at the same time. Due to lack of space, this extended abstract does not contain references; a more detailed version is available from the author.

Distance in stratified graphs

A graph G is stratified if its vertex set is partitioned into classes, called strata. If there are k strata, then G is k-stratified. These graphs were introduced to study problems in VLSI design. The strata in a stratified graph are also referred to as color classes. For a color X in a stratified graph G, the X-eccentricity e X(v) of a vertex v of G is the distance between v and an X-colored vertex furthest from v. The minimum X-eccentricity among the vertices of G is the X-radius radX G of G and the maximum X-eccentricity is the X-diameter diamX G. It is shown that for every three positive integers a, b and k with a≤b, there exist a k-stratified graph G with radX G = a and diamX G = b. The number s X denotes the minimum X-eccetricity among the X-colored vertices of G. It is shown that for every integer t with radX G ≤ t ≤ diamX G, there exist at least one vertex v with e X(v) = t; while if radX G ≤ t ≤ s X, then there are at least two such vertices. The X-center C X(G) is the subgraph induced by those vertices v with e X(v) = radX G and the X-periphery P X (G) is the subgraph induced by those vertices v with e X(G) = diamX G. It is shown that for k-stratified graphs H 1, H 2,..., H k with colors X 1, X 2,..., X k and a positive integer n, there exists a k-stratified graph G such that C X i(G)≅ H i (1 ≤; i ≤; k1) and \(d(C_{x_i } (G),C_{x_j } (G)) \geqslant n{\text{ for }}i \ne j.\) for i ≠ j. Those k-stratified graphs that are peripheries of k-stratified graphs are characterized. Other distance-related topics in stratified graphs are also discussed.

Two‐dimensional Placement Using Tabu Search

Search based placement of modules is an important problem in VLSI design. It is always desired that the search should converge quickly to a high quality solution. This paper presents a tabu search based optimization technique to place modules on a regular two‐dimensional array. The goal of the technique is to speed up the placement process. The technique is based on a two‐step placement strategy. The first step is targeted toward improving circuit routability and the second step addresses circuit performance. The technique is demonstrated through placement of several benchmark circuits on academic as well as commercial FPGAs. Results are compared to placements generated by commercial CAE tools and published simulated annealing based techniques. The tabu search technique compares favorably to published simulated annealing based techniques, and it demonstrates an average execution time speedup of 20 with no impact on quality of results when compared to commercial tools.

A neural network parallel algorithm for one-dimensional gate assignment problems

A near-optimum parallel algorithm for solving the one-dimensional gate assignment problem is presented in this paper, where the problem is NP-hard and one of the most fundamental layout problems in VLSI design. The proposed system is composed of n × n processing elements based on the artificial two-dimensional maximum neural network for (n + 2)-gate assignment problems. Our algorithm has discovered improved solutions in the benchmark problems compared with the best existing algorithms. The proposed approach is applicable to other VLSI layout problems such as the PLA (Programmable Logic Array) folding problem. © 1999 Scripta Technica, Electr Eng Jpn, 129(2): 71–77, 1999

A Near-Optimal Parallel Algorithm for One-Dimensional Gate Assignment in VLSI Layout

A novel approach to the one-dimensional gate assignment problem is presented in this paper where the problem is NP-hard and one of the most fundamental layout problems in VLSI design. The proposed system is composed of n × n processing elements calle

The steiner tree packing problem in VLSI design

In this paper we describe several versions of the routing problem arising in VLSI design and indicate how the Steiner tree packing problem can be used to model these problems mathematically. We focus on switchbox routing problems and provide integer programming formulations for routing in the knock-knee and in the Manhattan model. We give a brief sketch of cutting plane algorithms that we developed and implemented for these two models. We report on computational experiments using standard test instances. Our codes are able to determine optimum solutions in most cases, and in particular, we can show that some of the instances have no feasible solution if Manhattan routing is used instead of knock-knee routing.