Probabilistic Transfer Matrices Research Articles

Accurate reliability analysis of concurrent checking circuits employing an efficient analytical method

Transient faults are important concerns in emerging ICs built from deep semiconductors. Concurrent error detection (CED) scheme has been proved to be an efficient technique in such a context. On the other hand, the increase of multiple faults can be foreseeable in future ICs. However, reported efforts applied to quantify the efficiency of CED schemes mostly consider single faults or suppose that implemented checker mechanisms are fault-free. This paper describes an alternative analytical solution for CED circuits analysis under a more realistic hypothesis. In addition to the assumption of the whole fault-prone circuit (including checker mechanisms), different failure rates of logic gate are considered as well. The proposed approach is based on probabilistic transfer matrices and then can deal with multiple faults. The time efficiency of the proposed solution is demonstrated through arithmetic circuits. By applying this solution, classical CED schemes are discussed according to different failure rates of transistor.

Behavior of stochastic circuits under severe error conditions

Abstract Stochastic computing is an old and unconventional computing technique that is finding promising new applications in image processing and the handling of complex error-correcting codes. Stochastic circuits offer an alternative to conventional digital circuits because of their extremely small size and inherent noise tolerance. They are also well-suited to meeting the requirements of emerging nanoscale technologies where non-deterministic behavior due to manufacturing defects and soft errors cannot be ignored. Error analysis of stochastic circuits, however, has received little attention and remains a largely open problem, especially when multiple errors affecting both the data sources and the stochastic circuits can occur in the course of a computation. This paper attempts to analyze stochastic circuits under various error conditions, and to compare their behavior to that of conventional circuits under similar error conditions. We use probabilistic transfer matrices for this analysis, complemented by circuit simulation. Our results indicate that stochastic circuits provide significantly better error tolerance under severe error conditions.

Fault-tolerant analysis of TMR design with noise-aware logic

Due to the effect of thermal noise, ground bounce and process variations in nanometer process, the behavior of any logical circuit becomes increasingly probabilistic. In this paper, based on the noise model [5] on the input and output nodes of a probabilistic CMOS (PCMOS) gate, the correctness probabilities of four PCMOS primitive gates, NOT, NAND, NOR and XOR, can be firstly computed. Based on the concept of the probabilistic transfer matrices (PTMs) and the corresponding operations on PTMs for the serial and parallel compositions of the components in a well-formed circuit, the correctness probability of the output in a 3-input PCMOS majority circuit in a triple modular redundancy (TMR) design can be further computed. For a given circuit with smaller error, it is well known that a TMR design has good fault-tolerant characterization and the correctness probability of the original output is converged to 1. Under the use of noise-aware logic in a TMR design, it is obvious that the fault-tolerant characterization of a TMR design is degraded and the correctness probability of the original output is not converged to 1. The experimental results show that the improvement region of the correctness probability of the original output will be narrowed due to the noise effect on the gates in a 3-input PCMOS majority circuit.

Analyzing the Inherent Reliability of Moderately Sized Magnetic and Electrostatic QCA Circuits Via Probabilistic Transfer Matrices

As computing technology delves deeper into the nanoscale regime, reliability is becoming a significant concern, and in response, Teramac-like systems will be the model for many early non-CMOS nanosystems. Engineering systems of this type requires understanding the inherent reliability of both the functional cells and the interconnect used to build the system, and which components are most critical. One particular nanodevice, quantum-dot cellular automata (QCA), offers unique challenges in understanding the reliability of its basic circuits since the device used for logic is also used for interconnect. In this paper, we analyze the reliability properties of two classes of QCA devices: molecular electrostatic-based and magnetic-domain-based. We use an analytic model, probabilistic transfer matrices (PTMs), to compute the inherent reliability of various nontrivial circuits. Additionally, linear regression is used to determine which components are most critical and estimated the reliability gains that may be achieved by improving the reliability of just a critical component. The results show the critical importance of different structures, especially interconnect, as used by the two classes of QCA.

Probabilistic transfer matrices in symbolic reliability analysis of logic circuits

We propose the probabilistic transfer matrix (PTM) framework to capture nondeterministic behavior in logic circuits. PTMs provide a concise description of both normal and faulty behavior, and are well-suited to reliability and error susceptibility calculations. A few simple composition rules based on connectivity can be used to recursively build larger PTMs (representing entire logic circuits) from smaller gate PTMs. PTMs for gates in series are combined using matrix multiplication, and PTMs for gates in parallel are combined using the tensor product operation. PTMs can accurately calculate joint output probabilities in the presence of reconvergent fanout and inseparable joint input distributions. To improve computational efficiency, we encode PTMs as algebraic decision diagrams (ADDs). We also develop equivalent ADD algorithms for newly defined matrix operations such as eliminate_variables and eliminate_redundant_variables , which aid in the numerical computation of circuit PTMs. We use PTMs to evaluate circuit reliability and derive polynomial approximations for circuit error probabilities in terms of gate error probabilities. PTMs can also analyze the effects of logic and electrical masking on error mitigation. We show that ignoring logic masking can overestimate errors by an order of magnitude. We incorporate electrical masking by computing error attenuation probabilities, based on analytical models, into an extended PTM framework for reliability computation. We further define a susceptibility measure to identify gates whose errors are not well masked. We show that hardening a few gates can significantly improve circuit reliability.

Reliability Analysis of Large Circuits Using Scalable Techniques and Tools

The rapid development of CMOS and non-CMOS nanotechnologies has opened up new possibilities and introduced new challenges for circuit design. One of the main challenges is in designing reliable circuits from defective nanoscale devices. Hence, there is a need to develop methodologies to accurately evaluate circuit reliability. In recent years, a number of reliability evaluation methodologies based on probabilistic model checking, probabilistic transfer matrices, probabilistic gate models, etc., have been proposed. Scalability has been a concern in the applicability of these methodologies to the reliability analysis of large circuits. In this paper, we develop a general, scalable technique for these reliability evaluation methodologies. Specifically, an algorithm is developed for the model checking-based methodology and implemented in a tool called Scalable, Extensible Tool for Reliability Analysis (SETRA). SETRA integrates the scalable model checking-based algorithm into the conventional computer-aided design circuit design flow. The paper also discusses ways to modify the scalable algorithm for the other reliability estimation methodologies and plug them into SETRA's extensible framework. Our preliminary experiments show how SETRA can be used effectively to evaluate and compare the robustness of different circuit designs.

Comparing Reliability-Redundancy Tradeoffs for Two von Neumann Multiplexing Architectures

Nanoelectronic systems are anticipated to be highly susceptible to computation and communication noise. Interestingly, von Neumann addressed the issue of computation in the presence of noisy gates in 1952 and developed a technique called multiplexing. He proposed multiplexing architectures based on two universal logic functions, nand and maj. Generalized combinatorial models to analyze such multiplexing architectures were proposed by von Neumann and extended later by others. In this work, we describe an automated method for computing the effects of noise in both the computational and interconnect hardware of multiplexing-based nanosystems-a method employing a probabilistic model checking tool and extending previous modeling efforts, which only considered gate noise. This method is compared with a recently proposed automation methodology based on probabilistic transfer matrices and used to compute and compare the reliability of individual nand and maj multiplexing systems, both in the presence of gate and interconnect noise. Such a comparative study of nand and maj multiplexing is needed to provide quantitative guidelines for choosing one of the multiplexing schemes. The maximum device failure probabilities that can be accommodated by multiplexing-based fault-tolerant nanosystems are also computed by this method and compared with theoretical results from the literature. This paper provides a framework that can capture probabilistically quantified fault models and provide quick reliability evaluation of multiplexing architectures