Private Blocks Research Articles

A Novel Hybrid Cache Coherence with Global Snooping for Many-core Architectures

Cache coherence ensures correctness of cached data in multi-core processors. Traditional implementations of existing protocols make them unscalable for many core architectures. While snoopy coherence requires unscalable ordered networks, directory coherence is weighed down by high area and energy overheads. In this work, we propose Wireless-enabled Share-aware Hybrid (WiSH) to provide scalable coherence in many core processors. WiSH implements a novel Snoopy over Directory protocol using on-chip wireless links and hierarchical, clustered Network-on-Chip to achieve low-overhead and highly efficient coherence. A local directory protocol maintains coherence within a cluster of cores, while coherence among such clusters is achieved through global snoopy protocol. The ordered network for global snooping is provided through low-latency and low-energy broadcast wireless links. The overheads are further reduced through share-aware cache segmentation to eliminate coherence for private blocks. Evaluations show that WiSH reduces traffic by and runtime by , while requiring smaller storage and lower energy as compared to existing hierarchical and hybrid coherence protocols. Owing to its modularity, WiSH provides highly efficient and scalable coherence for many core processors.

Dynamic directory table with victim cache: on-demand allocation of directory entries for active shared cache blocks

In this paper, we present a novel directory architecture that can dynamically allocate a directory entry for a cache block on demand at runtime only when the block is shared by more than a single core. Thus, we do not maintain coherence for private blocks, substantially reducing the number of directory entries. Even for shared blocks, we allocate directory entry dynamically only when the block is actively shared, further reducing the number of directory entries at runtime. For this, we propose a new directory architecture called dynamic directory table (DDT), which is a decoupled directory storage from the shared cache and dynamically maintains directory entries only for actively shared blocks. Also, we add a small additional victim cache to its original DDT in order to reduce invalidation broadcasts caused by DDT eviction. Through our detailed simulation on PARSEC benchmarks, we show that DDT can outperform the expensive full-map directory by a slight margin with only 16.09% of directory area across a variety of different workloads. This is achieved by its faster access and high hit rates in the small directory. In addition, we demonstrate that even smaller DDTs can give comparable or higher performance compared to recent directory optimization schemes such as SPACE and DGD with considerably less area.

Reuse-Distance-Aware Write-Intensity Prediction of Dataless Entries for Energy-Efficient Hybrid Caches

Emerging nonvolatile memory technologies act as a prominent choice for the larger on-chip caches on account of high density, good scalability, and low static power consumption. However, costly write operations reduce their possibility as a successor of SRAM. To mitigate this problem, a spin-transfer torque random-access memory (STT-RAM)-SRAM hybrid cache architecture is proposed. In such cache architectures, allocation of a write-intensive block is the key challenge for energy efficiency. This paper presents a data allocation policy that reduces the number of writes and energy consumption of the STT-RAM region in the last-level cache by considering the existence of private blocks. Dataless entries are allocated in STT region for such private blocks, and actual data is written only when the block is written back from L1. Heavily written blocks are subsequently migrated to SRAM region. We also present a predictor that helps to redirect the write backs from L1 of dataless entries directly to SRAM region, depending on the predicted reuse-distance-aware write intensity. Experimental evaluation shows that this technique reduces the energy consumption by 34.3% (19.6%) and 23.3% (14.1%), respectively, over two existing techniques in the case of dual (quad) core system.

Home-grown: Gardens, practices and motivations in urban domestic vegetable production

Food production is of symbolic and practical importance in sustainable cities. Vegetable gardening in public spaces and community gardens is better understood than the same activity on private residential property. In suburbanised western cities most vegetable production is likely to be on private blocks. To increase vegetable production in cities, we need to understand private vegetable growing. We used a questionnaire administered in person with a diverse sample of 101 gardeners in Hobart, Tasmania, Australia to determine variation in gardens, gardening practices and gardener motivations, relationships between them, and potential for planning and other interventions to increase domestic vegetable production. Vegetable gardens varied from highly species-rich to species-poor and from staple production to expressions of culinary fashion. Gardening practices varied from integrated, organic and displayed, to strongly constructed and reliant on synthetic inputs. While all respondents were motivated to grow vegetables for pleasure, many were activists who wished to promote social change, while others wished to ensure affordable access to vegetables or to improve health. Activist gardeners used integrated organic or permacultural practices and produced highly complex garden outcomes. With the exceptions of the activists and food fashionistas, garden type, gardening practice and gardener motivation were not strongly interlinked. A large majority of respondents identified family members as important sources of information and inspiration. Gardeners without family role models were either influenced by new food cultures or were on low-incomes and wanted affordable access to vegetables. This latter group could be expanded through appropriate education and incentives.

Temporary domesticities: The Southeast Asian hotel as (re)presentation of modernity, 1968–1973

This essay examines the building of the Southeast Asian luxury hotel during the 1960s and 1970s as instrumental to the reshaping and consolidation of the global image of modernity for the region. While the war against slums and homelessness was being fought in the new towns, with public and private housing estates and blocks of flats for the working and middle classes, the branding of the modern Asian city was taking place at the waterfront and in the main thoroughfares of these cities. Not only did the luxury hotel present a stark contrast to the crowded, slum-filled imagery of these developing industrialising cities, its proponents— governments, developers and architects—sought to use it to replace ‘Third World’ impressions with ‘First World’ experiences. Driven by economic pragmatism, the proliferation of the slab-tower and podium building, and its interchangeable use as hotel and residential flats in the Southeast Asian city, witnessed a period of regional networking, investments, brand building, knowledge expertise transfers and the rise of a mobile class of international travellers. This essay argues that in response to Cold War political and economic contingencies, these temporary spaces of domesticity and consumption were part of an incipient complex of regional cultural identification in which architecture was paramount. It challenges the reading of the hotel interior as simply an orientalised space of consumption for foreign tourists and, instead, posits that it was complicit in the production of the citizenry as participants in these new public spaces of the emerging economies of Hong Kong and Singapore. Focussing on how such hotels were presented and described in newspapers and specialist trade journals, the essay seeks an alternative way to understand modern domesticity in these cities beyond the centre-periphery schema of one-way transfers of knowledge and expertise.

PS directory: a scalable multilevel directory cache for CMPs

As the number of cores increases in current and future chip-multiprocessor (CMP) generations, coherence protocols must rely on novel hardware structures to scale in terms of performance, power, and area. Systems that use directory information for coherence purposes are currently the most scalable alternative. This paper studies the important differences between the directory behavior of private and shared blocks, which claim for a separate management of both types of blocks at the directory. We propose the PS directory, a two-level directory cache that keeps the reduced number of frequently accessed shared entries in a small and fast first-level cache, namely Shared cache, and uses a larger and slower second-level Private cache to track the large amount of private blocks. Entries in the Private cache do not implement the sharer vector, which allows important silicon area savings. Speed and area reasons suggest the use of eDRAM technology, much denser but slower than SRAM technology, for the Private cache, which in turn brings energy savings. Experimental results for a 16-core CMP show that, compared to a conventional directory, the PS directory improves performance by 14 \(\%\) while reducing silicon area and energy consumption by 34 and 27 \(\%\), respectively. Also, compared to the state-of-the-art Multi-Grain Directory, the PS directory apart from increasing performance, it reduces power by 18.7 \(\%\), and provides more scalability in terms of area.

Increasing the effectiveness of directory caches by deactivating coherence for private memory blocks

To meet the demand for more powerful high-performance shared-memory servers, multiprocessor systems must incorporate efficient and scalable cache coherence protocols, such as those based on directory caches. However, the limited directory cache size of the increasingly larger systems may cause frequent evictions of directory entries and, consequently, invalidations of cached blocks, which severely degrades system performance. A significant percentage of the referred memory blocks are only accessed by one processor (even in parallel applications) and, therefore, do not require coherence maintenance. Taking advantage of techniques that dynamically identify those private blocks, we propose to deactivate the coherence protocol for them and to treat them as uniprocessor systems do. The protocol deactivation allows directory caches to omit the tracking of an appreciable quantity of blocks, which reduces their load and increases their effective size. Since the operating system collaborates on the detection of private blocks, our proposal only requires minor modifications. Simulation results show that, thanks to our proposal, directory caches can avoid the tracking of about 57% of the accessed blocks and their capacity can be better exploited. This contributes either to shorten the runtime of parallel applications by 15% while keeping directory cache size or to maintain system performance while using directory caches 8 times smaller.