Printed Circuit Board Substrate Research Articles

Thermal Degradation and Decomposition of FR4 Laminate PCB Substrates Joined by Friction Riveting

Abstract This study investigates the thermal degradation and chemical transformations of friction-riveted glass fiber-reinforced epoxy laminate (FR4) printed circuit boards (PCBs) with different copper configurations. The primary objective is to identify the critical degradation temperatures and the impact of copper layers on joint integrity and thermal stability. Cross-sectional analyses revealed that joints produced at 250 °C exhibited minimal rivet deformation, while those at 360 °C showed significant deformation and increased epoxy degradation. Thermal analyses, including Differential Scanning Calorimetry (DSC) and Thermogravimetric Analysis (TGA), identified critical degradation temperatures at 327 °C for FR4-I Cu with a single copper layer and 329 °C for FR4-II Cu with double copper layers. The presence of the additional copper layer in FR4-II Cu significantly improved thermal stability, with total mass loss reduced from 29.8% (FR4-I Cu) to 23.5% (FR4-II Cu) at a heating rate of 20 °C/min. The loss of flame-retardant components at elevated temperatures raises concerns for the fire safety of PCBs in electronic devices. These findings highlight the importance of selecting appropriate FR4 configurations for applications exposed to high temperatures, enhancing reliability and safety in the electronics industry.

Chip warpage and stress analysis in power modules of different substrate configurations

Purpose This paper aims to use rigorous finite element simulations to investigate the impact of different substrate systems on the warpage behavior of silicon (Si) chips of power modules exposed to thermal loading. Design/methodology/approach Three common substrate systems: direct copper bonded (DCB), insulated metal substrate (IMS) and printed circuit board (PCB) configurations examined. In addition, three lead-free bonding materials: silver-tin transient liquid phase (TLP), sintered silver (Ag) and sintered copper (Cu). This results in nine assembly configurations. Finite element models of the electronic modules are developed using ANSYS to apply thermal loads from room temperature to 250°C to induce deformations, strains and stresses in the electronic structure. Accordingly, the silicon chip deformations and maximum principal stresses of each assembly configuration are thoroughly examined. Findings The results indicate that DCB-based power modules markedly reduce Si die warpage and maximum principal stresses, suggesting enhanced resistance to thermal loads. In contrast, IMS systems exhibit the highest levels of die warpage and out-of-plane deformation. PCB substrates, however, induce the highest maximum principal stress values in the silicon die, potentially leading to accelerated crack initiation and propagation. While the die attach system has a minimal effect on die warpage, the silver-tin TLP bonds generate significantly higher die stresses compared with sintered Ag and sintered Cu, which both result in reduced stresses. Originality/value Power electronics exceptionally rely on ceramic-based and polymer-based substrate systems due to their superior thermal conductivity, heat resistance and electrical insulation properties. The strategic selection of substrate structures can significantly enhance the robustness of power. Ultimately, the findings of this research provide valuable insights for the design of highly reliable and efficient power modules subjected to thermal stress.

Dual covalent bond induced high thermally conductive polyimide composite films based on CNT@CN complex filler

Dual covalent bond induced high thermally conductive polyimide composite films based on CNT@CN complex filler

Effect of Ni Addtion on Electroless Cu for High Density Interconnect PCB Substrate

Introduction Nowadays, high-density interconnect (HDI) printed circuit board (PCB) substrates have been widely applied to high-end electronics to meet the increasing input and output (I/O) density and small footprint area. Micro-via, a tiny structure buried among build-up layers that provide electrical interconnection is a key component in the HDI substrate. However, the preparation of micro-via is facing new challenges. It is not only required that the size of the micro-via scales down to meet the increased interconnect density, but also that the micro-via should withstand severe operating conditions in different scenarios. Therefore, it is of great importance to improve the quality of micro-vias during processing and manufacturing. The micro-via structure is a sandwich structure that is processed by electroless Cu plating and Cu electrolyte plating sequentially, and thus the quality of the electroless Cu layer can significantly affect the reliability of micro-via. In this work, we mainly focused on the electroless Cu plating process and investigated the effect of the electroless Cu deposition speed on the quality of the micro-via structure. SIM and HR-TEM characterizations were employed to investigate the micro-structure inside the electroless Cu layer. Materials and Method In this study, we used the common alkaline ion catalyst method to prepare the electroless Cu layer. The electroless Cu plating and electrolyte Cu plating was conducted on a PCB Resin Coated Copper (RCC) substrate that was cleaned by soft etching in an acid condition. The surface is then pre-dipped in an anionic solution, and palladium ions were adsorbed using an alkaline ion catalyst. The electroless Cu processes adopted in a reaction bath that consists of Cu resource (CuSO4·5H2O), complexing agent (KNaC4H4O6·4H2O) and reductant (HCHO). The whole reaction was conducted in the alkaline condition with a PH of 12.5, and the thickness of the electroless Cu deposition was controlled at around 0.20 µm. NiSO4 is selected as the Ni precursor to alter the Ni concentration in the reation bath. The contents of Ni addition were selected as 50 %, 100 %, 200 % and 300% of a conventional process at a bath temperature of 27 ºC. The thickness of the plated Cu layer was measured by a gravimetric method. Results and discussion TEM observation was used to identify the structure at the interface. Fig. 1 shows the TEM observation of the sample with 50 % and 200 % Ni concentrate. There are some nanovoids found at the interface between the Cu substrate and electroless Cu, which is arguably due to hydrogen generated during electroless Cu plating. The sample with a higher reaction speed has more nanovoids. It can be due to that the higher reaction speed can generate more hydrogen bubbles in the bath that can attach to the electroless Cu layer, leading to nanovoids as shown in Fig. 1. The samples prepared at different bath temperatures are under investigation to illustrate that the reaction speed can significantly affect the Cu electroless layer quality. Conclusions In this work, we investigated the Ni effect in electroless Cu on the RCC substrate. It is found that the higher Ni incorporation can lead to massive nanovoids generation and fine Cu grains in the electroless layer, which is a potential risk for the reliability of the HDI substrate. By reducing the Ni incorporation content, the number of nanovoids can be effectively reduced. Figure 1

Sustainable printed circuit board substrates based on flame-retarded PLA/flax composites to reduce environmental load of electronics: Quality, reliability, degradation and application tests

Sustainable printed circuit board substrates based on flame-retarded PLA/flax composites to reduce environmental load of electronics: Quality, reliability, degradation and application tests

Innovating in-situ characterization: a comprehensive measurement system for measuring the ZT and the contact resistance of vertical thermolegs exploiting the vertical transfer length method

In order to optimize their system design and manufacturing processes, it is crucial to undertake a thorough electrical and thermal characterization of micro thermoelectric generators (µTEGs). To address this need, a highly advanced and fully integrated in-situ measurement system has been developed. The main objectives of this system are to (1) enable the measurement of ZT and thereby of all thermoelectric (TE) properties of thermolegs made from powder-based TE materials and (2) at the same time accurately measure the contact resistance between the TE material and the electrical contacts. The µTEG fabrication concept used in this study is based on copper-cladded printed circuit board (PCB) material as a substrate, using the Cu layers for easy contact formation. In a first step, an innovative measurement concept, based on a distinctive vertical rendition of the well-established transfer length method, has been realized, allowing for the in-situ measurement of contact resistance between the TE material and the copper conductors on the PCB substrate. This enables a comprehensive assessment of the impact exerted by the applied force and temperature during e.g. a hot-pressing step for compacting the powder-based thermolegs during the manufacturing process. In a second step, a comprehensive measurement platform, referred to as the ZT-Card, has been devised to facilitate the evaluation of all relevant TE material properties—Seebeck voltage, electrical conductivity and thermal conductivity (all measured in vertical cross-plane orientation)—inherent to a highly miniaturized thermoleg. Additionally, the ZT-Card also allows for the assessment of contact resistance between the copper contacts and the TE material. Successful testing of this measurement system inspires confidence in the capabilities of the platform and will aid in future µTEG development.

Polyphenylene oxide/boron nitride–alumina hybrid composites with high thermal conductivity, low thermal expansion and ultralow dielectric loss

AbstractTraditional integrated circuit (IC) packaging materials and printed circuit board substrate materials suffer from several limitations including low thermal conductivity, high coefficient of thermal expansion (CTE), and poor dielectric properties. Although significant efforts have been made to enhance these properties, achieving a single composite system with simultaneous high thermal conductivity, extremely low CTE, and dielectric loss remains a formidable task. In this study, we propose a hybrid polymer composite system that addresses these challenges. Our approach involves utilizing a thermosetting polyphenylene oxide (PPO) as the resin matrix, while incorporating boron nitride (BN) sheets with high thermal conductivity and alumina (Al2O3) spheres with favorable fluidity as fillers. To optimize the composite properties, the filler surfaces are modified using dopamine and silane coupling agents, ensuring proper interface control. The composites exhibit significant improvements in thermal conductivity, reduced dielectric loss and CTE, while maintaining excellent processibility. Specifically, with a composition of 25 vol% BN and 25 vol% Al2O3, the thermal conductivity of the composite reaches 2.18 W·m−1 K−1, surpassing neat PPO resin by a factor of 10.9. Simultaneously, the CTE decreases from 2.27% to 1.18% between 50 and 260°C, and the dielectric loss reduces from 0.0024 to 0.0011 at 10 GHz, as compared to neat PPO resin.Highlights The reported novel hybrid composite offers a promising solution to the limitations of traditional IC packaging materials. The reported hybrid composite exhibits significantly improved thermal conductivity, ultralow dielectric loss, and reduced coefficient of thermal expansion, while maintaining excellent processibility. The thermal conductivity of the composites reaches 2.18 W·m−1 K−1, surpassing that of the neat resin by a factor of 10.9, meanwhile the dielectric loss is as low as 0.0011 at 10 GHz, which is extremely difficult to achieve simultaneously for thermosetting polymer composites. Synergetic effects were realized with the hybridization of fillers with different dimensionality, and proper filler surface modification.

Magneto‐electric dipole antenna array for 77 GHz automotive radar

AbstractA 1 × 4 magneto‐electric dipole (ME dipole) antenna array for 77 GHz automotive radar is proposed. The ME dipole is fed by a fork‐shaped microstrip line coupling through a dog‐bone slot. To meet the requirements aimed at automotive radar applications, the beamwidths of the proposed antenna are well‐designed. Specially, a method of adding passive elements on both sides of the array is proposed to increase the 3 dB beamwidth from ±34° to ±52° in azimuth. Additionally, in elevation, a 3 dB beamwidth of ±10° is achieved by designing the spacing between array elements. Moreover, based on low‐loss printed circuit board substrates, radiation efficiency of the proposed array can reach approximately 90% at 77 GHz. Furthermore, a 4 × 4 array is established by arranging four 1 × 4 subarrays spacing 1.95 mm (half a free‐space wavelength at 77 GHz) to study the interactions between subarrays for multiple input multiple output scenarios. A 1 × 4 and a 4 × 4 antenna prototypes are fabricated and measured to validate the correctness of this design. The results show that the proposed antenna is an eligible candidate for the medium‐ and short‐range automotive radars.

Monomer ratio‐controlled polyimides with enhanced dielectric properties and thermal stabilities through crosslinking network

AbstractPolyimides (PI) are considered as one of the most used materials for flexible printed circuit board substrates because of their excellent thermal stabilities, outstanding mechanical properties, and great dielectric properties. Dielectric constants (Dk) of common commercial PIs, however, are still above 3.0 (at 10 GHz), which is still substandard for high‐frequency applications. In this study, we develop thermally stable PIs with enhanced dielectric properties by structural design and crosslinking. Stiff aromatic 2,2′‐bis(trifluoromethyl)benzidine (TFMB) and soft aliphatic dimer diamines (DDA, priamine), including priamine 1074 (DDA‐1) and priamine 1071 (DDA‐2), are used as the diamines, and cyclobutanetetracarboxylic dianhydride (CBDA) is used as the dianhydride. By adjusting the ratio of the diamines, a series of PIs (PI‐1–PI‐5) with high thermal stabilities and low‐Dk values are synthesized. Among these PIs, PI‐4 synthesized by diamines with the ratio of TFMB:DDA‐1:DDA‐2 = 85:10:5, possesses relatively good performances. Therefore, PI‐4 is further chosen to be thermally crosslinked. By changing the contents of the crosslinker, triallyl isocyanurate (TAIC), crosslinked PIs (CPIs) are synthesized. The resulting CPIs have a significant improvement in thermal properties, dielectric properties, and mechanical strengths. Especially, for the CPI‐4‐30, in which 30% of TAIC is used, the glass transition temperature (Tg) increases by 20°C, the Dk decreases from 2.62 to 2.41, and the ultimate tensile strength boosts from 91.65 to 115.16 MPa. The CPIs with low Dk and high Tg values may have great potential as substrate materials for broad applications, such as microelectronics and integrated circuit packages.

A Green Conformable Thermoformed Printed Circuit Board Sourced from Renewable Materials.

Printed circuit boards (PCBs) physically support and connect electronic components to the implementation of complex circuits. The most widespread insulating substrate that also acts as a mechanical support in PCBs is commercially known as FR4, and it is a glass-fiber-reinforced epoxy resin laminate. FR4 has exceptional dielectric, mechanical, and thermal properties. However, it was designed without considering sustainability and end-of-life aspects, heavily contributing to the accumulation of electronic waste in the environment. Thus, greener alternatives that can be reprocessed, reused, biodegraded, or composted at the end of their function are needed. This work presents the development and characterization of a PCB substrate based on poly(lactic acid) and cotton fabric, a compostable alternative to the conventional FR4. The substrate has been developed by compression molding, a process compatible with the polymer industry. We demonstrate that conductive silver ink can be additively printed on the substrate's surface, as its morphology and wettability are similar to those of FR4. For example, the compostable PCB's water contact angle is 72°, close to FR4's contact angle of 64°. The developed substrate can be thermoformed to curved surfaces at low temperatures while preserving the conductivity of the silver tracks. The green substrate has a dielectric constant comparable to that of the standard FR4, showing a value of 5.6 and 4.6 at 10 and 100 kHz, respectively, which is close to the constant value of 4.6 of FR4. The substrate is suitable for microdrilling, a fundamental process for integrating electronic components to the PCB. We implemented a proof-of-principle circuit to control the blinking of LEDs on top of the PCB, comprising resistors, capacitors, LEDs, and a dual in-line package circuit timer. The developed PCB substrate represents a sustainable alternative to standard FR4 and could contribute to the reduction of the overwhelming load of electronic waste in landfills.

An ultrawideband antenna with two independently tunable notch bands

An ultrawideband antenna with two independently tunable notch bands

Analysis of Tempering Effects on LDS-MID and PCB Substrates for HF Applications

Mechatronic Integrated Devices or Molded Interconnect Devices (MID) are three-dimensional (3D) circuit carriers. They are mainly fabricated by laser direct structuring (LDS) and subsequent electroless copper plating of an injection molded 3D substrate. Such LDS-MID are used in many applications today, especially antennas. However, in high frequency (HF) systems in 5G and radar applications, the demand on 3D circuit carriers and antennas increases. Electroless copper, widely used in MID, has significantly lower electrical conductivity compared to pure copper. Its lower conductivity increases electrical loss, especially at higher frequencies, where signal budget is critical. Heat treatment of electroless copper deposits can improve their conductivity and adhesion to the 3D substrates. This paper investigates the effects induced by tempering processes on the metallization of LDS-MID substrates. As a reference, HF Printed Circuit Boards (PCB) substrates are also considered. Adhesion strength and conductivity measurements, as well as permittivity and loss angle measurements up to 1 GHz, were carried out before and after tempering processes. The main influencing factors on the tempering results were found to be tempering temperature, atmosphere, and time. Process parameters like the heating rate or applied surface finishes had only a minor impact on the results. It was found that tempering LDS-MID substrates can improve the copper adhesion and lower their electrical resistance significantly, especially for plastics with a high melting temperature. Both improvements could improve the reliability of LDS-MID, especially in high frequency applications. Firstly, because increased copper adhesion can prevent delamination and, secondly, because the lowered electrical resistance indicates, in accordance with the available literature, a more ductile copper metallization and thus a lower risk of microcracks.

Power Law Creep Behavior Model of Third Generation Lead-Free Alloys Considering Isothermal Aging

Abstract In realistic applications, the solder joint is continually subjected to thermal-mechanical stress due to the difference in the coefficient of thermal expansion between the printed circuit board substrate and the electronic packaging components. Creep and fatigue processes were the most common causes of failure in electronic assemblies. Under isothermal aging, creep deformation becomes more prominent. The aged microstructure was recognized by intermetallic coarsening and the appearance of intergranular fracture generated by dynamic recrystallization in the bulk solder joint. In this study, the influence of Bi content on the creep behaviors of solder joints was investigated under various aging conditions. Three lead-free solder alloys, including SAC305, SAC-3Bi, and SAC-6Bi, are tested at room temperature. For each alloy, preliminary micro-indentation tests were conducted to define three stress levels for distinct aging conditions. After each test, displacement versus time data was gathered. A novel approach based on an empirical model was developed to systematically examine the development of the steady-state creep rate. A power dependency prediction model was developed to investigate the relationship between creep strain rate and stress levels. The steady-state creep rate of SAC305 is significantly higher than that of SAC-Bi alloys owing to the presence of bismuth (Bi) in the solid solution at room temperature. The creep properties showed less variation after 100 h of aging. SAC-Bi alloys showed less coarsening of the intermetallic compounds precipitates after aging than SAC305. In the SAC-Bi solder alloys, combinations of precipitate and solid solution hardening mechanisms were observed, while Ag3Sn particles were the dominant strengthening mechanism in the SAC305 alloy system.

Copper from Waste Printed Circuit Boards Was Effectively Bioleached Using Newly Isolated Microorganisms and Subsequently Recovered by Microbial Fuel Cell

Two newly isolated bacterial strains were isolated from activated sludge and identified as Coniochaeta fodinicola (C. fodinicola) and Talaromyces barcinensis (T. barcinensis) by 16S rDNA. C. fodinicola and T. barcinensis were used to bioleach the copper from the waste printed circuit boards (WPCBs) powder, which was obtained by crushing and sorting the printed circuit board substrate after removing components. Results showed that the minimum and maximum Cu2+ leaching rates for C. fodinicola leaching were 3.9% and 89.2%, respectively. The minimum and maximum Cu2+ leaching rates for T. barcinensis leaching were 20.6% and 89.0%, respectively. The bioleaching solution was used as the cathode liquid of a dual chamber microbial fuel cell (MFC), and an X-ray diffraction (XRD) pattern displayed that the Cu2+ in the bioleaching solution was reduced to copper using biological electricity generation.

Concept and Process Development Using Ex Situ Fabricated High-Density Interconnect Plugs for Circuit-Board Embedded Magnetic Components

Magnetic circuit components have long been the largest and most difficult components to miniaturize. Printed circuit board (PCB) fabrication methods cannot achieve small diameter, high aspect-ratio vias for high winding turn numbers to achieve high inductance, and microelectronics methods cannot achieve the high-quality and thick ferrite core materials. In this paper, we present an alternative breakthrough method of printed circuit fabrication to significantly reduce the effective via diameter for embedded magnetic devices, boosting the inductance per unit area. To reduce the effective via diameter, high-density via plugs are ex-situ fabricated and shaped, and then embedded into PCB substrate in the same process as standard magnetic core embedding. The structure of the plug is such that precise placement within the substrate, or alignment to the plug with the winding pattern, is not necessary. Devices presented in this paper use via plugs with an effective diameter of 40 μm and a theoretically unlimited aspect ratio, though refinements in the plug fabrication process are expected to reduce the via diameter down to 10μm. The process is experimentally demonstrated with a 14-turn racetrack shaped transformer; novel diagnostic methods using magneto-optic garnet films to image current paths are also demonstrated.

D-Band Air-Filled Substrate Integrated Waveguide (AFSIW) and Broadband Stripline to AFSIW Launcher Embedded in Multi-Layer PCBs

We report <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$D$</tex-math> </inline-formula> -band air-filled substrate integrated waveguides (AFSIWs) with solid copper sidewalls fabricated inside a multi-layer printed circuit board (PCB) with broad wall width of 1.6 mm and cavity height of 300 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu$</tex-math> </inline-formula> m. Measurements show a loss of 0.07–0.08 dB/mm across 115–155 GHz. This result is the first demonstration of an AFSIW above 100 GHz in a low-cost mass manufacturable PCB and has the lowest loss compared to reported planar PCB lines or substrate integrated waveguides (SIWs) in PCBs and Interposers. We also introduce a broadband stripline to the AFSIW launcher using a broad wall transverse slot which offers ease of manufacturability over existing transitions having a measured insertion loss of 1.1 dB and 27% bandwidth. The combination of a low-loss AFSIW and wideband launcher allows both striplines and AFSIWs to coexist in the same multi-layer PCB.

A novel approach of fabricating low-cost high temperature printed circuit board substrate based on poly(ether-ketone)/fly ash composites

A novel approach of fabricating low-cost high temperature printed circuit board substrate based on poly(ether-ketone)/fly ash composites

Powder production from recycled low-density polyethylene waste and doum palm nuts for light weight engineering application: A circular economy approach

The circular economy approach has been established as a possible solution to the increasing menace of hazardous waste materials. Despite the advances in science and technology, the world still struggles with the disposal and management of low-density polyethylene (LDPE) waste. This study presents the potential of recycled waste LDPE known as “pure water sachets” (PWS) and doum palm nut (DPN) as raw materials for lightweight structural engineering applications. Powder samples were produced from the different compositions of PWS and DPN heated in a controlled environment. The heating temperatures ranged from 250 to 350 o C while the holding time was 60, 90, and 120 minutes. The fixed mass of each powder sample was compacted into cylindrical pellets, only G and H samples had sufficient strength to be handled after compaction. Sample G is a compact from the powder with 40% DPN, 60% PWS, heated to 350 o C for 60 minutes while sample H is from the powder with 60% DPN and 40% PWS, heated to 350 o C for 90 minutes. The micrographs showed that sample G was more homogeneous than sample H and contained fewer voids. F-TIR analysis conducted on the samples shows C-H functional group at 2915 and 2845 cm -1 , 1460 cm -1 , and 700 cm -1 which is similar to low-density polyethylene. The X-ray diffraction analysis conducted on the fabricated samples shows that the doum palm nut sample had an amorphous feature while the samples G and H show a semi-crystalline feature. The sample G had a density of 1.0 g/cm 3 and a hardness value of 10.2 HV making it useful for Printed circuit board substrates. • This study is concerned with taking advantage of the vast amount of plastic and agro-waste and recycling to develop compatible powder for lightweight engineering applications e.g. printed circuit board substrates. Doum palm nut (DPN) and waste pure water sachet were processed into powder using different heating temperature regimes and different holding times. The chemical, mechanical and thermal behavior of the compacted powder was investigated.

A customizable cost-effective design for printed circuit board-based nanolayered gold screen-printed electrode: From fabrication to bioapplications.

Screen-printed electrodes (SPEs) are promising candidates for fabricating biosensing platforms in the laboratory and industry due to the various advantages they involve. The primary method for fabricating SPEs is 2D printing. However, commercial SPEs have some limitations due to the specific ports and connections they require, inflexible design, high prices, and decreased efficiency after a short time. This article introduces high performance, feasible, and cost-effective gold SPEs based on the combination of printed circuit board substrate (PCBs) and sputtering methods for electrochemical biosensing platforms. First, we discuss a general gold SPE development procedure that helps researchers to develop specific designs. The final developed version of SPEs was characterized in the second step, showing positive performance in electrochemical parameters because of the optimization of design and fabrication steps. In the study's final phase, SPEs were used to fabricate a simple platform for breast cancer cell detection as a proof of concept without using any linker or labeling step. The designed immunosensor is very simple and cost-effective, showing a linear calibration curve in the range of 10 - 2× 102 cellsmL-1 (R 2 = 0.985, S/N = 3). This research can be used as a reference for future studies in SPEs-based biosensors because of the flexibility of its design and the accessibility of the manufacturing equipment required.

Research on the Reliability of a Core Control Unit of Highway Electromechanical Equipment Based on Virtual Sensor Data.

The printed circuit board (PCB) is the core control unit of electromechanical equipment. In order to determine the influence of the coupling vibration caused by vehicle–road interaction on the PCB reliability of roadside electromechanical equipment, first, the dynamic load of the vehicle tire is solved by establishing the dynamic model of a vehicle road. Then, the acceleration response data generated by road vibration are obtained by solving the road finite element model. Finally, the power density spectrum of the acceleration response is taken as input excitation, and the deformation response of the PCB under vehicle–road coupling vibration is analyzed. The experimental results show that when the vehicle is driving close to the roadside, the vibration caused by vehicle–road coupling will lead to a large deformation of the PCB, and the deformation value reaches 0.170 mm, which can cause structural damage to the PCB. This shows that the vehicle–road coupling vibration can affect the reliability of the roadside electromechanical equipment; thus, the optimal design of the PCB layout is created. After optimization, the first-order modal frequency of the PCB is increase by 5.4%, which reduces the risk of the components breaking away from the PCB substrate.