Printed Circuit Board Test Research Articles

Boundary-scan bursts into the modern production facility

The IEEE 1149.1 boundary-scan standard was adopted ten years ago to solve anticipated problems in printed circuit board testing as board densities and complexities continued to escalate. We can see today that the foresight of the original JTAG committee was excellent. For several years after adoption of the standard, relatively few users had implemented boundary-scan solutions in their production lines. Now, however, for a number of reasons, interest in boundary-scan has rapidly intensified: (i) IC manufacturers have accepted boundary-scan as a feature that must be included in new ICs; (ii) Advances in board and IC Packaging technologies have accelerated, making new test strategies imperative; and (iii) Standard tools for engineering and production are now available to support boundary-scan, dramatically reducing test development effort, capital investments, along with a corresponding reduction in time to market. As a result, virtually every manufacturer of modern electronic boards has either adopted boundary-scan or faces difficult problems in manufacturing that could be resolved through boundary-scan. This presentation examines recent developments in boundary-scan technology as it relates to the development and production environments. Advanced tools, packaged to meet the needs of these environments, have brought boundary-scan into its prime. A detailed description of life-cycle implementation of boundary-scan is provided covering R&D, the factory, and service.

Nanotechnology-based molecular test equipment (MTE)

This paper describes original research efforts in the design, simulation, and development of nanotechnology-based molecular test equipment (MTE). This is a research effort for testing printed circuit boards independent of traditional automatic test equipment (ATE) through the fabrication of MTE within integrated circuits (ICs). The MTE is embedded within the IC substrate and encapsulated within nanoprobes that connect between the surface and the substrate of the IC at various functional areas. A process is followed whereby IC device simulation is performed to assess the electrical, chemical, and structural properties of integrated and adjacent substrate devices. Through this approach the nominal and failed device performance parameters of interest to substrate-based MTE are found. Discussion of the development and application of MTE within IC architectures is provided, including such topics as the effect of substrate composition on the design and realization of MTE, interfaces between MTE and IC devices, and reporting of MTE results to the IC surface and technician. Potential application areas within different device functions will also be identified. A chemical structure diagram is also provided to illustrate the implementation of MTE using discrete device configurations with MTE-augmented logic.

HIGHLY ACCELERATED SOLDER JOINT RELIABILITY TEST USING A THERMO-MECHANICAL DEFLECTION SYSTEM (TMDS)

A Thermo-Mechanical Deflection System (TMDS) test method has been developed for evaluating the fatigue performance of solder joints in printed circuit board (PCB) assemblies. The TMDS test imparts cyclic twisting deflections on an assembled PCB test vehicle which is tested under controlled iso-thermal conditions in a thermal chamber. Tests were conducted at various angles of twist and isothermal conditions at 100°C and 25°C. Failure analysis using SEM showed that the solder joint failure for the TMDS test is comparable to the failure mechanisms for ATC test failures for solder joints. Weibull failure distribution plots for TMDS and ATC tests were compared and a Scale Factor (SF) was used to correlate the test results.

Experimental and numerical investigation into the influence of printed circuit board construction on component operating temperature in natural convection

The steady state thermal performance of an isolated SO-8 package is experimentally characterized on five thermal test printed circuit boards (PCBs) and the results compared against corresponding numerical predictions. The study includes the low and high conductivity JEDEC standard, FR4 test PCBs and typical application boards. With each PCB displaying a different internal structure and effective thermal conductivity, this study highlights the sensitivity of component operating temperature to the PCB, provides benchmark data for validating PCB numerical modeling methodologies, and helps one assess the applicability of standard junction-to-ambient thermal resistance (/spl theta//sub JA/) data for design purposes on nonstandard PCBs. Measurements of junction temperature and component-PCB surface temperature distributions were used to identify the most appropriate modeling methodology for both the component and the PCB. Based on these results, a new PCB modeling methodology is proposed that conserves the need for modeling detail without compromising prediction accuracy.

A new macro/micro robotic probing system for the in-circuit test of PCBs

This paper presents a new macro/micro robotic probing system developed for the in-circuit test of printed circuit boards (PCBs). Commercially available robotic probing devices are likely to generate excessive contact force due to their uncontrollability, as a rigid probe makes a contact with a less rigid, plastically deformable solder joint at high speed. Since the conventional probing mechanism has only passive compliance, it cannot effectively control such a large contact force. This uncontrollable excessive contact force often makes some defects on the surface of the solder joint and oscillatory motions of the probe, resulting in unreliable test data. In addition, contact with a steep surface of the solder joint makes slip motion of the probe tip onto the surface. To overcome these problems, we propose a serially connected macro and micro robotic probing device equipped with active compliance capability and sensing ability of surface conditions of the solder joint in real-time. This paper describes its design characteristics and control scheme of the newly proposed device. The effectiveness of the proposed probing system is verified through a series of experiments.

The use of knowledge-based systems for PCB testing and repair

Abstract Based on a standardized, product- and production-independent concept and realization for factory automation, this paper presents a fault location and elimination concept using knowledge-based systems for the purpose of automating quality control procedures (CAQ) in printed circuit board (PCB) manufacturing. The goal of this concept is to achieve an uninterrupted flow of information in both directions, to and from the manufacturing environment, and data supported work processes. Besides the measurement test of the product performed by using the terminal measurement procedure, knowledge-based systems are presented. These are written in the programming language PROLOG, and each consists of an inference component, a knowledge base and a dialogue component. The systems permit comparative statements to the measurement tests of the product PCB. An example of this is the impedance calculation of electrical circuits or networks. Pattern recognition procedures are also part of these systems. The knowledge-based systems can be used not only to determine the analysis of electrical circuits or networks on the base of impedance calculation of resistors, as can be seen from this paper, but also can be applied to circuits or networks with linear, nonlinear, and digital components or elements, or to circuits or networks with star-delta connection.

4907230 Apparatus and method for testing printed circuit boards and their components

Apparatus and method for testing electrical circuits, especially printed circuit boards containing a number of integrated circuit components. Access to the component to be tested is by means of a clip with driver/sensor pins having field effect transistor circuitry. Each pin corresponds to an access point on the device under test, and each pin includes its own circuitry for driving the inputs and sensing the outputs of both analog and digital components. The test instrumentation is integrated with a host microcomputer, eliminating the need for "memory behind the pins". Test programming directs the test instrumentation to perform functional testing while the components are in circuit and to test for in-circuit component parameters. The invention provides automatic test generation, including means for learning the characteristics of known good components and boards. The invention also provides expert system programming for recording and analyzing test results data and for using this data to generate faster tests.

The benefits of using ATE systems in the testing of printed circuit boards

An industry-based pragmatic review is provided of the economic and product-quality consequences of automatic test equipment (ATE) usage in printed circuit board testing. The company selection process, the nature of the industrial participants, and the data collection process are described. The benefits obtained by users are identified. It is demonstrated that the use of ATE systems does result in definable economic and quality-level benefits.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Economics of Bare Printed Circuit Board Testing

The increasing complexity of today's Printed Circuit Boards inevitably leads to higher failure rates at the assembled board and product levels. Electrical testing of PCBs at the bare board level always results in early identification of failures, and thus in increased production economies. The escalating costs to identify faults at various levels of the PCB manufacturing and assembly process are discussed and illustrated. The typical PCB spectrum of faults, including contamination, shorts, opens, and holes is discussed, along with reliable methods of fault removal. In addition to the economic factors such as capital equipment cost, programming, fixturing, and operating costs, several technical factors are discussed and illustrated. These include test comprehensiveness and test speed. Since fault coverage is directly proportional to the measurement capability of the test equipment, the effects of measurement threshold on fault coverage and the resultant failure rates at the assembled board and product levels are discussed and illustrated. The importance of using the standard 100 megohm threshold is also discussed and illustrated.

4465972 Connection arrangement for printed circuit board testing apparatus

4465972 Connection arrangement for printed circuit board testing apparatus

International quality control—cooperation in an overview : J. M. Juran. Quality Prog. p. 14/15 (July 1979)

The goal of this research is to develop a systematic, accurate and robust method for printed circuit board (PCB) positioning evaluation in the testing fixture. Theoretical analysis and experimental observation of tolerance distribution in bed-of-nails fixture were involved. Actual deformation of PCB (translation, rotation and deflection) could be obtained based upon a proposed model. The combined accuracy of the test lands positioning (false failure rate) were estimated by the Weibull distribution. All data processing was finished by MATLAB. Results will be helpful for evaluation of the minimal size of the PCB test lands and modification of the testing fixtures.

An application of graph coloring to printed circuit testing

A proposed method for testing printed circuit boards for the existence of possible (undesired) short circuits transforms the test minimization problem into one of finding minimum vertex colorings of certain special graphs, called line-of-sight graphs. Under certain assumptions on the possible types of short circuits, we analyze the structure of such graphs and show that a well known and efficient algorithm can be used to color them with a small number of colors. In particular, we show that no more than 5, 8, or 12 colors (depending on the particular assumptions) will ever be required for such a graph, independent of the number of vertices. Thus, in such cases, the potential advantage of the proposed method over exhaustive testing could be considerable.