Printed Circuit Board Area Research Articles

A New Reconfigurable Filter Based on a Single Electromagnetic Bandgap Honey Comb Geometry Cell

This work presents a new unit cell electromagnetic bandgap (EBG) design based on HoneyComb geometry (HCPBG). The new HCPBG takes a uniplanar geometry (UCPBG—uniplanar compact PBG) as a reference and follows similar design methods for defining geometric parameters. The new structure’s advantages consist of reduced occupied printed circuit board area and flexible rejection band properties. In addition, rotation and slight geometry modification in the HCPBG cell allow changing the profile of the attenuation frequency range. This paper also presents a reconfigurable unit cell HCPBG filter strategy, for which the resonance center frequency is shifted by changing the gap capacitance with the assistance of varactor diodes. The HCPBG filter and reconfiguration behavior is demonstrated through electromagnetic (EM) simulations over the FR1 band of the 5G communication network. Intelligent communication systems can use the reconfiguration feature to select the optimal operating frequency for maximum attenuation of unwanted or interfering signals, such as harmonics or intermodulation products.

Heat Dissipation Derivation and Optimization of the Fan-Out 3-D Package Model

Heat dissipation of the fan-out (FO) package is a primary concern in advanced electronic packaging. It is a challenge to characterize the thermal performance using the actual geometry of the FO package due to the complex structure and time-consuming calculations. A simplified FO model was constructed based on the equivalent material principle and the mathematical FO model was validated by using the finite element (FE) simulation. Then FO-package thermal resistance network (FO-TRN) was established to evaluate the thermal performance, which was proven efficient and accurate by the simulation of FE models. The influence of the critical dimension (CD) of redistribution line (RDL), the thermal conductivity of molding material, and the printed circuit board (PCB) area were also investigated by using the FE simulation and FO-TRN calculation. The results demonstrated that the smaller the CD of RDLs, the greater the thermal resistance of the FO package. The high thermal conductivity of the molding compound and large PCB area is beneficial for heat dissipation. The simplified FO model and FO-TRN are practicable and effective for thermal characterization and management.

New Version of High-Damping PCB with Multi-Layered Viscous Lamina

In a previous study, a high-damping printed circuit board (PCB) implemented by multilayered viscoelastic acrylic tapes was investigated to increase the fatigue life of solder joints of electronic packages by vibration attenuation in a random vibration environment. However, the main drawback of this concept is its inability to mount electronic parts on the PCB surface area occupied by interlaminated layers. For the efficient spatial accommodation of electronics, this paper proposes a new version of a high-damping PCB with multilayered viscoelastic tapes interlaminated on a thin metal stiffener spaced from a PCB. Compared to the previous study, this concept ensures efficient utilization of the PCB area for mounting electronic parts as well as the vibration attenuation capability. Free vibration tests were performed at various temperatures to obtain the basic characteristics of the proposed PCB. The effectiveness of the proposed PCB was verified by random vibration fatigue tests of sample PCBs with various numbers of viscoelastic layers to compare the fatigue life of electronic packages.

Thermal Design Optimization of the Printed Circuit Board through Area Reduction

The dimensions of an electronic control unit are extremely important in the developing of any new product design. It is well known that a large area of the printed circuit board (PCB) increases thermal performance. For any developed product, when the PCB area is enlarged, the volume, the mass, and the surroundings also increase. This article presents how the shape is more important than the area and the way in which the area of the PCB can be reduced but still has similar or even better thermal performance. An response surface methodology (RSM) of the design of experiments (DOE) quality tool from optimization phase of design for six sigma concept was developed using MINITAB statistical software. The results for each DOE combination of length and width were simulated as a parametric run by the ICEPAK version 19.1 commercial software, which is based on the finite volume method. Numerical analyzes check the obtained transfer function for other dimensions than those analyzed in response surface DOE and it is extrapolated for different areas. With the obtained and numerically checked RSM transfer function, it is recognized a significantly better thermal performance for the same area of the PCB, but with a smaller dimension in the airflow direction.

A Mixed-Signal Adaptive Ripple Canceler for Switching Regulators Providing 18 dB-24 dB of Ripple Rejection up to 1 MHz

A mixed-signal adaptive ripple canceller for reducing switching noise and spurious emissions in switching regulators is presented. The proposed mixed-signal ripple suppression technique tracks and cancels the switching noise by utilizing two schemes: A primary mixed-signal adaptive ripple canceller that provides large signal ripple cancellation up to 20 dB, and an auxiliary linear amplifier-based ripple canceller that minimizes the residual ripple content, achieving a combined ripple rejection of 24 dB. Proposed approach operates without the need for external components, reducing overall printed circuit board area without loss of efficiency. The adaptive ripple canceller is designed and fabricated in a 250 nm CMOS process with four levels of metal. The ripple-canceller is integrated with an on-chip buck regulator to characterize its rejection effectiveness. The ripple canceller can also be utilized as a stand-alone ripple cleaner module with an external commercial-off-the-shelf (COTS) switching regulator. The proposed ripple canceller can track and cancel power supply ripple up to 1 MHz with 24 dB rejection and reduces ripple content up to fourth harmonic by at least 20 dB while supporting dc loads up to 1 A and ripple currents up to 350 mApk-pk. The proposed approach achieves 30% lower quiescent current than using a linear low-dropout regulator without the need for any external components.

Electronics system thermal management optimization using finite element and Nelder-Mead method

The demand for high-performance, smaller-sized, and multi-functional electronics component poses a great challenge to the thermal management issues in a printed circuit board (PCB) design. Moreover, this thermal problem can affect the lifespan, performance, and the reliability of the electronic system. This project presents the simulation of an optimal thermal distribution for various samples of electronics components arrangement on PCB. The objectives are to find the optimum components arrangement with minimal heat dissipation and cover small PCB area. Nelder-Mead Optimization (NMO) with Finite Element method has been used to solve these multi-objective problems. The results show that with the proper arrangement of electronics components, the area of PCB has been reduced by 26% while the temperature of components is able to reduce up to 40%. Therefore, this study significantly benefits for the case of thermal management and performance improvement onto the electronic product and system.

GaN VHF Converters With Integrated Air-Core Transformers

This paper proposes an air-core transformer integration method, which mounts the transformer straight into the multilayer printed circuit board (PCB), and maintains a proper distance between the inner transformer and other components on the top layer. The integration method reduces the PCB area significantly, ensuring higher power density. The design of the complete structure is accomplished with finite element analysis (FEA) to ensure that the unconstrained transformer magnetic field does not affect other components. It is applied to three resonant flyback converters operating at 20 MHz with Si mosfet s, 30 MHz, and 50 MHz with enhancement-mode gallium nitride (eGaN) high-electron mobility transistors, respectively. The 30-MHz eGaN prototype achieves the full load efficiency of 80.1% (an increase of 1.1% compared with the 20-MHz Si prototype) and power density of 32 W/in3 at 5-V input and 5 V/ 2 W output. The 50-MHz eGaN prototype achieves the power density of 39.4 W/in3, which is 41% higher than the 20-MHz Si prototype. With the similar efficiency, the overall height of the converters in this paper is less than half of the commercial products, very suitable for low thickness and profile applications.

A compact Class D RF power amplifier for mobile nuclear magnetic resonance systems.

A 20 MHz Class D amplifier with an output of 100 W of RF power has been developed. The compact size printed circuit board area of 50 cm2 and efficiency of 73% make it suitable for mobile nuclear magnetic resonance (NMR) systems. Test results show that the rise and ring down times of the amplifier are less than 0.2 μs, and it is capable of producing constant amplitude pulses as short as 2 μs. Experiments using a Carr Purcell Meiboom Gill pulse sequence with a NMR MOUSE sensor confirm that the Class D amplifier is suitable for mobile NMR applications.

Design of a compact, fully‐autonomous 433 MHz tunable antenna for wearable wireless sensor applications

The authors present the design of a tunable 433 MHz antenna that is tailored for wearable wireless sensor applications. This study first presents a detailed analysis of the measured impedance characteristics of a chosen antenna under test (AUT) in varying proximity to a human test subject. Instead of limiting the analysis to the head and hand only, this analysis measures the AUT impedance at varying distances from 11 different body positions. A novel antenna equivalent circuit model is then developed that enables both the free-space and total on-body AUT impedance variation to be rapidly computed using a circuit simulator instead of the requirement for computationally intensive finite-element methods for example. The design and characterisation of a tunable matching network that enables AUT impedance matching for 11 different positions on the human body is then outlined. Finally, a fully-autonomous 433 MHz tunable antenna is demonstrated. The antenna occupies a small printed circuit board area of 51 × 28 mm and is printed on standard FR-4 material with the tuner completely integrated into the antenna itself. Prototype measurements show an improvement of 3.9 dB in power delivery to the antenna for a load voltage standing wave ratio of 17:1, with a maximum matching loss of 0.84 dB and S 11 (−10 dB) ≥ 18 MHz for all load conditions.

VRSPV Soft-Start Strategy and AICS Technique for Boost Converters to Improve the Start-Up Performance

Soft-start strategy is very important for boost converters to guarantee the stability of the output voltage. However, previous methods may cause large initial inrush current and long output voltage settling time. In this paper, a variable ramp-slope with predefined voltage (VRSPV) soft-start strategy is proposed. As a result, one branch of the initial inrush current is successfully eliminated and the output settling time of the boost converter is shortened by using the variable slope soft-start voltage. Also, an adaptive inrush current suppressing (AICS) technique is designed. The series resistance of the output capacitor is adaptively regulated by AICS technique to further suppress the initial inrush current. Finally, the VRSPV strategy and AICS technique are combined and implemented in a voltage-mode boost converter. The measurement results show that the peak initial inrush current and settling time are decreased by 60% and 40%, respectively. The output voltage of the boost converter increases smoothly during the soft-start period and finally achieves stability. The proposed method of combining VRSPV strategy and AICS technique is very suitable to be integrated on a chip to save the printed circuit board area and cost.

Low-Input Power-Level CMOS RF Energy-Harvesting Front End

RF energy-harvesting front ends consist of $LC$ matching networks and RF rectifiers. The minimum detectable power (sensitivity) is dependent on the losses of both parts. In this paper, RF energy-harvesting sensitivity limits at steady state and design tradeoffs for matching networks and rectifiers are introduced. These limits and tradeoffs are examined for standard CMOS 0.18- $\mu$ m technology. Two designs, one with off-chip matching network and the other with on-chip matching network, are presented, compared, and measured for an output voltage of 1 V. The sensitivity of the off-chip design is ${-}{\hbox{27.3}}$ dBm while taking 180 $\,\times\,$ 90 $\mu$ m $^{2}$ die area and off-chip high quality inductor and capacitor, which takes an extra 7.28 mm $^{2}$ printed circuit board area. The fully integrated on-chip design has a sensitivity of ${-}{\hbox{21.7}}$ dBm while taking 820 $\,\times\,$ 450 $\mu$ m $^{2}$ die area. The sensitivity of the former proved superior while the latter is more attractive in terms of compactness, low cost, and easier tunability.

UV laser cutting of glass-epoxy material for opening flexible areas of rigid-flex PCB

Purpose – The purpose of this paper is to form good cutting qualities in glass-epoxy material for opening flexible areas of rigid-flex printed circuit boards (PCB) by ultraviolet (UV) laser cutting. Design/methodology/approach – The cut width and cut depth of glass-epoxy materials were both observed to evaluate their cutting qualities. The heat affected zone (HAZ) of the glass-epoxy material was also investigated after UV laser cutting. The relationships between the cut width and the parameters of various factors were analyzed using an orthogonal experimental design. Findings – The cut width of the glass-epoxy material gradually increased with the increment of the laser power and Z-axis height, while cutting speed and laser frequency had less effect on the cut width. Optimal parameters of the UV laser process for cutting glass-epoxy material were obtained and included a laser power of 6W, a cutting speed of 170 mm/s, a laser frequency of 50 kHz and a Z-axis height of 0.6 mm, resulting in an average cut width of 25 μm and small HAZ. Originality/value – Flexible areas of rigid-flex PCBs are in good agreement with the cutting qualities of the UV laser. The use of a UV laser process could have important potential for cutting glass-epoxy materials used in the PCB industry.

Applications of Emerging Parallel Optical Link Technology to High Energy Physics Experiments

Modern particle detectors depend upon optical fiber links to deliver event data to upstream trigger and data processing systems. Future detector systems can benefit from the development of dense arrangements of high speed optical links emerging from the telecommunications and storage area network market segments. These links support data transfers in each direction at rates up to 120 Gbps in packages that minimize or even eliminate edge connector requirements. Emerging products include a class of devices known as optical engines which permit assembly of the optical transceivers in close proximity to the electrical interfaces of ASICs and FPGAs which handle the data in parallel electrical format. Such assemblies will reduce required printed circuit board area and minimize electromagnetic interference and susceptibility. We will present test results of some of these parallel components and report on the development of pluggable FPGA Mezzanine Cards equipped with optical engines to provide to collaborators on the Versatile Link Common Project for the HI-LHC at CERN.

Optimization of electronics component placement design on PCB using self organizing genetic algorithm (SOGA)

The optimal placement of electronic components on a printed circuit board (PCB) requires satisfying multiple conflicting design objectives as most of the components have different power dissipation, operating temperature, types of material and dimension. In addition, most electronic companies are currently emphasizing on designing a smaller package electronic system in order to increase the system performance. This paper presents a new self organizing genetic algorithm (SOGA) method for solving this multi-objective optimization problem. The SOGA can be viewed as a cascade of two GAs which consists of two steps fitness evaluation process to ensure that the fitness of selected chromosomes for each iteration process is optimally selected. The algorithm is developed based on weighted sum approach genetic algorithm (WSGA) where an inner loop GA is used to optimize the selection of weights of the WSGA. Experiments are conducted to evaluate the performance of SOGA. Four objective functions are formulated in the experiments which are temperature of components, area of PCB, high power component placement and high potential critical components distance. Comparisons of the performance of SOGA are made with two well known methods namely fixed weight GA (FWGA) and random weighted GA (RWGA). The results show that the SOGA gives a better optimal solution as compared to the other methods.

Adding microstrip line at the bottom of PCB for enhancing antenna bandwidth

AbstractIn this article, added microstrip line at the bottom area of printed circuit board (PCB) is proposed for improving the bandwidth of GSM900, DCS1800, and PCS1900. By printing the microstrip line at the bottom area of PCB, frequency bandwidth of slim‐type cellular phone which has a low‐profile monopole antenna is improved. Dimension of the microstrip line is 45 mm × 9 mm. The width and length of the microstrip line is modified for good bandwidth. The measured return loss of the antenna is better than 7.3 dB for low and high band. Measured peak gains of the proposed antenna present 3.41, 5.48, and 5.95 dBi in each band, respectively. Details of the antenna design are described. Its performances are also presented. © 2010 Wiley Periodicals, Inc. Microwave Opt Technol Lett 52: 1984–1988, 2010; Published online in Wiley InterScience (www.interscience. wiley.com). DOI 10.1002/mop.25399

Impact of a Frequency Modulated Pulsewidth Modulation (PWM) Switching Converter on the Input Power System Quality

In this paper, we show that a frequency modulated (FM) source of conducted emission has an adverse effect on a dc power system, although it is believed that frequency modulation of the interferer reduces such effects. Spread spectrum modulation is a commonly proposed technique of electromagnetic interference (EMI) reduction. It is often suggested that an FM pulsewidth modulation ramp be used in a voltage mode controlled dc-dc switching converter for reduction of conducted and radiated EMI. However, this paper shows that this technique is not as beneficial as is commonly perceived. The power quality standard MIL-STD 704, which is the origin of the EMI standard MIL-STD 461, puts restriction on several parameters other than the frequency spectrum of the disturbance, which is the only parameter that is specified in the EMI norms and tested in electromagnetic compatibility (EMC) tests. In this paper, we show that different interferers which are compatible to the same EMC limit, may affect the same power system differently. This difference is noticed if the other power quality parameters are considered. We have also mentioned that the actual benefit from spread spectrum modulation-based EMI reduction depends on the savings in printed circuit board (PCB) footprint area that we get by using a smaller filter. Through a numerical study, we have shown that such a method leads to only a negligible savings in PCB area in spite of significant EMI reduction. Moreover, this brings about a degraded performance on the other parameters that are not normally checked in EMI tests.

A Parallel-Structure Solder Paste Inspection System

In this paper, we present an innovative design of a solder paste inspection system that can be practically integrated into existing solder paste printing machines. Since solder paste inspection systems usually occupy a large vertical space, we designed a mirror box that can redirect the transmission of fringe patterns. In this way, a new parallel-structure solder paste inspection system with a significant reduction in the vertical constraint is developed. We also developed a hybrid weighting algorithm that applies the distance and fringe contrast to acquire the height of solder pastes. Furthermore, we developed an algorithm that generates the 2-D image from the fringe pattern images during the four-step algorithm. It reduces the time required for solder paste inspection compared to traditional approaches that use special lighting systems to create the 2-D image. Based on the results of the height acquisition algorithm, 2-D and 3-D solder paste inspections are performed. Experimental results show that our system can inspect a 20 mm times 20 mm printed circuit board area within 2 s to detect common 2-D and 3-D defects, and the maximum standard deviation for the average height is 3 mum.

Low Profile Switchmode Converter with Embedded Passive Components in the PCB

Technologies are now available to embed circuit functionality into the printed circuit board (PCB) that is used to interconnect the various components of a power electronics converter. Technologies are presented for realizing capacitive, magnetic and resistive functions in a multilayer PCB. It is suggested that in planar magnetic cores be combined with ferroelectric capacitor sheets together with new surface mount components to enhance the reactive power capability of the passive components. Two case studies are presented illustrating the possibilities that the new technologies offer. The capacitance values needed for switchmode power conversion is analyzed and possibility to embed these capacitors in the PCB is investigated. Two factors that limit the power handling capability in low profile converters with embedded passive components are identified and analyzed, namely the ratio of PCB area to component area and role that the third dimension plays in planar converters.

Reduction of crosstalk noise in modular jack for high-speed differential signal interconnection

Crosstalk noise has become a significant problem in the design of high-speed digital interconnections. In this paper, we demonstrate a crosstalk reduction method, which has been successfully applied to the design of a CAT-5E modular jack. The CAT-5E is a newly adopted cabling and connector standard for advanced cabling network systems to assure more robust, reliable and high-speed operation, which is based on differential mode signal transmission using unshielded twist pair (UTP) cable. The improved design of the modular jack shows minimal crosstalk noise and return loss over a wide range of manufacturing conditions. The improved crosstalk characteristics of the modular jack were accomplished by inserting embedded capacitors on the printed circuit board (PCB) of the modular jack. The embedded capacitors compensate for the unbalanced capacitive crosstalk that occurs in the plug and insert. In particular, the embedded balancing capacitor is designed to have maximum capacitance, with limited PCB area, by using a double-sided PCB design. Less than -45 dB near-end-crosstalk (NEXT) was achieved after the crosstalk noise compensation, satisfying the CAT-5E specification for frequencies up to 100 MHz.

A 10.7-MHz CMOS SC radio IF filter using orthogonal hardware modulation

FM radio receivers require an IF filter for channel selection, customarily set at an IF center frequency of 10.7 MHz. Up until now, the limitations of integrated radio selectivity filters in terms of power dissipation, dynamic range, and cost are such that it is still required to use an external ceramic 10.7-MHz bandpass filter. This paper demonstrates a CMOS switched-capacitor IF filter that can be integrated with most of the rest of the FM receiver, eliminating external components and printed circuit board area. This is made possible through a combination of two techniques: orthogonal hardware modulation, and delta-charge redistribution. It exhibits a tightly controlled center frequency with a Q of 55 and also contains a programmable gain. The filter occupies an area of 0.7 mm/sup 2/ in a 0.6 /spl mu/m CMOS process with poly-poly capacitors. The new filter requires only 16 mW of power, and this is offset by elimination of the power needed in current designs to drive off-chip filters.