Primary Input Sequences Research Articles

Invisible-Scan: A Design-for-Testability Approach for Functional Test Sequences

Functional test sequences can detect defects that are not detected by scan-based tests, but overall, achieve a lower gate-level fault coverage than scan-based tests. Design-for-testability (DFT) approaches for functional test sequences cause the sequences to deviate from functional operation conditions in arbitrary ways over the entire design. This paper introduces the concept of invisible-DFT as a DFT approach for functional test sequences, where the effects of activating the DFT logic are confined to selected logic blocks. This paper develops an invisible-scan approach. Considering a single logic block, the procedure described in this paper inserts scan shift cycles into a functional test sequence while maintaining the same primary input and output sequences for the logic block. This makes the activation of the DFT logic invisible to other logic blocks. The procedure allows a limited number of primary output vectors to be corrected for this purpose. Experimental results are presented to demonstrate the increase in fault coverage that can be achieved by invisible-scan.

An Initialization Process to Support Online Testing Based on Output Comparison for Identical Finite-State Machines

Identical instances of a logic block are included in a design to improve its performance or reliability. This allows instances at close proximity to be tested by comparing their output responses, alleviating the need to know which tests will be applied, or what the fault-free response is. This paper considers an approach to online testing where the primary output sequences of identical finite-state machines that receive the same primary input sequences are compared to detect faults. To address the hardware and delay overheads of bringing one of the machines to the same state as the other before starting the output comparison process, this paper describes an initialization process where only part of the state of one machine is loaded into the other, and subsequences of their common primary input sequences are used for completing the initialization process. A unique feature of this process is that it addresses the situation where the input sequences that are applied during online testing, and the initial state for output comparison, are unknown. With this initialization process it is possible to start the output comparison process at an arbitrary point during functional operation. Experimental results for benchmark circuits demonstrate the percentages of state variables who values need to be loaded from one machine to the other, the fault coverage that can be achieved by output comparison following initialization, and the occurrence of failures in the initialization process.

On‐chip generation of primary input sequences for multicycle functional broadside tests

Functional broadside tests are important for avoiding overtesting of delay faults during the application of scan-based tests. Multicycle tests have advantages in defect detection and test compaction. This study addresses the on-chip generation of primary input sequences for the application of multicycle functional broadside tests to a circuit that is embedded in a larger design. In this study, multicycle functional broadside tests are considered under two types of constraints: (i) functional constraints that the design imposes on the primary input patterns of the circuit, and (ii) test application constraints when direct access to the primary inputs of the circuit is not available, and the application of two or more consecutive primary input patterns requires hardware support. The use of multicycle functional broadside tests also results in an increased fault coverage.

On-chip Generation of Functional Tests with Reduced Delay and Power

This paper describes different methods on-chip test generation method for functional tests. The hardware was based on application of primary input sequences in order to allow the circuit to produce reachable states. Random primary input sequences were modeled to avoid repeated synchronization and thus yields varied sets of reachable states by implementing a decoder in between circuit and LFSR. The on-chip generation of functional tests require simple hardware and achieved high transition fault coverage for testable circuits. Further, power and delay can be reduced by using Bit Swapping LFSR (BS-LFSR). This technique yields less number of transitions for all pattern generation. Bit-swapping (BS) technique is less complex and more reliable to hardware miscommunications.

Enhanced Test Compaction for Multicycle Broadside Tests by Using State Complementation

Multicycle tests support test compaction by allowing each test to detect more target faults. The ability of multicycle broadside tests to provide test compaction depends on the ability of primary input sequences to take the circuit between pairs of states that are useful for detecting target faults. This ability can be enhanced by adding design-for-testability (DFT) logic that allows states to be complemented. This article describes a test compaction procedure that uses such DFT logic to form a compact multicycle broadside test set for transition faults where the tests use constant primary input vectors. The use of complemented states also allows the procedure to increase the transition fault coverage beyond the transition fault coverage of a broadside test set. The procedure has the option of increasing the switching activity of the tests gradually in order to explore the tradeoff between the number of tests, the fault coverage, and the switching activity.

English

In the proposed method we are test the S27 sequential circuit by using Built in Self Test.This paper describes an on-chip test generation method for functional broadside tests. The hardware was base on the application of primary input sequences initial from a well-known reachable state, therefore using the circuit to produce additional reachable states. Random primary enter sequences were changed to avoid repeated synchronization and thus defer varied sets of reachable states. Functional broadside tests are two-pattern scan based tests that avoid over testing by ensuring that a circuit traverses only reachable states in the functional clock cycles of a check. These consist of the input vectors and the equivalent responses. They check for proper operation of a verified design by testing the internal chip nodes. Useful tests cover a very high percentage of modeled faults in logic circuits and their generation is the main topic of this method. Often, functional vectors are understood as verification vectors, these are used to verify whether the hardware actually matches its specification. Though, in the ATE world, any one vectors applied are understood to be functional fault coverage vectors applied during developing test. This paper show the on chip test Generation for a bench mark circuit using simple fixed hardware design with small no of parameters altered in the design for the generation of no of patterns. If the patterns of the input test vector results a fault simulation then circuit test is going to fail.

Generation of Functional Broadside Tests for Logic Blocks With Constrained Primary Input Sequences

This paper describes a test generation procedure that produces functional broadside tests for logic blocks whose primary input sequences are constrained. The constraints are created during functional operation by logic blocks that drive the logic block under consideration. Functional broadside tests avoid overtesting of delay faults by creating functional operation conditions during the clock cycles where delay faults are detected. Test generation procedures for functional broadside tests typically assume that the primary input sequences are unconstrained during functional operation. This paper shows that the constraints, which are imposed by a logic block driving the primary inputs of another block, can be time dependent and difficult to represent compactly. The test generation procedure described in this paper addresses this issue by separating the problem of test generation into the generation of constrained primary input sequences for the block under consideration, and the extraction of functional broadside tests from these sequences.

Multipattern Scan-Based Test Sets With Small Numbers of Primary Input Sequences

When a multipattern scan-based test is applied at-speed to detect delay defects, it is necessary to change the primary input vectors at-speed. However, tester limitations can make this infeasible. The solution where the primary input vectors are held constant during the test reduces the fault coverage. An alternative solution is to store the primary input sequences of a multipattern test set on-chip and apply them at-speed from an on-chip memory. To support such a solution, this paper describes a procedure for computing a multipattern test set that requires a small number of different primary input sequences. Experimental results for single stuck-at faults and for transition faults show that a multipattern test set that detects all the detectable faults requires a number of primary input sequences that is significantly smaller than the number of tests.

Primary Input Vectors to Avoid in Random Test Sequences for Synchronous Sequential Circuits

Random test sequences may be used for manufacturing testing as well as for simulation-based design verification. This paper studies one of the reasons for the fact that random primary input sequences achieve very low fault coverage for synchronous sequential circuits. It is shown that a synchronous sequential circuit may have input cubes, or incompletely specified input vectors, that synchronize a subset of its state variables, i.e., it forces them to certain specified values. When an input cube c that synchronizes the subset of state variables S(c) has a small number of specified inputs, the input vectors covered by it may appear often in a random primary input sequence. As a result, the sequence will force the same values on the state variables in S(c) repeatedly. This may limit the fault coverage that the sequence can obtain. To address this issue, a procedure is described for modifying a random primary input sequence to eliminate the appearance of input vectors that synchronize subsets of state variables. It is demonstrated that this procedure has a significant effect on the fault coverage that can be achieved by random primary input sequences.

Static test compaction for full-scan circuits based on combinational test sets and nonscan input sequences and a lower bound on the number of tests

A new class of static compaction procedures is described that generate test sets with reduced test application times for scan circuits. The proposed class of procedures combines the advantages of two earlier static compaction procedures, one that tends to generate large numbers of tests with a short primary input sequence included in every test and one that tends to generate small numbers of tests with a long, primary input sequence included in one of the tests. A procedure of the proposed class starts from an initial test set that has a large number of tests and long primary input sequences and it selects a subset of the tests and subsequences of their primary input sequences. It thus has the flexibility of finding an appropriate balance between the number of tests and the lengths of the primary input sequences in order to minimize the test application time. Several ways of computing the primary input sequences for the initial test set are considered. The most compact test sets are obtained when a test sequence for the nonscan circuit is available and this sequence is used as part of every test in the initial test set. However, it is shown that high levels of compaction can also be achieved without the overhead of test generation for the nonscan circuit. Specifically, we show that the industry practice of holding a primary input vector constant between scan operations can be accommodated. We estimate the ability of the procedure to achieve optimum test sets by computing a lower bound on the number of tests and demonstrating that the procedure achieves or approaches this lower bound.

On the use of random limited-scan to improve at-speed random pattern testing of scan circuits

A method is proposed for improving the fault coverage that can be achieved by random patterns for circuits with scan. Under the test application scheme considered, primary input sequences are applied at-speed between scan operations. The proposed method uses limited scan operations to improve the fault coverage. Under a limited scan operation, the circuit state is shifted by a number of positions which may be smaller than the number of state variables. Limited scan operations are inserted randomly to ensure that the complete test set can be generated by a random pattern generator. Experimental results show that complete fault coverage is achieved by the proposed method, i.e., the proposed method detects all the detectable circuit faults, for all the benchmark circuits considered.

Test compaction for at-speed testing of scan circuits based on nonscan test. sequences and removal of transfer sequences

Proposes a procedure for generating compact test sets with enhanced at-speed testing capabilities for scan circuits. Compaction refers here to a reduction in the test application time, while at-speed testing refers to the application of primary input sequences that contribute to the detection. of delay defects. The proposed procedure generates an initial test set that has a low test application time and consists of long sequences of primary input vectors applied consecutively. To construct this test set, the proposed procedure transforms a test sequence T/sub o/ for the nonscan circuit into a scan-based test by selecting an appropriate scan-in state and removing primary input vectors from T/sub o/ if they do not contribute to the fault coverage. If T/sub o/ contains long transfer sequences, several scan-based tests with long primary input sequences may be obtained by replacing transfer sequences in T/sub o/ with scan operations. This helps reduce the test application time further. We demonstrate through experimental results the advantages of this approach over earlier ones as a method for generating test sets with minimal test application time and long primary input sequences.