In this paper, the impact of several processing parameters, like the etch depth and elevation of the epitaxial Si0.8Ge0.2 layer on the current-voltage (I-V) characteristics of recessed Source/Drain p+-n junctions is studied. It is shown that the area leakage current density is a strong function of the position of the junction with respect to the SiGe/Si interface. The highest area leakage current density is found for the heterojunctions, which can be explained by the presence of extended defects, generating excess carriers in the depletion region in the silicon substrate. The corresponding perimeter leakage current density is also highest for the highest etch depths. In addition, for some splits an empirical exponential dependence on the total epi layer thickness has been observed.