Prefix Sum Research Articles

A new parallel algorithm for rooting a tree

When an undirected tree,T, and a vertex,r, in the tree are given, the problem to transformT into a rooted tree withr as its root is considered. Using Euler tour and prefix sum, an optimal algorithm has been developed [2, 3]. We will present another parallel algorithm which is optimal also on EREW PRAM. Our approach reduces the given tree step by step by pruning and pointer jumping. That is, the tree structure is retained during algorithm processing such that another tree computations can be carried out in parallel.

Linear array with a reconfigurable pipelined bus system — Concepts and applications

A new computational model, called a linear array with a reconfigurable pipelined bus system (LARPBS), has been proposed as a feasible and efficient parallel computational model based on current optical technologies. In this paper, we further study this model by proposing several basic data movement operations on the model. These operations include broadcast, multicast, compression, split, binary prefix sum, maximum finding. Using these basic operations, several image processing algorithms are also presented for the model. We show that all algorithms can be executed efficiently on the LARPBS model. It is our hope that the LARPBS model can be used as a new and practical parallel computational model for designing parallel algorithms.

Randomized Priority Queues for Fast Parallel Access

We present simple randomized algorithms for parallel priority queues on distributed memory machines. Inserting O(n) elements or deleting the O(n) out ofmsmallest elements usingnprocessors requires O(Tcoll+ log(m/n)) amortized time with high probability whereTcollbounds the time for performing prefix sums and randomized routing. The memory requirement is bounded by (m/n)(1 +o(1)) + O(logn) whp. These bounds are an improvement over the best previously known algorithms for many interconnection networks and even matches the speed of the best known PRAM algorithms. Generalizations for accessing thek⪢nsmallest elements are even more efficient. A portable implementation using MPI demonstrates that our approach is already useful for medium scale parallelism. Two parallel selection algorithms for randomly placed data are a spin-off. One runs in time O(Tcoll) with high probability, beating a lower bound for the worst case. The other requires only a single reduction operation.

Basic operations on the OTIS-Mesh optoelectronic computer

In this paper, we develop algorithms for some basic operations-broadcast, window broadcast, prefix sum, data sum, rank, shift, data accumulation, consecutive sum, adjacent sum, concentrate, distribute, generalize, sorting, random access read and write-on the OTIS-Mesh model. These operations are useful in the development of efficient algorithms for numerous applications.

Range queries in OLAP data cubes

A range query applies an aggregation operation over all selected cells of an OLAP data cube where the selection is specified by providing ranges of values for numeric dimensions. We present fast algorithms for range queries for two types of aggregation operations: SUM and MAX. These two operations cover techniques required for most popular aggregation operations, such as those supported by SQL. For range-sum queries, the essential idea is to precompute some auxiliary information (prefix sums) that is used to answer ad hoc queries at run-time. By maintaining auxiliary information which is of the same size as the data cube, all range queries for a given cube can be answered in constant time, irrespective of the size of the sub-cube circumscribed by a query. Alternatively, one can keep auxiliary information which is 1/ b d of the size of the d -dimensional data cube. Response to a range query may now require access to some cells of the data cube in addition to the access to the auxiliary information, but the overall time complexity is typically reduced significantly. We also discuss how the precomputed information is incrementally updated by batching updates to the data cube. Finally, we present algorithms for choosing the subset of the data cube dimensions for which the auxiliary information is computed and the blocking factor to use for each such subset. Our approach to answering range-max queries is based on precomputed max over balanced hierarchical tree structures. We use a branch-and-bound-like procedure to speed up the finding of max in a region. We also show that with a branch-and-bound procedure, the average-case complexity is much smaller than the worst-case complexity.

Reliable computations on faulty EREW PRAM

We consider the problem of efficient and reliable computing on EREW PRAM whose processors are subject to random independent stop-failures with constant probability p < 1. An algorithm for such a fault-prone machine is called safe if it solves a problem of size n with probability exceeding 1 − d n , for some constant d independent of n. Our main contribution is a safe algorithm for the well-known list ranking problem, working in time O( log n) on an O( n log n)-processor EREW PRAM. We also show an optimal safe algorithm for computing prefix sums, which works in time O( log n) on an O( n log n )- processor EREW PRAM. The methods presented in this paper can be applied to a wide class of EREW PRAM algorithms making them safe and simultaneously preserving their complexity.

Enhanced Fibonacci Cubes

We propose the enhanced Fibonacci cube (EFC) structure for parallel systems. It is defined based on the sequence F n = 2F n-2 + 2F n-4 . We show that the enhanced Fibonacci cube contains the Fibonacci cube (FC) as a subgraph and maintains virtually all the desirable properties of the Fibonacci cube. In addition, it is a Hamiltonian graph. We can embed complete binary trees into enhanced Fibonacci cubes with dilation one and with a relatively small expansion. We also propose a series of enhanced Fibonacci cubes EFC (k) , where k is a series number. Each EFC (k) contains an FC of the same order as a subcube. Moreover, each EFC (k) in the series contains any other cube that precedes it as subcubes and the last one in the series is a hypercube of the corresponding order. This series of EFC (k) s provides us with more options for selecting cubes with various sizes. Because EFC is a subgraph of the hypercube, it may find applications in fault-tolerant computing for degraded hypercube computer systems. As an application of EFC, we show that the parallel prefix sum computation can be efficiently implemented on enhanced Fibonacci cubes.

Optimal computing hough transform on a reconfigurable array of processors with wider bus networks

The parallel computation model on which our algorithms are based is the reconfigurable array of processors with wider bus networks. Conventionally, only one bus is connected between two processors, but in this machine it has a set of buses. Such a characteristic makes the computation power of this machine enormous. Based on the base- m number system, we first derive a constant time algorithm to compute the prefix sum for the bit one of a binary sequence of size N using N processors. Then two applications, such as the histogram of an n × n image and the Hough transform of N edge pixels with n × n parameter space are also solved in constant time using n × n and n × ( N + 1) processors respectively. Both results are shown to be optimal.

Lower Bounds for Dynamic Transitive Closure, Planar Point Location, and Parentheses Matching

We give a number of new lower bounds in the cell probe model&lt;br /&gt;with logarithmic cell size, which entails the same bounds on the random access computer with logarithmic word size and unit cost operations. We study the signed prefix sum problem: given a string of length n of zeroes and signed ones, compute the sum of its ith prefix during updates. We show a&lt;br /&gt;lower bound of Omega(log n/log log n) time per operations, even if the prefix sums are bounded by log n/log log n during all updates. We also show that if the update time is bounded by the product of the worst-case update time and the&lt;br /&gt;answer to the query, then the update time must be Omega(sqrt(log n/ log log n)).&lt;br /&gt; These results allow us to prove lower bounds for a variety of seemingly unrelated&lt;br /&gt;dynamic problems. We give a lower bound for the dynamic planar point location in monotone subdivisions of &lt;br /&gt;Omega(log n/ log log n) per operation. We give&lt;br /&gt;a lower bound for the dynamic transitive closure problem on upward planar graphs with one source and one sink of &lt;br /&gt;Omega(log n/(log logn)^2) per operation. We give a lower bound of Omega(sqrt(log n/log log n)) for the dynamic membership problem of any Dyck language with two or more letters. This implies the same&lt;br /&gt;lower bound for the dynamic word problem for the free group with k generators. We also give lower bounds for the dynamic prefix majority and prefix equality problems.

The parallel complexity of integer prefix summation

The time required by a p-processor CRCW PRAM to add n integers of N bits each or to compute all their prefix sums is shown to be θ ( n p + log n log log p + log min{ N log p, n }) , which unifies many previous results.

Designing efficient parallel algorithms on CRAP

A cross-bridge reconfigurable array of processors is a parallel processing system which has the ability to change dynamically the supported interconnection scheme during the execution of an algorithm. Based on this architecture, several O(1) time basic operations such as the transpose, the untranspose, the shift, the unshift and the prefix sum of a binary sequence are first proposed. Then, these basic operations can be used to find the kth smallest element of N m bits unsigned integers in O(m) time using N processors and to sort N data items in O(1) time using O(N/sup 5/3/) processors instead of using O(N/sup 2/) processors as those proposed by other researchers. >

An O(1) time algorithms for computing histogram and Hough transform on a cross-bridge reconfigurable array of processors

In this paper, instead of using the base-2 number system, we use a base-m number system to represent the numbers used in the proposed algorithms. Such a strategy can be used to design an O(T) time, T=[log/sub m/N]+1, prefix sum algorithm for a binary sequence with N-bit on a cross-bridge reconfigurable array of processors using N processors, where the data bus is m-bit wide. Then, this basic operation can be used to compute the histogram of an n/spl times/n image with G gray-level value in constant time using G/spl times/n/spl times/n processors, and compute the Hough transform of an image with N edge pixels and n/spl times/n parameter space in constant time using n/spl times/n/spl times/N processors, respectively. This result is better than the previously known results. Also, the execution time of the proposed algorithms is tunable by the bus bandwidth.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

DATA MANIPULATION ON THE DISTRIBUTED MEMORY BUS COMPUTER

We consider fundamental data manipulation operations such as broadcasting, prefix sum, data sum, data shift, data accumulation, consecutive sum, adjacent sum, sorting, and random access reads and writes, and show how these may be performed on the distributed memory bus computer (DMBC). In addition, we study two image processing applications: shrinking and expanding, and template matching. The DMBC algorithms are generally simpler than corresponding algorithms of the same time complexity developed for other reconfigurable bus computers.

Mapping a functional notation for parallel programs onto hypercubes

Abstract The theory of powerlists was recently introduced by Jayadev Misra (1994). Powerlists can be used to specify and verify certain parallel algorithms, using a notation similar to functional programming languages. In contrast to sequential languages the powerlist notation has constructs for expressing balanced divisions of lists. We study how Prefix Sum , a fundamental parallel algorithm, can be tailored for efficient execution on hypercubic architectures. Then we derive a strategy for mapping most powerlist functions to efficient programs for hypercubic architectures.

Reconfigurable buses with shift switching: concepts and applications

We propose to enhance traditional broadcast buses by the addition of a new feature that we call shift switching. We show that on a linear array of processors enhanced with shift switching, the prefix sums of n bits can be computed in [log(n+1)/log w] broadcasts, each over n switches, assuming a global bus of width w. Next our prefix sums algorithm is used in conjunction with broadcasting on short buses to obtain several efficient architectural designs for the following fundamental problems: 1) ranking linked lists, 2) counting the number of 1's in a sequence of n bits, and 3) sorting small sets. We see our main contribution in showing that the new bus feature leads to designs that are both theoretically interesting and practically relevant.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

ON PARALLEL PREFIX COMPUTATION

We prove that prefix sums of n integers of at most b bits can be found on a COMMON CRCW PRAM in [Formula: see text] time with a linear time-processor product. The algorithm is optimally fast, for any polynomial number of processors. In particular, if [Formula: see text] the time taken is [Formula: see text]. This is a generalisation of previous result. The previous [Formula: see text] time algorithm was valid only for O(log n)-bit numbers. Application of this algorithm to r-way parallel merge sort algorithm is also considered. We also consider a more realistic PRAM variant, in which the word size, m, may be smaller than b (m≥log n). On this model, prefix sums can be found in [Formula: see text] optimal time.

Virtual Shared Memory: Algorithms and Complexity

We consider the Block PRAM model of Aggarwal et al. ( in "Proceedings, First Annual ACM Symposium on Parallel Algorithms and Architectures, 1989," pp. 11-21). For a Block PRAM model with n /log n processors and communication latency l = O (log n ), we show that prefix sums can be performed in time O ( l log n /log l ), but list ranking requires time Ω( l log n ); these bounds are tight. These results justify an intuitive observation of Gazit et al. ( in "Proceedings, 1987 Princeton Workshop on Algorithm, Architecture and Technology Issues for Models of Concurrent Computation," pp. 139-156) that algorithm designers should, when possible, replace the list ranking procedure with the prefix sums procedure. We demonstrate the value of this technique in choosing between two optimal PRAM algorithms for finding the connected components of dense graphs. We also give theoretical improvements for integer sorting and many other algorithms based on prefix sums, and suggest a relationship between the issue of graph density for the connected components problem and alternative approaches to integer sorting.

DATA MOVEMENT TECHNIQUES ON RECONFIGURABLE MESHES, WITH APPLICATIONS

Data movement operations are central to many efficient algorithms for parallel machines constructed as interconnection networks of processors. The purpose of this work is to present a number of basic data movement techniques for reconfigurable meshes. These include computing the prefix maxima of a sequence of real numbers and computing the prefix sums of a binary sequence. The data movement techniques presented in this paper have far-reaching applications. Among them, we present a new sorting algorithm and an efficient algorithm to find all maximal elements of a planar set of points.

ON THE EFFICIENT SUMMATION OF N NUMBERS ON AN N-PROCESSOR RECONFIGURABLE MESH

A reconfigurable mesh is a two-dimensional processor array equipped with a reconfigurable bus system that can be changed dynamically to suit different computational needs. In this paper we present a parallel algorithm for the summation of N numbers each in the range [0, 2b). The algorithm runs in O(b+ log log N) time on [Formula: see text] reconfigurable mesh. This is an improvement over the best previously known algorithm that solves the same problem in O(b log log N) time. The algorithm is finally extended to compute the prefix sums of the given numbers in the same time.

Fast computer vision algorithms for reconfigurable meshes

A bus system that can change dynamically to suit computational needs is referred to as reconfigurable. The purpose of this work is to show that a number of seemingly unrelated low-level computer vision tasks are in the same class, in the sense that they can be solved using the same technique. We show that a novel technique for computing integer prefix sums on meshes, augmented with a reconfigurable bus system (reconfigurable meshes), affords us fast algorithms to compute low-level descriptors including perimeter, area, histogram, and median row. Specifically, for an N × N digitized image stored one pixel per processor, all our algorithms run in O(loglogN) time, which is a vast improvement over the state of the art.