Predistortion Of Power Amplifiers Research Articles

A low-power high-performance digital predistorter for wideband power amplifiers

In this paper, we present a low-power high-performance digital predistorter (DPD) for the linearization of wideband RF power amplifiers (PAs). It is based on the novel FIR memory polynomial (FIR-MP) predistorter model, which significantly augments the performance of the conventional memory polynomial predistorter with the use of complex baseband digital FIR filter prior to the memory polynomial. The adjacent channel leakage ratio (ACLR) performance comparison between the conventional MP and the proposed FIR-MP is done based on simulations with multi-carrier modulated signals of 20 and 80 MHz bandwidths. The PA models used for the simulations are extracted from the measurements of a commercial $$1\,\hbox {W}$$ GaAs HBT PA. At the ideal system-level simulations, the improvements in ACLR over the conventional MP are 7.2 and 15.6 dB, respectively, for 20 and 80 MHz signals. The choice of selection of various parameters of the predistorter along with the subsequent digital-to-analog converter (DAC) is presented. The impact of fixed-point representation is assessed using ACLR metrics, which shows that a wordlength of 14 bits is sufficient to obtain ACLR beyond $$45\,\hbox {dBc}$$ with a margin of $$10\,\hbox {dB}$$ . The proposed predistorter is synthesized in $$28\,\hbox {nm}$$ fully-depleted silicon-on-insulator (FDSOI) CMOS process. It is shown that with a fraction of the power and die area of that of the MP a huge improvement in ACLR is attained. With an overall power consumption of 8.2 and 88.8 mW, respectively, for 20 and 80 MHz signals, the FIR-MP DPD proves to be a suitable candidate for small-cell base station PA linearization.

Envelope Preformulation Digital Predistortion for Concurrent Dual-Band Power Amplifiers with Improved Performance and Stability

This letter proposes a novel envelope preformulation digital predistortion technique to linearize concurrent dual-band (DB) power amplifiers (PAs), presenting improved stability/performance, and easier implementation compared to conventional methods. The concurrent DB system was implemented on a GaN Doherty PA by employing two 20-MHz orthogonal frequency division multiplexing signals at the center frequency of 2.25 and 2.45 GHz, respectively. Experimental results have shown great effectiveness of the proposed method, especially when the PA is pushed into highly nonlinear regions, which is very promising for multiband applications in the future communication systems.

Direct Error-Searching SPSA-Based Model Extraction for Digital Predistortion of RF Power Amplifiers

This paper presents a low-complexity architecture to extract model coefficients for digital predistortion of radio frequency power amplifiers. The proposed approach directly updates the model coefficients online using a stochastic optimization algorithm that utilizes random perturbation of the model coefficients to determine the coefficient updating direction and converge toward the optimum solution. This technique avoids resource-intensive matrix operations and the requirement for an offline error model in the conventional model extraction techniques and thus drastically reduces the implementation complexity. The complete model extraction solution has been implemented on a field-programmable gate array, and it is shown that the hardware resource usage is remarkably low. Experimental measurements were conducted on a gallium nitride Doherty amplifier excited by Long Term Evolution signals and the results showed that the proposed technique can achieve linearization performance comparable to that obtained by using the conventional and significantly more complex solutions.

Instantaneous Sample Indexed Magnitude-Selective Affine Function-Based Behavioral Model for Digital Predistortion of RF Power Amplifiers

In this paper, we present a new behavioral model for digital predistortion (DPD) of RF power amplifiers in wireless transmitters. Derived from the decomposed vector rotation model, the new model uses magnitude-selective affine functions as nonlinear operators to construct nonlinear behavior of the model, leading to a highly efficient hardware implementation. Moreover, cross-terms are carefully redesigned based on a new formulation of model structure that not only improves the modeling performance but also significantly lowers the complexity of model extraction. Simulation and experimental results have demonstrated its superior performance and efficient hardware implementation, making this model well suitable for future DPD deployment in 5G small cell base stations where digital hardware resource is highly constrained.

A Novel Generalized Parallel Two-Box Structure for Behavior Modeling and Digital Predistortion of RF Power Amplifiers at LTE Applications

This paper presents a generalized parallel two-box structure that is proposed for modeling and digital predistortion of power amplifiers and wireless transmitters exhibiting memory effects. The proposed predistortion scheme consists of two separable boxes; the first is utilized to model the static behavior of the power amplifier, while the second is proposed to consider the memory effect and nonlinear distortion of the power amplifier. The coefficients of the proposed model are identified by applying an indirect learning structure and a least square method. The validation of the proposed model is carried out using the simulation of the power amplifier and the digital predistortion excited by a 64QAM signal in the advanced design system software. According to the simulation results, the criterion of adjacent channel power ratio reduced by about 16 dB. The simulation results reveal an adjacent channel power ratio of almost − 48 dB. Indeed, the proposed model leads to a better performance in terms of spectral regrowth in comparison with the memory polynomial model, and it also reduces the number of coefficients by approximately 22%. This proposed model enables a more accurate modeling of nonlinear distortion and memory effects compared to previous linearization methods.

Obtaining the Preinverse of a Power Amplifier Using Iterative Learning Control

Telecommunication networks make extensive use of power amplifiers to broaden the coverage from transmitter to receiver. Achieving high power efficiency is challenging and comes at a price: the wanted linear performance is degraded due to nonlinear effects. To compensate for these nonlinear disturbances, existing techniques compute the pre-inverse of the power amplifier by estimation of a nonlinear model. However, the extraction of this nonlinear model is involved and requires advanced system identification techniques. We used the plant inversion iterative learning control algorithm to investigate whether the nonlinear modeling step can be simplified. This paper introduces the iterative learning control framework for the pre-inverse estimation and predistortion of power amplifiers. The iterative learning control algorithm is used to obtain a high quality predistorted input for the power amplifier under study without requiring a nonlinear model of the power amplifier. In a second step a nonlinear pre-inverse model of the amplifier is obtained. Both the nonlinear and memory effects of a power amplifier can be compensated by this approach. The convergence of the iterative approach, and the predistortion results are illustrated on a simulation of a Motorola LDMOS transistor based power amplifier and a measurement example using the Chalmers RF WebLab measurement setup.

Digital Predistortion of Wideband Power Amplifier With Single Undersampling ADC

A novel direct-learning digital predistortion (DPD) of power amplifier (PA) is proposed to alleviate the requirement of an analog-to-digital converter (ADC) in the feedback path. Different from existing undersampling methods, the proposed approach requires only a single ADC running at low sampling rate, which saves one-half hardware cost and avoids the I/Q imbalance problem of the conventional zero-IF feedback structure. First, a modified Gauss-Newton iteration using a low-rate single-branch feedback signal is derived, which justifies the use of single undersampling ADC. Second, a low-complexity time and phase synchronization algorithm based on pattern cross correlation is presented, to align the input and output samples. Experimental results on a 10-W class-AB wideband PA and 100-MHz LTE-A test signal show that the proposed approach can effectively linearize the PA and outperforms other undersampling DPD approaches using the conventional zero-IF feedback structure, in terms of adjacent channel leakage ratio.

Digital Predistortion of an RF Power Amplifier Using a Reduced Volterra Series Model With a Memory Polynomial Estimator

A technique for reducing the number of basis waveforms used in a Volterra series model for digital predistortion (DPD) of radio frequency power amplifiers is proposed. An effective delay is defined for each basis waveform. The DPD model is constrained so that the basis waveforms used have unique delays. When several of the original Volterra terms have a common delay, they are either grouped together to form a single basis waveform or pruned to discard all but the dominant term. It is shown that grouping and pruning produce similar ACLR results when the coefficient estimator notch filters the linear signal bandwidth and applies regularization. Unique delay DPD basis sets are compatible with a fractionally sampled memory polynomial estimator. The basis waveforms within the estimator are specified in the frequency domain as a function of memoryless waveforms and delay operators, thereby reducing the number of fast Fourier transforms needed and allowing for fractional tap spacing that matches the effective delays of Volterra basis waveforms used within the DPD basis set. The approximation associated with using a memory polynomial estimator is sufficiently accurate for a closed-loop estimator to converge to a desired steady state.

A Modified Decomposed Vector Rotation-Based Behavioral Model With Efficient Hardware Implementation for Digital Predistortion of RF Power Amplifiers

This paper proposes a novel hardware implementation strategy to achieve low-cost design for digital predistortion of radio frequency power amplifiers (PAs) using a modified decomposed vector rotation-based behavioral model. To make the model hardware friendly, we first modify the model into a subdecomposed format, which significantly reduces the computational complexity in model extraction. We then reassemble the coefficients and propose a simple digital implementation structure for real-time signal processing in the transmit path. A new dual-direction coordinate rotation digital computer design is also proposed to simultaneously calculate both magnitude and ${e}^{j{\theta }_{n}}$ values to facilitate the model implementation. To validate hardware implementation, a wideband signal is employed to evaluate the performance with a Doherty PA. Experimental results show that the proposed approach can achieve comparable performance with much lower system complexity compared with that using the conventional approaches.

1-bit Observation for Direct-Learning-Based Digital Predistortion of RF Power Amplifiers

In this paper, we propose a low-cost data-acquisition approach for model extraction of digital predistortion (DPD) of RF power amplifiers. The proposed approach utilizes only 1-bit-resolution analog-to-digital converters (ADCs) in the observation path to digitize the error signal between the input and output signals. The DPD coefficients are then estimated based on the direct learning architecture using the measured signs of the error signal. The proposed solution is proved feasible in theory, and the experimental results show that the proposed algorithm achieves the performance equivalent to that using the conventional method. Replacing high-resolution ADCs with 1-bit comparators in the feedback path can dramatically reduce the power consumption and cost of the DPD system. The 1-bit solution also makes DPD become practically implementable in future broadband systems since it is relatively straightforward to achieve an ultrahigh sampling speed in data conversion using only simple comparators.

Concurrent dual‐band digital predistortion implemented with reduced look‐up‐tables

A reduced look-up-tables (LUTs) implementation of digital predistortion (DPD) for concurrent dual-band power amplifiers (PAs) is proposed. In the proposed method, the dual-band output is captured jointly with reduced sampling rate, then the PA characteristics of the lower band and the upper band are identified with a group of shared model coefficients, thus DPD can be implemented with shared LUTs for the two bands, which results in reducing the LUTs by 50% comparing with those traditional dual-band DPD techniques implemented with individual LUTs for each band. Experimental results show that the proposed method can achieve better than −48.2 dBc adjacent channel power ration performance with reduced LUTs.

Digital predistortion of power amplifiers using structured compressed‐sensing Volterra series

Digital predistortion has become an attractive technique for power amplifier linearisation whose limiting factor for using Volterra series as the underlying model is its computational complexity, since the number of components rapidly grows with the non-linear order and memory. Based on a previous reference algorithm, which consists on applying the orthogonal matching pursuit for the sorting of the model components and a Bayesian information criterion for the selection of the optimum number of components, a new technique to reduce the size of the support set taking into account the structural information within a model is presented. Experimental results of the predistortion of a commercial power amplifier are given as a proof of its capabilities, showing equivalent performance to the pruning with the reference algorithm while further reducing the number of components.

Preparing Linearity and Efficiency for 5G: Digital Predistortion for Dual-Band Doherty Power Amplifiers with Mixed-Mode Carrier Aggregation

As new wireless communication standards seek to meet the myriad demands of today's end users, the traditional RF transmitter chain is faced with an evolving set of challenges. To maximize information throughput, signal bandwidths are continuously growing. In fourth-generation longterm evolution-advanced (also called LTE-A), for example, to meet the stated goals of 1-Gb/s downlink and 500-Mb/s uplink speeds, the carrier aggregation (CA) technique was introduced, expanding the maximum transmit bandwidth up to 100 MHz [1]. With mobile traffic expected to increase by a factor of 1,000 over the next decade, future fifth-generation (5G) systems will continue to place new demands on the transmit chain [2].

High power amplifier predistorter based on fuzzy wavelet neural networks for WiMAX signals

High power amplifier predistorter based on fuzzy wavelet neural networks for WiMAX signals

Digital Predistortion for Power Amplifier Based on Sparse Bayesian Learning

In this brief, a sparse-Bayesian-learning algorithm is applied to estimate the coefficients of the power amplifier (PA) behavioral models and inverse models from the view of probability. With this sparse learning method, the needed number of samplings can be reduced significantly. In addition, it also provides researchers with ideas that obtain the needed subspace of the preselected model. The performance of the algorithm is validated experimentally on a gallium nitride (GaN) PA, and the signal used to test the proposed approach is an Long Term Evolution (LTE) signal. A comparison with the state-of-the-art estimation algorithm in an open-loop digital-predistortion system is also presented, and the vast majority of tests show that the number of model coefficients is reduced by at least 50%.

Low-Complexity Stochastic Optimization-Based Model Extraction for Digital Predistortion of RF Power Amplifiers

This paper introduces a low-complexity stochastic optimization-based model coefficients extraction solution for digital predistortion of RF power amplifiers (PAs). The proposed approach uses a closed-loop extraction architecture and replaces conventional least squares (LS) training with a modified version of the simultaneous perturbation stochastic approximation (SPSA) algorithm that requires a very low number of numerical operations per iteration, leading to considerable reduction in hardware implementation complexity. Experimental results show that the complete closed-loop stochastic optimization-based coefficient extraction solution achieves excellent linearization accuracy while avoiding the complex matrix operations associated with conventional LS techniques.

An Optimization Platform for Digital Predistortion of Power Amplifiers

The article introduces an integrated hardware/software codesign and test platform for the digital predistortion and power amplifier blocks of radiofrequency transceivers. The platform allows evaluation and optimization of system performance with minimum computational resources, contributing to higher design flexibility. The platform is demonstrated on a variety of power amplifiers.

A Novel Model for Digital Predistortion of Discrete Level Supply-Modulated RF Power Amplifiers

The linearization of a discrete level supply modulated RF power amplifier using digital predistortion (DPD) is investigated. The characteristics of the system are evaluated and a novel DPD model, capable of handling the switching dynamics of the system, is developed and presented. The model is tested for an RF power amplifier operating at 2.65 GHz with a 16 MHz modulated signal. It is shown that modeling the supply voltage transitions with the novel model significantly improves linearity by up to 1.6 dB NMSE and 3.3 dB in ACLR. With the novel model DPD on the supply modulated PA can achieve similar linearity as a single supply PA but with much improved PAE.

Low-cost FPGA implementation of 2D digital pre-distorter for concurrent dual-band power amplifier

This paper proposes a low-cost hardware architecture based on concurrent dual-band digital pre-distorter (DPD). The architecture is implemented on field programmable gate array (FPGA) to compensate for the nonlinearity of the concurrent dual-band power amplifier (PA). This implementation introduces a novel model complexity reduction technique into system, namely, time-division multiplexing for out-of-band lookup tables (LUTs) sharing. Performances are evaluated with an experimental test setup using a wideband class-F PA. The dual-band signal center frequency separated by 80 MHz. Lower and upper center frequency are located at 2.61 GHz and 2.69 GHz, respectively. This novel DPD implementation maintains excellent performance, but uses hardware resources reduced by 29.17% compared with conventional approaches. The results show that the adjacent channel power ratio (ACPR) is less than 59 dBc and normalized mean square error (NMSE) is around 62dB for lower sideband (LSB) and 63dB for upper sideband (USB).

Spectra-Folding Feedback Architecture for Concurrent Dual-Band Power Amplifier Predistortion

This paper proposes a spectra-folding feedback (SFFB) architecture for digital predistortion (DPD) of concurrent dual-band power amplifiers (PAs). Conventional dual-band DPD contains a dual-branch feedback path to receive the PA output signals at respective bands. The proposed architecture, however, is constructed by a single-branch receiving path, so that the hardware expense (such as down converters, filters, or analog-to-digital converters) of the feedback path is significantly reduced. In this architecture, simple modifications are made to the down converter to allow the use of only one analog-to-digital converter. With the proposed signal processing in the baseband, the SFFB DPD can achieve comparative performance as the conventional dual-branch DPD. Experiments were performed using various configurations of LTE/LTE-Advanced (long-term evolution/long-term evolution advanced) signals of up to 80 MHz contiguous bandwidth and carrier spacing of 1 GHz. It is clearly shown by the experimental results that the proposed SFFB DPD can achieve satisfactory linearization performance, with significantly reduced hardware complexity.