Predistortion Of RF Power Amplifiers Research Articles

A Modified Decomposed Vector Rotation-Based Behavioral Model With Efficient Hardware Implementation for Digital Predistortion of RF Power Amplifiers

This paper proposes a novel hardware implementation strategy to achieve low-cost design for digital predistortion of radio frequency power amplifiers (PAs) using a modified decomposed vector rotation-based behavioral model. To make the model hardware friendly, we first modify the model into a subdecomposed format, which significantly reduces the computational complexity in model extraction. We then reassemble the coefficients and propose a simple digital implementation structure for real-time signal processing in the transmit path. A new dual-direction coordinate rotation digital computer design is also proposed to simultaneously calculate both magnitude and ${e}^{j{\theta }_{n}}$ values to facilitate the model implementation. To validate hardware implementation, a wideband signal is employed to evaluate the performance with a Doherty PA. Experimental results show that the proposed approach can achieve comparable performance with much lower system complexity compared with that using the conventional approaches.

Low-Complexity Stochastic Optimization-Based Model Extraction for Digital Predistortion of RF Power Amplifiers

This paper introduces a low-complexity stochastic optimization-based model coefficients extraction solution for digital predistortion of RF power amplifiers (PAs). The proposed approach uses a closed-loop extraction architecture and replaces conventional least squares (LS) training with a modified version of the simultaneous perturbation stochastic approximation (SPSA) algorithm that requires a very low number of numerical operations per iteration, leading to considerable reduction in hardware implementation complexity. Experimental results show that the complete closed-loop stochastic optimization-based coefficient extraction solution achieves excellent linearization accuracy while avoiding the complex matrix operations associated with conventional LS techniques.

Graphic User Interface for Memory Polynomial Based Digital Pre-Distortion of RF Power Amplifiers

The availability of fast and cost effective digital processing technology makes digital pre-distortion attractive for power amplifier linearization since it promises high power efficiency and flexibility. Digital pre-distortion task can be divided into three sub tasks: modeling of the power amplifier (PA), adaptive identification of the model parameters, and development of the pre-distorter. The memory polynomial model, which is reduced form of Volterra series, is most widely used by researchers. The accuracy of memory polynomial based digital pre-distortion depends on the memory depth and order of memory polynomial. In this work a generalized graphic user interface has been developed for modeling of power amplifier and digital pre-distorter. The memory depth and order of memory polynomial can be changed and experimentation can be done for different values of memory depth and order of memory polynomial.

Optimized Low-Complexity Implementation of Least Squares Based Model Extraction for Digital Predistortion of RF Power Amplifiers

Least squares (LS) estimation is widely used in model extraction of digital predistortion for RF power amplifiers. In order to reduce computational complexity and implementation cost, it is desirable to use a small number of training samples in the model parameter estimation. However, due to strong correlations between data samples in a real transmit signal, the ill-conditioning problem becomes severe in standard LS, which often leads to large errors occurring in model extraction. Using a short training sequence can also cause mismatch between the statistical properties of the training data and the actual signal that the amplifier transmits, which could degrade the linearization performance of the digital predistorter. In this paper, we propose first to use a 1-bit ridge regression algorithm to eliminate the ill-conditioning problem in the LS estimation and then use root-mean-squares based coefficients weighting and averaging approach to reduce the errors caused by the statistical mismatch. Experimental results show that the proposed approach can produce excellent model extraction accuracy with only a very small number of training samples, which dramatically reduces the computational complexity and the system implementation cost.

Peak-Power Controlling Technique for Enhancing Digital Pre-Distortion of RF Power Amplifiers

In this paper, we present a method to limit the generation of signal peak power at the output of a digital pre-distorter that is applied to a RF power amplifier (PA) operating in strong compression. The method can be considered as a joint crest-factor reduction and digital pre-distortion (DPD). A challenging characteristic of DPD when applied to a PA in strong compression is the generation of relatively high peaks due to the DPD expansion behavior. Such high peaks generation, which may be physically unrealistic, can easily damage the amplification system. Such a phenomenon, referred in this study as DPD-avalanche, is more noticed when the signal exciting the PA is compressed due to crest-factor reduction. The suggested method for controlling such DPD-avalanche is based on shaping the input signal to the DPD in such a way to keep the pre-distorted signal peak power below or near the maximum allowed peak power of the PA. The suggested method is tested experimentally on a Class-AB and a Doherty PA when excited with a wideband orthogonal frequency-division multiplexing (OFDM) signal. Scenarios for an OFDM signal with and without crest-factor reduction are evaluated. Measurement results when using the proposed DPD-avalanche controller show smooth deterioration of the in-band and out-of-band linearity compared to steep deterioration when no controller is used. In addition, the suggested controller offers a higher operating power range of the DPD while fulfilling out-of-band distortion requirements and preserving low in-band error.

A Parallelizable Adaptive Method to Update Close-Loop Digital Predistorter for RF Power Amplifiers

This paper presents a parallelizable adaptive method to estimate and update close-loop digital predistorter for RF power amplifiers. The proposed scheme can be realized with multiple processors which can save computational time and be used in real-time implementation. By using a three-carrier wideband code-division multiple access (WCDMA) signal, the scheme is tested in the way of 3 branches in Nios II. Results show that the performance is approximate to that based on RLS algorithm and the time the scheme expensed is much less than that RLS needed.

An Accurate Complexity-Reduced “PLUME” Model for Behavioral Modeling and Digital Predistortion of RF Power Amplifiers

This paper introduces a new, accurate, and complexity-reduced three-nonlinear-box model that is suitable for the behavioral modeling and digital predistortion (DPD) of power amplifiers (PAs) exhibiting memory effects. This model is composed of a look-up table (LUT), a memory polynomial (MP), and an envelope MP (EMP), which are all connected in parallel, and it is termed as Parallel-LUT-MP-EMP (PLUME). The PLUME model's performance is experimentally assessed using a highly nonlinear Doherty PA driven by a multicarrier wideband code division multiple access signal. A comparison is held between the PLUME model and different state-of-the-art models reported in the literature, such as the MP model, the parallel twin nonlinear two-box model, and the generalized MP (GMP) model. The experimental results, in both behavioral modeling and DPD applications, demonstrate that the proposed PLUME model outperforms the first two models. However, it shows the same accuracy as the GMP model but with an approximately 45% reduction in the number of coefficients. This significant decrease in coefficients considerably reduces the model computational complexity. Another comparison of the resources utilized for field programmable gate array implementation of the PLUME model and the GMP model is performed, which reveals that the PLUME model uses much fewer resources than the other model.

Low-Cost FPGA Implementation of Volterra Series-Based Digital Predistorter for RF Power Amplifiers

This paper presents a low-complexity and low-cost hardware implementation of a Volterra series-based digital predistorter (DPD). This is achieved by introducing two novel model complexity reduction techniques into the system, namely, lookup table assisted gain indexing and time-division multiplexing for multiplier sharing. Experimental results show that this novel DPD implementation uses much less hardware resources, but still maintains excellent performance compared to conventional approaches.

An Approximation of Volterra Series Using Delay Envelopes, Applied to Digital Predistortion of RF Power Amplifiers With Memory Effects

In this letter, a new model for digital predistortion (DPD) of radio frequency power amplifiers for wide-band applications is proposed. The model is based on a spline approximation of Volterra series by considering second-order cross-terms. The advantage of the spline cross-term model is a reduction in the number of model parameters. We further reduce the model order by operating on delayed envelope samples, rather than the complex baseband samples. A block of wide-band code-division multiple access signal is sent through a 90 W class-AB power amplifier, based on the freescale LDMOS output device, and the input/output baseband samples were used to identify the DPD parameters.