IEEE 1588 Research Articles

Quantum enhanced time synchronisation for communication network

It is essential to establish precise times in future communication networks. Any real-time task’s ability to function depends on the system’s ability to synchronise time. In the current communication network, time synchronisation is critical and must be maintained to transmit data packets. The functionality of 6G, the Tactile Internet, Time-Sensitive Networking, and ultra-reliable low-latency communications is highly susceptible to time synchronisation. We investigated the idea of employing time synchronisation across different communication network nodes. The current state-of-the-art employs network protocols like Precision Time Protocol for clock synchronisation across different nodes. These network protocols are not very robust and can generate jitters in data transmission. In this paper, we suggested synchronising the time of the node clocks at three different places using quantum technology. Notably, the oscillation frequencies of each qubit (or oscillator) located at these nodes can be synchronised using quantum synchronisation technique. This set of three oscillators will work as a single clock and will be the master clock of the network. We propose distributing precise time and frequency standards using quantum synchronisation on node clocks. We can synchronise the three qubits (each placed at one node) to oscillate at an identical frequency by applying an external field of a wavelength of 813.32nm. We analysed our model for different coupling constants and dissipation rates to provide an analysis of the behaviour of the amount of synchronisation in different experimental configurations. The optimal accuracy for our system is 1.6×1015 signals per second. Further, we used the Allan deviation to examine the stability of our system for various noise strengths.

Time sensitive networking security: issues of precision time protocol and its implementation

Time Sensitive Networking (TSN) will be an integral component of industrial networking. Time synchronization in TSN is provided by the IEEE-1588, Precision Time Protocol (PTP) protocol. The standard, dating back to 2008, marginally addresses security aspects, notably not encompassing the frames designed for management purposes (Type Length Values or TLVs). In this work we show that the TLVs can be abused by an attacker to reconfigure, manipulate, or shut down time synchronization. The effects of such an attack can be serious, ranging from interruption of operations to actual unintended behavior of industrial devices, possibly resulting in physical damages or even harm to operators. The paper analyzes the root causes of this vulnerability, and provides concrete examples of attacks leveraging it to de-synchronize the clocks, showing that they can succeed with limited resources, realistically available to a malicious actor.

PESNet 3.0: A WRN-Based Communication Network With ±0.5 ns Synchronization Error for Large-Scale Modular Power Converters

Emerging large-scale silicon-carbide (SiC)-based modular power converters are pursuing high-performance distributed control systems (DCSs). In particular, fast-switching-enabled novel control schemes raise the need for minimal synchronization error (SE) of communication networks. This article presents the development of a proposed power electronics system network (PESNet) 3.0 that features a sub-nanosecond (ns) SE and gigabits-per-second data rate. The White Rabbit Network (WRN) technology, originally developed for particle accelerators, has been embedded in PESNet 3.0 and tailored to be suited for large-scale high-frequency modular power converters. A simplified node-to-node phase-locked loop (N2N-PLL) and an improved precision time protocol (PTP) model has been proposed to lock both the frequency and phase of two independent clocks on two adjacent nodes. Subsequently, the stability analysis of the N2N-PLL is carried out with its closed-loop transfer function verified by digital perturbation injection (DPI). Finally, the experimental validation of PESNet 3.0 is demonstrated at both controller and converter levels. The latter is on a first-of-it-kind 10-kV SiC-MOSFET-based modular converter prototype operating at 12-kV dc-link voltage, 10-kHz switching frequency, and above 100-V/ns slew rate, verifying ±0.5 ns SE at 5 Gb/s data rate.

Distributing and Synchronizing Signals Between the Worlds of SDI and IP

Moving signals between the worlds of serial digital interface (SDI) and Internet Protocol (IP) is not exactly rocket science, but synchronizing these signals may prove to be a challenge. It is these cases that we will discuss in this article and these challenges to which we seek to identify and present a viable and cost-effective solution. We will consider a recent Riedel project with a major U.S. broadcaster. Following the decision to move its operations to ST 2110, this broadcast network experienced synchronization problems between its IP-based flagship station and more than 200 affiliate stations throughout North America relying on SDI. The fact that the remote feed needed to be compressed posed yet another challenge, as it required the decompressed signal to be decoded to ST 2110 before it could be converted to SDI. The Riedel team managed to solve the synchronization issue with a single, powerful device smaller than the size of your thumb: A software-defined processing small form-factor pluggable (SFP) device that enabled the conversion of UHD-1 and ST 2110 signals for bidirectional distribution between the headquarters and the affiliate stations while generating a Precision Time Protocol (PTP) Grand Master clock from the affiliate’s synchronized signal. This greatly reduced both system complexity and the cost of replacing the entire affiliate synchronization system. After a general description of the specific use-case setup, we will present an overview of the various possible solutions and weigh the pros and cons before focusing on the most viable solution. After short explanations of the demarcation switch configuration and the Epoch reference generation at the affiliate sites, we conclude with an outlook on other potential use cases.

시각 동기된 다중 양방향 TMDS 데이터 전송기능을 갖는 IED용 TSMB 버스 시스템의 구현 및 성능분석

In this paper, we propose a novel TSMB bus system with multiple bidirectional data transmission and time synchronization capability for IEDs(Intelligent Electronic Devices). Unlike the legacy unidirectional TMDS(Transition Minimized Differential Signaling) used for transfer digital video signals, the proposed bus system employs dual high-speed serial TMDS link for sending trigger signals from the FPGA of main processor module and receiving the sampled data from submodules such as either current or potential transformers. For simultaneous triggering multiple submdoules, we also employ the precision timing protocol processing capability in the main processor, which generates the wall clock pulse per second(PPS) synchronized to GPS. Adopting PLL for the PPS signal, we can provide the reference clock of 98.304MHz for supporting the data rate of 491.52 Mbps over each TMDS link. The data rate can support eight 24 bits ADCs for PTs or CTs in the single link, each of which requires 4800 samplings per second. An implemented TSMB bus system with FPGA consists of a single main processor with clock expander and eight submodules, in which each submodule is connected with the bidirectional TMDS link to the FPGA of main processor module. The jitter of 1 PPS between the two main processor modules was measured to be less than 102nsec at the maximum, and the jitter of the TSMB transmission data line was measured to be less than or equal to 660ps at the TP3 point of the receiving side, confirming that the TMDS specification was satisfied. Finally, the proposed time- synchronized multi-directional bus system can contribute to the improvement of the reliability and performance of the algorithm of the intelligent protection relay system through the optimal transmission of equivalent and simultaneous sampling data without the involvement of the processor.

Supporting Live Production Using Precision Time Protocol Over 5G Systems With Dedicated Time Synchronization Support

The article explores the possibility of using IEEE 1588 Precision Time Protocol (PTP) over a 5G system for media production applications. The article describes lab sessions performed by the 5G RECORDS consortium members, testing the performance of PTP over 5G with and without the dedicated time synchronization support. A trial with a real camera supporting SMPTE ST 2110–22 with JPEG- XS was conducted to experiment with synchronization and packet pacing precision. The 5G system used in these experiments features additional functionalities from the 3rd Generation Partnership Program (3GPP) Release 16, including specific time synchronization support for time-sensitive networks (TSNs), that is, acting as a time-aware system, and Release 17 in which the support for IEEE 1588 is extended with several additional features. The article also describes the testing setup based on the open-source software used by the team and the methodology developed. The article concludes on the performance and synchronization quality when using PTP over various 5G systems and analyzes the results from the lab trials. This new approach with the experimental setup allows using PTP according to the SMPTE ST 2059–2 PTP profile reliably over 5G for media device synchronization, which is not usually done in the context of the 5G networks.

A Novel Switching Algorithm to the Preferred Clock Skew Estimator Applicable for the PTP Case in the Fractional Gaussian Noise Environment

Recently, the same authors provided a switching algorithm for the preferred clock skew estimator appropriate for the precision time protocol (PTP) scenario. The algorithm chooses the one‐way delay (OWD) clock skew estimator for the Forward path or the Reverse path or the two‐way delay (TWD) clock skew estimator that has the best performance in the mean square error (MSE) perspective. However, the switching algorithm applies only to the Gaussian scenario. In a real system, the packet delay variation (PDV) can be characterized as an fractional Gaussian noise (fGn) process where the Hurst exponent parameter can also have values higher than 0.5. Thus, the Gaussian case‐switching algorithm may not apply in a real system where after a small set of PTP measurements, the switching algorithm should be able to switch effectively to the preferred clock skew estimator with the best performance in the MSE perspective. In this paper, the PDV is characterized as an fGn process where the Hurst exponent (H) is in the range of 0.5 ≤ H < 1. We estimate the unknown PDV variances and the Hurst exponent parameters of the Forward and Reverse paths. These estimated parameters are used for switching to the preferred clock skew estimator from the MSE perspective, even in the presence of asymmetry in the PDV or in the Hurst exponent parameters. We also detect and alarm for the unexpected load, cyber‐attack, or clock skew deviation that can occur in a real system.

Tighter NIC/GPU Integration Yields Next-Level Media Processing Performance

As the media industry further consolidates building services based on commercial-off-the-shelf (COTS) hardware, the requirement for increasing performance continues to accelerate. The processing of video resolutions up to ultra-high definition (HD) (UHD) and 8K, higher frame rates, increased bit depth, and high-dynamic-range (HDR) imagery requires tighter integration and optimization between the network interface controller (NIC) and the graphical processing unit (GPU). Combined with simultaneous input and output of multiple streams; this creates the potential for performance bottlenecks that must be unlocked. This article describes how COTS hardware platforms running Graphics Processing Unit (GPU)s alongside ST 2059–2 Precision Time Protocol (PTP) locked Network Interface Cards (NIC)s, which are accurately pacing packets according to ST 2110–21 requirements, may further increase their performance throughput by reducing central processing unit (CPU)-driven data copy overhead and, in doing so, they reduce processing latency and jitter as well as more effectively use GPU resources while freeing up CPU resources.

Ultra Wideband-based wireless synchronization of IEEE 1588 clocks

Time-Sensitive Networking (TSN) requires clock synchronization superior to the well-known Network Time Protocol (NTP). The IEEE 802.1AS-2020 used for synchronization in TSN networks is based on the IEEE 1588-2019 standard (also known as Precision Time Protocol, PTP) defines methods and tools to perform sub-microsecond time synchronization over vari- ous communication channels. However, the IEEE 1588 implementation is commonly used with wired communication protocols, although there are use cases that could gain an advantage from a wireless solution. This paper investigates the possibility of PTP clock synchronization through wireless Ultra Wideband (UWB) communication. UWB excels where other wireless technologies are lacking: it provides high accuracy timestamping even if multipath propagation is present. The method is evaluated using commercial, well-accessible cheap hardware, resulting in the order of 10-nanosecond accuracy. The paper also highlights the main error components and requirements for improving wireless PTP synchronization.

An ST 2110 Network-Attached Display Adapter for Virtualizing Production

Graphics processing unit (GPU) installations in post-production and broadcast facilities require video to be sent remotely conforming to the SMPTE ST 2110 standards for plug-and-play device connectivity. Furthermore, in such facilities, workstations are now being virtualized and hosted in the data center with what would have previously been a physically attached serial digital video (SDI) reference display replaced by an Internet Protocol (IP) network connection. We present a SMPTE ST 2110 virtual network-attached reference display adapter using commercial off-the-shelf (COTS) hardware that presents the GPU and network interface card (NIC) as a display on the computer workstation desktop. Color-accurate rendered video frames are transmitted directly from GPU device memory. Alignment of the GPU display of the rendered frame and the synchronization of the audio, video, and ancillary data streams are maintained by precision time protocol (PTP). Advanced Media Workflow Association Networked Media Open Specifications (AMWA NMOS) integration permits the discovery and registration of the virtual network-attached reference display adapter as a source node on the media network such that it can be remotely managed and controlled by software greatly simplifying the administration compared with a physically connected display and associated cables. Content creation applications send ST 2110-compliant video, audio, and ancillary data flows on the media network from a virtualized computer workstation desktop without the cost of directly integrating ST 2110 transmission capabilities.

Design considerations for hardware implementation of nanoseconds time synchronization low-cost system based on precise time protocol

Precise time synchronization is the key for coordinating every node of the distributed system to complete tasks. The widespread use of Field Programmable Gate Array (FPGA) in distributed nodes has a positive effect on improving time synchronization accuracy. Although the use of FPGA could significantly improve time synchronization accuracy, there is not a universal design guideline. This work has analyzed and summarized three factors that should be considered when building a low-cost clock synchronization system using FPGA: where the timestamp should be generated, the calculation and correction of time offset, and how to handle Precise Time Protocol (PTP) messages. Based on these design considerations, the time synchronization system intellectual property (IP) core was constructed. The synchronization accuracy experiments have been performed on Zynq system-on-chip (SoC) evaluation boards of different architectures. The experimental results demonstrated that the time synchronization system constructed in this article could achieve nanoseconds accuracy.

Synchronization in Time-Sensitive Networking: An Introduction to IEEE Std 802.1AS

Synchronization has become key in many applications. It is a key aspect of Industrial Automation networks, as those applications depend on synchronized time. It is also important for automotive applications, as synchronization is used for infotainment and handling sensor data. In Telecommunications networks, synchronization has been used for many years, and it is very important to fulfill 5G technology requirements. The Time-Sensitive Networking (TSN) Task Group (TG) of IEEE 802.1 has developed several base standards to allow a deterministic network with bounded latency. IEEE Std 802.1 AS, “Timing and Synchronization for Time-Sensitive Applications,” is part of these base standards developed by the TSN TG. This article gives an introduction of IEEE Std 802.1 AS, and addresses synchronization concepts and its applications. IEEE Std 1588 defines a precision time protocol (PTP), and IEEE Std 802.1AS includes a profile of IEEE Std 1588; therefore, some concepts of IEEE 1588 are also described in this article.

Integrity Verification of Distributed Nodes in Critical Infrastructures.

The accuracy and reliability of time synchronization and distribution are essential requirements for many critical infrastructures, including telecommunication networks, where 5G technologies place increasingly stringent conditions in terms of maintaining highly accurate time. A lack of synchronization between the clocks causes a malfunction of the 5G network, preventing it from providing a high quality of service; this makes the time distribution network a very viable target for attacks. Various solutions have been analyzed to mitigate attacks on the Global Navigation Satellite System (GNSS) radio-frequency spectrum and the Precision Time Protocol (PTP) used for time distribution over the network. This paper highlights the significance of monitoring the integrity of the software and configurations of the infrastructural nodes of a time distribution network. Moreover, this work proposes an attestation scheme, based on the Trusted Computing principles, capable of detecting both software violations on the nodes and hardware attacks aimed at tampering with the configuration of the GNSS receivers. The proposed solution has been implemented and validated on a testbed representing a typical synchronization distribution network. The results, simulating various types of adversaries, emphasize the effectiveness of the proposed approach in a wide range of typical attacks and the certain limitations that need to be addressed to enhance the security of the current GNSS receivers.

Hardware Efficient Clock Synchronization Across Wi-Fi and Ethernet-Based Network Using PTP

Precision time protocol (PTP), a state-of-the-art clock synchronization protocol primarily designed for wired networks, has recently gained attention in the wireless community, due to the increased use of the IEEE 802.11 wireless local area networks (WLAN) in real-time distributed systems. However, all the existing WLAN-based PTP designs either incorporate software timestamping (TS) delivering poor clock synchronization accuracy, or hardware (HW) TS providing better synchronization accuracy at the cost of a significant amount of HW overhead. Moreover, the performance of the existing PTP solutions is mostly evaluated in single-hop wireless networks, while the performance across wired and wireless networks is taken for granted. In this article, a new software-defined-radio-based approach to implement PTP is introduced and validated for the IEEE 802.11 WLAN. Instead of using a dedicated HW clock, the solution utilizes the timing synchronization function clock, an existing clock in the IEEE802.11 standard for synchronization between access point and WLAN stations. The performance of the proposed solution is first investigated within a single-hop WLAN and then across wired–wireless networks. Experimental results unveil that 90% of the absolute clock synchronization error falls within 1.4 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\mu \mathrm{s}$</tex-math></inline-formula> .

A Synchronous Distributed Communication and Control System for SiC-Based Modular Impedance Measurement Units

Single-phase modular impedance measurement unit (IMU) is a promising solution to power system stability analysis. Yet, existing designs only have modularity at the power-stage level other than the control-platform level, which restricts the scalability of modular IMUs. As such, this article proposes a distributed communication and control system (DCCS) for high-frequency large-scale modular IMUs with tight synchronization and low latency to enhance the controller-level modularity and scalability. The new architecture is realized on a widely adopted DSP+FPGA control platform that can be adapted from most existing centralized control systems (CCSs) of modular converters. In this article, the influence of synchronization accuracy (SA) on converter harmonics under carrier-based PWM is first investigated, followed by the study of communication latency’s impact on the system control frequency. Subsequently, the synchronization method of a combined oversampling clock and data recovery (CDR) plus precision time protocol (PTP) method is presented. Furthermore, a communication protocol to maximize control frequencies and a system-level control strategy are elaborated. Finally, controller- and converter-level experimental results are demonstrated on a 520-V, 20-A, SiC-MOSFET-based IMU prototype at 120-kHz equivalent switching frequency, achieving a well-performed ±12.5-ns SA and 60-kHz control frequency.

NTS4PTP — A comprehensive key management solution for PTP networks

In many areas, such as electrical power distribution, industry or the financial sector, time synchronization of devices in their local network is important. The high requirements for synchronization accuracy are often met by the widely used Precision Time Protocol (PTP), which up to now communicates in an unsecured manner. Attacks on the time protocol can lead to high economic damages, for which reason security is becoming more and more important. The current PTP standard IEEE Std 1588-2019 therefore defines initial security mechanisms to potentially enable checking of the authenticity and integrity of PTP messages. However, distribution and application of these security parameters are not part of the specification, and thus no viable protection exists in PTP so far. In this article, we describe our emerging NTS4PTP protocol, which is under development in cooperation with the IEEE Security Subcommittee to address this problem. It is a practical solution for an automated distribution of these security parameters using a key management system that follows the principle of the immediate security processing in PTP. NTS4PTP bases on the recently released Network Time Security (NTS) protocol and provides basic features for PTP such as group management and parameters updating. In addition, our protocol supports all common PTP modes (e.g., multicast, unicast, 802.3) and can be used in combination with the NTS-secured Network Time Protocol (NTP). Here, we step into the most important details of our protocol, describe the advantages and disadvantages and discuss the security requirements and challenges. The work on NTS4PTP is also available with the Internet Engineering Task Force (IETF) as an Internet draft and a proof-of-concept implementation is already under development.

A Security Enhancement of the Precision Time Protocol Using a Trusted Supervisor Node.

The Precision Time Protocol (PTP) as described in IEEE 1588–2019 provides a sophisticated mechanism to achieve microsecond or even sub-microsecond synchronization of computer clocks in a well-designed and managed network, therefore meeting the needs of even the most time-sensitive industrial and financial applications. However, PTP is prone to many security threats that impact on a correct clock synchronization, leading to potentially devastating consequences. Here, the most vicious attacks are internal attacks, where a threat actor has full access to the infrastructure including any cryptographic keys used. This paper builds on existing research on the impact of internal attack strategies on PTP networks. It shows limitations of existing security approaches to tackle internal attacks and proposes a new security approach using a trusted supervisor node (TSN), in line with prong D as specified in IEEE 1588–2019. A TSN collects and analyzes delay and offset outputs of monitored slaves, as well as timestamps embedded in PTP synchronization messages, allowing it to detect abnormal patterns that point to an attack. The paper distinguishes between two types of TSN with different capabilities and proposes two different detection algorithms. Experiments show the ability of the proposed method to detect all internal PTP attacks, while outlining its limitations.

Stability and Accuracy Analysis of a Distributed Digital Real-Time Cosimulation Infrastructure

Cosimulation techniques are gaining popularity amongst the power system research community to analyze future scalable smart grid solutions. However, complications such as multiple communication protocols, uncertainty in latencies are holding up the widespread usage of these techniques for the power system analysis. These issues are even further exacerbated when applied to digital real-time simulators (DRTSs) with strict real-time constraints for power hardware-in-the-loop (PHIL) tests. In this article, we present an innovative digital real-time cosimulation infrastructure that allows interconnecting different DRTS through the Aurora 8B/10B protocol to reduce the effects of communication latency and respect real-time constraints. The proposed solution synchronizes the DRTS interconnection by means of the IEEE 1588 precision time protocol (PTP) standard to align executions and results obtained by the cosimulated scenario. The ideal transformer method interface algorithm, commonly used in PHIL applications, is used to interface the DRTS. Finally, we present time-domain and frequency-domain accuracy analyzes on the obtained experimental results to demonstrate the potential of the proposed infrastructure. With the presented setup, a time step duration down to 50 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\mu$</tex-math></inline-formula> s is shown to be stable and accurate in running an electromagnetic transients cosimulated power grid scenario by interconnecting two commercial DRTS (i.e., RTDS NovaCor), extending the scalability of future smart grid real-time simulations.

Two Novel One-Way Delay Clock Skew Estimators and Their Performances for the Fractional Gaussian Noise/Generalized Fractional Gaussian Noise Environment Applicable for the IEEE 1588v2 (PTP) Case

Papers in the literature dealing with the Ethernet network characterize packet delay variation (PDV) as a long-range dependence (LRD) process. The fractional Gaussian noise (fGn) or the generalized fractional Gaussian noise (gfGn) belong to the LRD process. The IEEE1588v2 is a two-way delay (TWD) protocol that uses the messages from the Forward (Master to Slave) and the Reverse (Slave to Master) paths. Suppose we have a significant difference between the PDV variances of the Forward and the Reverse paths. Thus, if we can use only the path with the lowest PDV variance (namely, only the one-way delay (OWD) technique), we might get a better clock skew performance from the mean square error (MSE) point of view compared with the traditional TWD method. This paper proposes two OWD clock skew estimators, one for the Forward path and one for the Reverse path applicable for the white-Gaussian, fGn and gfGn environment. Those OWD estimators do not depend on the unknown asymmetry between the fixed delays in the Forward and Reverse paths and nor on the clock offset between the Master and Slave. We also supply two closed-form approximated expressions for the MSE related to our new proposed OWD clock skew estimators. In addition, we supply some conditions, summarized in a table, guiding us whether we should use the OWD clock skew estimator for the Forward path or for the Reverse path, or just use the TWD algorithm. Simulation results confirm that our new proposed OWD clock skew estimators achieve better clock skew performances from the MSE point of view, compared with the TWD clock skew estimator recently proposed by the same authors and compared with two literature known OWD methods (the maximum likelihood and Kalman clock skew estimators).

Wireless fieldbus networking with precision time synchronization for a low-power WSAN

A wireless sensor actuator network (WSAN) is an essential part of the industrial Internet of things (IIoT) with a cyber-physical system (CPS). However, the lack of time synchronization support for WSANs to date means that losses in synchronization accuracy have not been overcome. In this manuscript, we design a real-time kernel to resolve the precision time synchronization (PTS) problem and achieve dynamic automatic synthesis and rapid deployment in a complex WSAN system. Furthermore, tight coupling between wireless control and time synchronization motivates a Modbus-based precision time protocol (PTP) codesign that integrates industrial fieldbus networks and a PTS design. The experimental results indicate that our proposed PTP performance can far exceed the time synchronization requirement of an industrial real-time system. Finally, the proposed solution is successfully applied to an IoT-based smart lighting system.