Pre-layout Simulation Research Articles

A 46% PAE, 2.4-GHz Two-Stage Class E Power Amplifier Utilizing CMOS 0.13-µm Technology

A wireless device with a long battery life and great sensitivity becomes difficult to develop since there is a huge demand for low-power, low-cost wireless gadgets. The power amplifier (PA) is the most crucial part of radio frequency (RF) transceivers because of its massive power consumption. Consequently, in order to minimize power loss, a very effective and low-power consumption PA is needed. In this paper, high efficiency two-stage CMOS PA designed in 0.13-μm process for 2.4 GHz IoT transmitter applications is presented. The driver stage and power stage are the two stages that make up the two-stage topology of the proposed CMOS PA. To attain high efficiency and great power gain, a class E PA is used at the power stage. The LC matching network at the output is used for harmonic rejection filter at 2.4 GHz with an additional parallel capacitor helps for better harmonic rejection. In addition, a layout has been successfully designed and optimized. All the components in the proposed PA are designed on-chip. The pre-layout and post-layout simulations have been conducted to verify the proposed PA's performance. The pre-layout simulation of the proposed PA can deliver 19.19 dBm output power and 45.2% PAE at 2.0 V power supply into a 50-Ω load. On the other hand, the proposed PA produced an output power of 17.33 dBm and 46% PAE, according to the results of the post-layout simulation with a similar power supply of 2.0 V. The chip area for the proposed layout design is 1.05 mm2.

Low power CMOS Gm-C based low pass filter for front end neural signal processing

The sub 100 µV voltage levels and sub 100 Hz frequency range makes the processing of most popular signal electroencephalograph (EEG) for brain functionality analysis, a complex task. The low frequency content of EEG (useful signals below 70 Hz) is commonly used for diagnosis of various brain related disorders making low-pass filter (LPF) a key block in front-end processing as noise reduction and resolution enhancement is crucial for precise recovery of these information. This paper is aimed to design reduced transconductance (Gm) based low power and small area CMOS LPF with cutoff frequency (fc) around 70 Hz. The proposed design is simulated using Cadence virtuoso tool and gives cut-off frequency of 72.958 Hz with low output noise of 3.0609 µV/√Hz and power consumption of 264.060 nW at operating voltage of 0.4 V. The simulation results show linearity of performance over -40 to 100 °C. Layout of circuit takes up area of 86.74×81.21 µm and post layout simulation shows 5% variation in power consumption as compared to pre layout simulations.

Programmable PVT compensated dual output resistance tunable current controlled conveyor

ABSTRACT In the existing dual output resistance tunable current controlled conveyor (DO-RTCCCII), a resistance trimming block is added at the X terminal () which is controlled by programmable bits. includes the variations due to bias current (i.e. intrinsic resistance, RX) and due to setting of digital bits. However, the PVT variations may cause deviations in bias current, thus leading to inaccuracies in the design parameters. To address this, a programmable PVT compensated DO-RTCCCII (PPC-DO-RTCCCII) is proposed. It uses a reference generation section along with DO-RTCCCII. The reference generation section uses bias compensation bits for PVT independent bias current generation and also provides flexibility to get desired bias current through current multiplication bits. The operation of the proposed PPC-DO-RTCCCII has been designed and simulated using 28 nm CMOS technology through the simulator ELDO (AMS) tool of Mentor graphics. The post layout simulations closely match with pre layout simulations. A filter circuit is also included to illustrate the usefulness of the proposal.

Quad path, CG-CS resistive feedback LNA architecture for 25–35 GHz band

In this paper, a Quad Path Noise Cancellation (QPNC) Low Noise Amplifier (LNA)presented for 5G sub-band 25-35GHz using GPDK 45 nm Complementary Metal Oxide Semiconductor (CMOS) technology; which is composed of Common Source (CS) & Common Gate (CG) stages with resistive feedback and current reuse at the output. QPNC is used to cancel the noise of common gate transistors, which leads to reduce the noise fig. (NF). Resistive feedback is used to tradeoff between the input matching, gain, and NF i.e. overall refining the Figure of Merit (FoM) of the circuit. Mathematical analysis of impedance matching, gain, noise transfer function, and NF have been done using the small signal model of QPNC-LNA. Simulation has been done on Cadence Virtuoso software using GPDK 45 nm CMOS technology. Pre layout simulation result shows the minimum value of gain is 13.38 dB at 30.9GHz while the maximum value is 14.12 dB at 25.87GHz and flat over the entire frequency range. S11 i.e. input reflection coefficient is ranging from −16.16 dB at 25.21GHz to −11.52 dB at 35GHz for 50 Ω input impedance matching. NF value ranges from 2.69 dB at 25.69GHz to 3.77 dB at 35GHz. The IIP3 value for the proposed QPNC-LNA is 5.3 dB. For the four corners SS, SF, FS, and FF, process corner simulation has been performed. Post-layout simulation results depict the maximum value of gain is 12.71 dB at 25.75GHz. NF value is varying from 2.88 dB to 4.02 dB while the input reflection coefficient is ranging from −10.12 dB to −14.13 dB for 10GHz bandwidth. The circuit consumes 17.53 mW power at 1.2 V under a DC current of 14.61 mA, FoM1 is 8.36 dB and FoM2 of the proposed LNA is 49.35 dB. The layout of the proposed LNA is having an area of 0.03026mm2.

A new low voltage low power fully differential CMOS class AB current output stage with unique current drive capability

ABSTRACT This paper presents a novel low-voltage low power fully differential class AB current output stage with high linearity and unique current drive capability. The proposed circuit is based on a simple and efficient structure to obtain high linearity by minimising the channel length modulation effect and also avoids cascade structure to act best in low-voltage applications. Giving the complete analyses and equations of the circuit, its properties are verified by Cadence using TSMC 0.18 µm CMOS parameters. In order to study its performance at the presence of non-idealities, Pre-layout and Post-layout both plus Monte–Carlo simulations are also performed. Under±0.9 V supply and 35 µA output bias current, it can deliver the ever high output current of ±350 mA with THD of −49 dB and output impedance of 2.8 MΩ, which leads to a unique high current drive ratio (Ioutmax/Ibias) of 10,000 and low consumed power of 150 µw in pre-layout simulation. In post-layout plus Monte–Carlo simulation, the results will be as ±320 mA output current, −42 dB THD, 2.2 MΩ output impedance, 40 µA DC current of the output branch, 8000 current drive ratio and 160 µw consumed power. These remarkable results prove the proposed novel COS not only as the unique one in the world but Longley ahead of the yet second rank COS by some unbeatable ratios as 11300×,14×,4× and3× in F T , I outmax , (Ioutmax/power), and current drive, respectively, that promise to keep it as the lead one for many years in low-voltage/power ultra-high current applications.

Time-domain Continuous-time Delta-sigma Modulator using VCO-based Integrator and GRO-based Quantizer

This paper presents a 3SUPrd/SUP-order time-domain continuous-time delta-sigma modulator (CTDSM) using two voltage-controlled oscillator (VCO)-based integrators and a gated ring oscillator (GRO)-based quantizer. The GRO-based quantizer has 1SUPst/SUP-order noise-shaping characteristics without the increase of the signal transfer function (STF) order and has magnificent linearity. Also, the output of the GRO-based quantizer has an intrinsic data weighted averaging (DWA)-based dynamic element matching (DEM) pattern that is less susceptible to the DAC mismatch. The PWM signal, which is the input of the GRO-based quantizer, is generated by the VCO-based integrator without additional blocks. In the pre-layout simulation, the CTDSM consumes 3.84 mW and achieves an SNDR of 71.2 dB at a 400-MSs sampling frequency and a 10-MHz bandwidth.

Comprehensive Analytical Comparison of Ring Oscillators in FDSOI Technology: Current Starving Versus Back-Bias Control

Back-bias control is a new degree of freedom brought by fully-depleted silicon-on-insulator (FDSOI) CMOS technologies, which can be used to control the oscillation frequency of voltage-controlled ring oscillators (VCROs). The resulting VCRO architecture is called a back-bias-controlled oscillator (BBCO). This paper compares it with the conventional current-starved ring oscillator (CSRO) topology in terms of power consumption and phase noise figure-of-merit (FoM), while taking practical design constraints of process-voltage-temperature (PVT) robustness and frequency tuning range into account. The proposed comprehensive analysis takes advantage of relevant and compact analytical models, as well as extensive pre-layout simulation results. The comparison is made at four different target oscillation frequencies, which are representative of frequency synthesis for WiFi/Bluetooth/LPWAN wireless communications and of clock generation for smartphone/Internet-of-Things processors: 300 MHz, 868 MHz, 2.45 GHz, and 5.18 GHz. In 28-nm FDSOI technology, the results demonstrate that BBCOs can intrinsically reach 1.69 to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4.63\times $ </tex-math></inline-formula> lower minimum power consumption and slightly better FoM values than CSROs.

Fully differential fifth-order dual-notch low-pass filter for portable EEG system

This paper presents a new fully differential fifth-order dual-notch low-pass filter based on multiple-input multiple-output operational transconductance amplifiers (MIMO OTA). This work shows that MIMO OTA-based fifth-order dual-notch filter can reduce the number of used OTAs, resulting in simplified realization and low-power consumption. The multiple-input OTA is obtained by using the multiple-input dynamic threshold MOS (DTMOS) technique without additional differential pairs. A simple common-mode feedback technique has been used; thus, fully differential OTA can be easily obtained. The proposed dual-notch low-pass filter can be applied to electroencephalogram (EEG) detection system to reject the 50 Hz powerline interference and the third harmonic 150 Hz. The proposed filter has been simulated using Cadence environment with 0.18 µm TSMC CMOS process. The power supply of 0.5 V is used and the total power consumption of the MIMO OTA is 17.5 nW. The proposed filter provides 49.7 dB dynamic range for 1% total harmonic distortion (THD) for a sine input signal of 250 mVpp at 10 Hz. At 50 Hz and 150 Hz the notch depths of attenuation are respectively −37.2 dB and −47.4 dB. The pre-layout simulation results are in good agreement with the theory.

A Sub-1 V Bulk-Driven Rail to Rail Dynamic Voltage Comparator with Enhanced Transconductance

Reduced voltage head room availability for input signal swing is one of the major bottlenecks in the design of circuits operating with low supply voltages which attracts investigations leading to improvement in the input signal dynamic range of such circuits. Employing bulk-driven MOSFETs (BDMOS) at the input section of the circuit is a popular technique used for increasing the input dynamic range, but the smaller bulk transconductance of the bulk-driven MOSFET degrades the performance of the circuit in comparison with that of a conventional gate-driven counterpart. A double tail voltage comparator employing BDMOS technique offering rail-to-rail input dynamic range and capable of operating at sub-1[Formula: see text]V power supply is presented in this paper. A transconductance improvement scheme is employed for the first time in the literature for a voltage comparator to overcome the major drawbacks associated with the reduced bulk transconductance of BDMOS input transistors and double tail topology permits low voltage operation. The performance parameters of the proposed voltage comparator are comparable to that of conventional gate-driven comparators, with an additional advantage of rail-to-rail input dynamic range. Pre-layout and post-layout simulations were performed in Cadence Virtuoso suite with gpdk 90[Formula: see text]nm library at power supply as low as 0.6[Formula: see text]V. The worst case delay of the proposed circuit is 0.71[Formula: see text]ns and the worst case power consumption of the circuit is 15[Formula: see text]uW. The circuit consumes a silicon area of 33[Formula: see text]μm[Formula: see text]46[Formula: see text]μm. An analytical model of the transconductance enhancement technique and delay of the proposed comparator are also presented.

A 4–6 GHz Single-Ended to Differential-Ended Low-Noise Amplifier for IEEE 802.11ax Wireless Applications with Inherent Complementary Distortion Cancellation

With the emergence of the internet-of-things (IoT), many devices process data through the IEEE 802.11 wireless networks. To satisfy the increased data processing, the wireless fidelity (Wi-Fi) networks must have sufficient capacity. IEEE 802.11ax is formulated to provide higher data processing capabilities for IoT applications. The IEEE 802.11ax receiver operating at 5[Formula: see text]GHz must be able to withstand interference from nearby IoT applications. Hence, the low-noise amplifier (LNA) employed in such receivers must have a high input-referred third-order intercept point (IIP3). This paper aims to present a wideband LNA operating at 5[Formula: see text]GHz with high IIP3 for modern IoT transceivers using IEEE 802.11ax protocol. The LNA is designed and implemented in UMC 65[Formula: see text]nm CMOS technology using the Cadence virtuoso design tool. The proposed LNA can provide a maximum gain of 17.64[Formula: see text]dB while consuming 8.18[Formula: see text]mW of power from a 1.2[Formula: see text]V supply. It can be noted that the minimum noise figure (NF) achieved is 3.67[Formula: see text]dB and the corresponding IIP3 is 9.44[Formula: see text]dBm at 5[Formula: see text]GHz from the pre-layout simulations.

A Dual Frequency RF-DC Rectifier Circuit with a Low Input Power for Radio Frequency Energy Harvesting

The energy-harvesting radio frequency (RF) can be an attractive alternative energy capable of replacing all or some of the board batteries. The RF waves are present in several high frequencies ([Formula: see text] GHz) and at low power (a few [Formula: see text]W). An energy-harvesting circuit designed must provide 1[Formula: see text]V voltage at minimum that is able to operate an actuator or a sensor. The RF-DC rectifier is the main component of an energy-harvesting circuit. This paper presents a new design RF-DC rectifier circuit using the MOSFET transistors, the capacitors and the inductors. Our proposed circuit is a combination of an Inductor–Capacitor–Inductor–Capacitor (LCLC) serie-parallel resonant tank (SPRT) and rectifier cascade using the Dynamic threshold Voltage Cancellation (DVC) and the technique of the Internal threshold Voltage Cancellation (IVC). Our proposed circuit operates in dual frequencies [Formula: see text][Formula: see text]GHz and [Formula: see text][Formula: see text]GHz with a low input power [Formula: see text][Formula: see text][Formula: see text]W ([Formula: see text][Formula: see text]dbm) and [Formula: see text][Formula: see text][Formula: see text]W ([Formula: see text][Formula: see text]dbm), respectively. This circuit gives a Power Conversion Efficiency (PCE) of 56.9% and an output voltage [Formula: see text][Formula: see text]V for the frequency 2.543[Formula: see text]GHz and a PCE of 62.6% and an output voltage [Formula: see text][Formula: see text]V for the frequency 4[Formula: see text]GHz. The pre-layout simulations were performed using the Advanced Design System (ADS) and the technology used is CMOS 0.18[Formula: see text][Formula: see text]m from TSMC. The simulations were performed on the proposed circuit composed by three stages.

Design and analysis of differential ring voltage controlled oscillator for wide tuning range and low power applications

SummaryVoltage‐controlled oscillator (VCO) is the most basic component required for all wireless and communication systems. In this article, a four‐stage differential ring VCO with two control voltages for wide tuning range is proposed. This VCO uses the dual‐delay loop technique for high operation frequency. Also, a low‐VT NMOS transistor is used in series with pull down network of the proposed VCO delay cell to achieve low frequencies. Prelayout simulation of the proposed VCO is performed in 65‐nm TSMC CMOS technology in Cadence software under 1.2‐V supply voltage. The tuning range of the proposed VCO varies from 1 MHz to 13.8 GHz and has been improved by 19.77% compared to other works. The power consumption of this low power VCO is between 29.3 μW to 1.715 mW. The phase noise of the proposed circuit is −82.3 dBc/Hz at 1 MHz offset frequency and −106.9 dBc/Hz at 10 MHz offset frequency from 5.161 GHz center frequency, while its area is 102.457 μm2. This design demonstrates other benefits in low power consumption and area compared with other ring oscillators.

Generation of square and triangular wave with independently controllable frequency and amplitude using OTAs only and its application in PWM

This paper presents a self-generating square/triangular wave generator using only the CMOS Operational Transconductance Amplifiers (OTAs) and a grounded capacitor. The output frequency and amplitude of the proposed circuit can be independently and electronically adjusted. The proposed circuit validates its advantage by consuming less amount of power, which is about 71.3 µW. The theoretical aspects are authentically showcased using the PSPICE simulation results. The performance of the proposed circuit is also verified through pre layout and post layout simulation results using the 90 nm GPDK CMOS parameters. A prototype of this circuit has been made using commercially available IC CA3080 for experimental verification. Experimentation also gives the similar output as per the theoretical proposition. The designed circuit is also made applicable to perform pulse width modulation (PWM).

A New Transresistance-Mode Instrumentation Amplifier with Low Number of MOS Transistors and Electronic Tuning Opportunity

In this paper, the simplest possible electronically adjustable transresistance-mode (TRM) instrumentation amplifier (IA) using only eight MOS transistors is presented. Extremely simple structure of the proposed IA leads to a wide bandwidth and robust performance against mismatches and parasitic capacitances. Of more interest is that the differential-mode gain of the proposed IA can be electronically varied by control voltages. Post-layout and pre-layout simulation results based on 0.18[Formula: see text][Formula: see text]m TSMC CMOS parameters are included to confirm the validity of the theoretical analysis. Despite extremely simple structure, its input and output impedances are 1.93 and 1.68[Formula: see text]k[Formula: see text], respectively. Time domain analysis shows that for an input signal of 20[Formula: see text][Formula: see text]A peak to peak, maximum value of THD is 4.5% for different frequencies. Monte Carlo simulation is also carried out, which proves robust performance of the proposed IA against mismatches. The required chip area is only [Formula: see text].

A Modified PFD Based PLL with Frequency Dividers in 0.18-&amp;#181;m CMOS Technology

This paper introduces a modified design of CMOS dynamic Phase Frequency Detector (PFD). The proposed PFD circuit (PPFD) is designed, simulated and the results obtained are analyzed. In order to reduce dead zone, internal signal routing is used in the PPFD circuit. To extend, Phase Locked Loop (PLL) is designed and it is verified with two different Frequency Divider (FD) circuits. There is a decrease in area of the PPFD circuit with 16 transistors and dissipates power of 40.8 pW for 1.2 V power supply. The pre-layout simulation result shows that the PPFD circuit has an elimination of a dead zone. Further, it works with the high speed and reduced power operated in the reference frequency of 50 MHz and the feedback frequency up to 4 GHz.

A Low-Voltage Fully Differential Pure Current Mode Current Operational Amplifier

In this paper a novel high-frequency fully differential pure current mode current operational amplifier (COA) is proposed that is, to the authors' knowledge, the first pure MOSFET Current Mode Logic (MCML) COA in the world, so far. Doing fully current mode signal processing and avoiding high impedance nodes in the signal path grant the proposed COA such outstanding properties as high current gain, broad bandwidth, and low voltage and low-power consumption. The principle operation of the block is discussed and its outstanding properties are verified by HSPICE simulations using TSMC $$0.18\,\upmu \hbox {m}$$0.18μm CMOS technology parameters. Pre-layout and Post-layout both plus Monte Carlo simulations are performed under supply voltages of $$\pm 0.75\,\hbox {V}$$±0.75V to investigate its robust performance at the presence of fabrication non-idealities. The pre-layout plus Monte Carlo results are as; 93 dB current gain, $$8.2\,\hbox {MHz}\,\, f_{-3\,\text {dB}}, 89^{\circ }$$8.2MHzf-3dB,89? phase margin, 137 dB CMRR, 13 $$\Omega $$Ω input impedance, $$89\,\hbox {M}\Omega $$89MΩ output impedance and 1.37 mW consumed power. Also post-layout plus Monte Carlo simulation results (that are generally believed to be as reliable and practical as are measuring ones) are extracted that favorably show(in abovementioned order of pre-layout) 88 dB current gain, $$6.9\,\hbox {MHz} f_{-3\text {db}} , 131^{\circ }$$6.9MHzf-3db,131? phase margin and 96 dB CMRR, $$22\,\Omega $$22Ω input impedance, $$33\,\hbox {M}\Omega $$33MΩ output impedance and only 1.43 mW consumed power. These results altogether prove both excellent quality and well resistance of the proposed COA against technology and fabrication non-idealities.

Low Leakage and High Performance tag Comparator Implemented in 180 nm CMOS Technology

The parasitic capacitance in the dynamic node increases for wide tag comparator increasing the delay and power consumption. The output signal may also degrade with high performance computing that uses clock frequency over 1GHz. In this paper a circuit is proposed to reduce the delay of the evaluation phase of the 64 bit tag comparator by reducing the parasitic capacitance at the dynamic node. The circuit is applicable for wide fan-in gates. The performance has enhanced by 60-70% with reduced leakage providing reduced voltage degradation of the output signal when compared to the rest of the dynamic circuit under study. The Mentor Graphics tool kit is used to perform pre-layout simulations, circuit layout generation and physical verification of the layout.

A low power current controllable single-input three-output current-mode filter using MOS transistors only

A novel circuit configuration for the realization of low power single-input three-output (SITO) current mode (CM) filters employing only MOS transistors are presented. The proposed circuit can realize low-pass (LP), band-pass (BP) and high-pass (HP) filter functions simultaneously at three high impedance outputs without changing configuration. Despite the other previously reported works, the proposed circuit is free from resistors and passive capacitors. Instead of passive capacitors; the gate-source capacitor of MOS transistor is used making the proposed circuit ideally suitable for integration. Compared to other works, the proposed filter has also the lowest number of transistors and lowest power consumption. The proposed circuit exhibits low-input and high-output impedances, which is highly desirable for cascading in CM signal processing. Moreover, it is center frequency can be electronically adjusted using a control current without a significant effect on quality factor (Q) granting it the highly desirable capability of electronic tunability. Transfer functions of the LP, BP and HP outputs are derived and the performance of the proposed circuit is proved through pre layout and post layout simulations at supply voltage of 1.8V and using 0.18μm CMOS process parameters. The power consumption and the required chip area are only 0.5mW and 77.4μm×70.2μm, respectively.

Design of an Active-Gm-RC Reconfigurable Filter for the Multi-Mode Receiver

Based on TSMC 0.18m RF CMOS process a reconfigurable low-pass filter (LPF) is presented in this paper. The LPF adopts active-Gm-RC structure. By manually adjusting the capacitor arrays, the LPF can switch working mode and correct frequency offset caused by process deviation. The pre-layout simulation shows that with 1.8V power supply, the bandwidth ranges from 1.4MHz to 9.8MHz with a step of 1.4MHz. The out of band attenuation is about-80dB/10 octave and the power consumption is 0.43mW .

Crosstalk Minimization in VLSI Interconnects

&lt;p&gt;Crosstalk noise is often induced in long interconnects running parallel to each other .There arises a need to minimize the effect of these crosstalk noise so as to maintain the signal integrity in interconnects. So in this paper crosstalk noise is minimized using various techniques such as repeater (bidirectional buffer) insertion along with shielding, skewing and shielding &amp;amp; skewing simultaneously. With the help of these techniques crosstalk noise is controlled to a great extent in long interconnects. Prelayout simulations for crosstalk are carried out for different techniques at 90nm technology nodes using cadence. The influences of these techniques are analyzed and it is found that crosstalk is reduced upto 57%.&lt;/p&gt;