Pre-emphasis Transmitter Research Articles

A 15 Gb/s Non-Return-to-Zero Transmitter With 1-Tap Pre-Emphasis Feed-Forward Equalizer for Low-Power Ground Terminated Memory Interfaces

This brief presents a 1-tap pre-emphasis transmitter (TX) for a single-ended ground-terminated memory interface with 28 nm complementary metal-oxide-semiconductor (CMOS) technology. By employing a charge pump scheme, a voltage level below ground was used to remove inter-symbol interference (ISI). Encoded with the unit interval (UI) delayed data, the proposed equalization technique increases the vertical voltage margin for the receiver (RX) compared to conventional feed-forward equalization (FFE). In addition, the short current after equalization was removed, and impedance matching for reflection was facilitated. The data rate of the proposed work is 15 Gb/s, and the data path power dissipation for the entire design is 20.3 mW. The measured energy efficiency is 1.35 pJ/bit, and the total area occupation is 0.008 mm².

A 6.84 Gbps/lane MIPI C-PHY Transceiver Bridge Chip With Level-Dependent Equalization

A 3.0 GSymbol/s/lane transceiver bridge chip, which fully supports the mobile industry processor interface (MIPI) C-PHY version 1.1 specification, is proposed for field-programmable gate array (FPGA)-based pattern generators and frame grabbers. In transmit mode, it converts parallel low-voltage complementary metal oxide semiconductor (CMOS) signals into high-speed three-level signals when performing serialization. In addition, deserialization including clock recovery from the received data is performed for its receive mode operation. A pre-emphasis transmitter and an elastic receiver that perform equalization according to the signal level are proposed to improve the signal integrity of high-speed three-level signals. The proposed MIPI C-PHY transceiver bridge chip is implemented using a 65 nm CMOS process with 1.2 V supply voltage. The area of each lane is 0.103 mm2 and the power consumption in high-speed transmit and receive modes is 2.96 mW/Gbps/lane and 5.62 mW/Gbps/lane, respectively. The measured peak-to-peak time jitter of the proposed high-speed transmitter, receiver, and clock recovery are 0.27 UI, 0.35 UI, and 90 ps, respectively, at a data rate of 3 GSymbol/s/lane.

A 5 Gbps serial link pre-emphasis transmitter with a novel-designed register based multiplexer

A serial link transmitter with 4-tap pre-emphasis is presented in this manuscript. The system consists of two 5:1 multiplexers, a 2:1CML multiplexer, and a driver with 4-tap pre-emphasis. A new 5:1 multiplexer structure is proposed to prevent sampling on the data edge, which shows a lower power consumption and chip size. Implement in standard 180nm CMOS 1P6M process with 1.8V power supply, the newly designed transmitter can be able to work with bit error rate (BER) as 10−14. The transmitter output jitter is 0.09UI while the amplitude can reach from 540mV to 750mV.

CCS: A low-power capacitively charge-sharing transmitter for NoC links

In this letter, a capacitively charge-sharing transmitter (CCS) is proposed as a novel design to replace the traditional differential capacitive pre-emphasis transmitter (CPE), for the purpose of reducing the dynamic power consumption by half. The CCS functions as a transmitter for mesh NoC links to achieve high-speed and low-power transmission. CCS generates a pair of differential low-swing signals at a time through charge-sharing. Its capacitively driven mode enables high-speed transmission and provides pre-emphasis to extend the bandwidth. Simulation shows that CCS can achieve 9Gb/s data rate over 2mm twisted differential interconnects with only 56.4fJ/b power consumption. With a clockless hysteresis receiver, the transceiver for NoC links enables a data rate of 7Gb/s with at least 70% eye-opening while consumes only 90.8fJ/b.

Pre‐emphasis transmitter (0.007 mm 2 , 8 Gbit/s, 0–14 dB) with improved data zero‐crossing accuracy in 65 nm CMOS

A pre-emphasis transmitter with improved data zero-crossing accuracy is described. It is achieved via data re-synchronisation using a set of extended true single-phase clock latches before output combining, constituting a robust, area- and power-efficient solution. Fabricated in 65 nm CMOS, the full-rate one-tap pre-emphasis transmitter measures a total jitter of 33.12 ps up to an 8 Gbit/s data rate, and 25.04 to 38.75 ps under a 0–14 dB reconfigurable pre-emphasis range. The achieved output swing is as large as 550 mVpp, and the active area is just 0.007 mm2.

Active terminated current-mode pre-emphasis transmitter for PCI Express standard

In this work we propose an active terminated current-mode pre-emphasis transmitter for high-speed chip-to-chip data communication. The salient feature of this current-mode transmitter is, it selectively provides high output port impedance while driving and 100-Ω differential impedance for the reflected signal coming back to the transmitter end. This feature helps in halving the signal current level for a specified signal swing at the output of the transmitter compared to traditional passive terminated current-mode transmitter. In the transmitter, a scaled down replica driver followed by a differential common drain is connected in parallel with the main driver. The output port impedance of this composite driver is matched with the characteristic impedance of the channel. However, while driving, the output signal appears to the output port through the replica and the main stage resulting in high impedance. The circuits have been implemented in a 1.8-V, 0.18-μm Digital CMOS technology meeting PCI Express standard. The simulated performance shows data transfer rate of 5 Gb/s, while transmitting the data over 15-in. FR4 PCB trace for a target bit-error rate (BER) of 10 12. The power consumed in the replica stage and main driver stage are 1.98 mW and 16.38 mW respectively for a target differential voltage swing of 800 mV.

Low-Power, High-Speed Transceivers for Network-on-Chip Communication

Networks on chips (NoCs) are becoming popular as they provide a solution for the interconnection problems on large integrated circuits (ICs). But even in a NoC, link-power can become unacceptably high and data rates are limited when conventional data transceivers are used. In this paper, we present a low-power, high-speed source-synchronous link transceiver which enables a factor 3.3 reduction in link power together with an 80% increase in data-rate. A low-swing capacitive pre-emphasis transmitter in combination with a double-tail sense-amplifier enable speeds in excess of 9 Gb/s over a 2 mm twisted differential interconnect, while consuming only 130 fJ/transition without the need for an additional supply. Multiple transceivers can be connected back-to-back to create a source-synchronous transceiver-chain with a wave-pipelined clock, operating with 6sigma offset reliability at 5 Gb/s.

An area-power efficient 4-PAM full-clock 10-Gb/s CMOS pre-emphasis serial link transmitter

This paper presents a new area-power efficient 4-PAM full-clock CMOS pre-emphasis transmitter for 10-Gb/s serial links. The proposed transmitter reduces the chip area and power consumption by minimizing the number of digital-to-analog converters for 4-PAM signaling and pre-emphasis. In addition, a new full-clock scheme is proposed to double the data rate without increasing the sampling clock frequency. To assess the effectiveness of the proposed transmitter, a 8-to-1 serial link consisting of the proposed transmitter and a pair of terminated microstrip lines with a FR4 substrate has been implemented in TSMC 0.18 μm 1.8 V CMOS technology and analyzed using SpectreRF from Cadence Design Systems with BSIM3.3V transistor models that count for both device parasitics and second-order effects. Simulation results are presented.

An area-power efficient CMOS 4-PAM class AB current-mode pre-emphasis serial link transmitter

This paper presents an area-power efficient CMOS 4-PAM class AB current-mode pre-emphasis transmitter for multi-Gb/s serial links. The proposed transmitter minimizes both chip area and power consumption by constructing pre-emphasis symbols directly from the current symbol, eliminating the need for complex FIR filters and digital-to-analog converters. The differential output current obtained from a class AB pre-amplifier and the push-pull operation of both the current-symbol and pre-emphasis drivers minimizes the electromagnetic interference exerted by channels to neighboring devices. The use of latches at both the multiplexer and pre-amplifier minimizes the effect of power fluctuation and ground bouncing on the output current of the transmitter. The proposed transmitter has been implemented in both UMC-0.13 μm 1.2 V and TSMC-0.18 μm 1.8V CMOS technologies and analyzed using SpectreRF from Cadence Design Systems with BSIM3.3v device models. The effectiveness of the proposed transmitter architecture is validated from the simulation results of both designs.

A Large-Swing Transformer-Boosted Serial Link Transmitter With $>{\rm V}_{\rm DD}$ Swing

The design and analysis of a large-swing transformer-boosted serial link transmitter is described. Transformer boosting is used to produce a signal swing that is not constrained by the supply voltage and enables a true pre-emphasis transmitter with a differential output swing greater than the supply. The boosted signal is separated from the driver through series inductors and therefore does not stress the transistor voltage tolerance. Several design tradeoffs between the amounts of boosting, power, and output matching are examined in both analysis and simulation. Distributed boosting is employed to relax the tradeoff between the amount of boosting and output matching degradation. Implemented in a 0.13-mum CMOS technology, the prototype chip produces an 8-Gb/s PRBS 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">31</sup> -1 data pattern and achieves a 1.42 V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">pp</sub> differential output swing while drawing 137 mA current from a 1.2-V supply. The measured output reflection coefficient is better than -10dB up to 4 GHz

A 20-Gb/s 256-Mb DRAM With an Inductorless Quadrature PLL and a Cascaded Pre-emphasis Transmitter

A 20-Gb/s 256-Mb DRAM with the proposed PLL and transmitter schemes has been designed and fabricated using an 80-nm CMOS process. An inductorless tetrahedral oscillator generates inherent quadrant phases combined with cascaded pre-emphasis transmitter achieves 10-Gb/s/pin data rate.