PRBS Data Research Articles

A 32-Gb/s PAM4-Binary Bridge With Sampler Offset Cancellation for Memory Testing

This brief presents a 32-Gb/s PAM4-Binary bridge for the next-generation memory testing. The bridge incorporates all the required functions to evaluate a high-speed PAM4 memory using a low-speed NRZ tester. The low-speed data transmitted from the NRZ tester to the bridge are converted into high-speed PAM4 data through half-rate clock control and forwarded to the memory, and vice-versa. The ground-terminated PAM4 driver provides the single-ended output by controlling the output current with a 2-tap feed-forward equalizer, achieving a ratio level mismatch (RLM) of 0.95. To minimize the offset at the PAM4 receiver, the offset cancellation circuit with an offset of 2.76mV consisting of a CTLE and sampling latches is employed, and the horizontal margin of the received PAM4 signal is 50% for BER <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${ &lt; } 10^{-9}$ </tex-math></inline-formula> . An all-digital PLL integrated in the bridge doubles the 4-GHz WCK used as forwarded clock for the graphic memory. The count-based PAM4 eye-opening monitor is also proposed to find the optimal codes for the maximum eye opening using the PRBS7 data sequence. The bridge fabricated in the 40-nm CMOS technology occupies an active area of 1.6mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and dissipates 132mW.

A 35 Gb/s junction-less dual parallel Mach-Zehnder modulator for short reach interconnects

An electrostatic doping (ED) based 35 Gb/s dual-parallel Mach-Zehnder modulator (DP-MZM) for photonic integrated circuits (PICs) is proposed and analyzed. Theoretical formulation of the transfer function and linearity analysis of the proposed modulator is also presented here. The proposed modulator contains two ED-aided sub-MZMs and an ED-aided optical phase shifter (PS) in a MZI structure. Numerical simulations are performed using commercially available tools and the simulation results are presented here. From the results we estimate that the proposed DP-MZM with 400 μm long sub-MZMs can offer peak dynamic extinction ratio (ER) of 14 dB with maximum 8.7 dB of insertion loss (IL) at 10 Gb/s data rate. Using dual-tone test method, the predicted spurious free dynamic range (SFDR) of the modulator are 62.74 dB·Hz1/2 and 99.35 dB·Hz $$^{2/3}$$ for second and third harmonic intermodulation distortions (IMD2 and IMD3), respectively. From the transient analysis, the estimated maximum operating frequency and 3-dB EO bandwidth of the modulator are approximately 35.5 GHz and 32.37 GHz, respectively. At maximum data rate, 5.89 dB of dynamic ER is offered by the proposed DP-MZM for OOK modulation. Simulation verifies successful transmission of 25 Gb/s OOK modulated PRBS data stream over a 10 km standard single mode fiber (SSMF) link. Furthermore, we have shown that the proposed DP-MZM is capable of generating 50 Gb/s PAM-4 signal, which makes the modulator suitable for next-generation short-reach interconnects.

A 5–13.5 Gb/s Multistandard Receiver With High Jitter Tolerance Digital CDR in 40-nm CMOS Process

A 5-13.5 Gbps multi-standard I/O link receiver is presented in this paper. An inductor-free CTLE, whose gain and bandwidth are highly adjustable, is achieved by using the second-order negative capacitance circuit. A high jitter tolerance clock and data recovery (HJTOL-CDR) is proposed for Spread Spectrum Clock applications. In this work, the JTOL is improved by two ways: first, a partial-noise-shaping-based digital loop filter (PNS-DLF) is implemented to reduce the output jitter caused by the truncation error in the integral path; second, the proposed CDR logic is fully custom designed to operate at a quarter-rate clock of 5 GHz. Moreover, the CDR bandwidth can be tuned to satisfy various data rates and jitter masks. Post-layout simulation shows that the proposed CTLE can provide wide gain tuning range, the boost gain at 10 GHz is beyond 29 dB and the proposed CDR can tolerate up to 31-kppm frequency offset. The proposed receiver is fabricated in 40-nm CMOS with an active area of 0.06 mm2 and 65 mW power consumption at 20 Gbps from 1.2-V supply. Measurement results show that, when receiving the PRBS31 data at 10 Gbps with 5-kppm frequency offset across a channel with 14-dB loss, the JTOL is 0.39 UIpp at 10 MHz and can guarantee a 0.34 UIpp at high frequency, which proves that the proposed receiver can meet stringent standards such as PCIe 3.0/4.0, USB 3.2, DisplayPort 1.4.

Reconfigurable and Scalable Multimode Silicon Photonics Switch for Energy-Efficient Mode-Division-Multiplexing Systems

A novel integrated scalable multimode switch (SMS) is experimentally demonstrated using tapered multimode-interference-based couplers and Ti/W metal heater phase shifters for mode-division-multiplexing (MDM) silicon photonics switching. The SMS allows path-reconfigurable switching of the first two (TE0 and TE1) or the first three (TE0, TE1, and TE2) transverse electric (TE) modes using the same device achieving footprint efficiency for higher bandwidth density. A proof-of-concept realization of the two-mode switch demonstrates the (de)multiplexing and switching of broadband optical signals over the TE0 and TE1 modes exhibiting $-$ 6.5 dB insertion loss (IL) in the bar state and $-$ 7.3 dB IL in the cross state at 1550 nm with less than $-$ 14 dB crosstalk. Simultaneous switching of two parallel TE modes (TE0+TE1) exhibits less than $-$ 7.0 dB IL and $-$ 11.9 dB crosstalk at 1550 nm. An aggregated bandwidth of 2 × 10 Gb/s is experimentally achieved while switching between two non-return-to-zero PRBS31 data signals with <9.8 $\mu$ s switching time and >17.7 dB switching extinction ratio (ER) for individual-mode transmission, and <7.6 $\mu$ s switching time and >12.0 dB switching ER for dual-mode transmission. The SMS is scalable to switch higher order TE modes with lower energy consumption (up to 63% less) than the single-mode switches indicating its potential application in energy-efficient MDM photonic networks.

A Reconfigurable Multimode Demultiplexer/Switch for Mode-Multiplexed Silicon Photonics Interconnects

We experimentally demonstrate a scalable and broadband reconfigurable multimode demultiplexer/switch (RMDS) for mode-division multiplexed inter- and intra-chip data communication systems. The RMDS exploits a thermo-optically tuned tapered multimode interference coupler, enabling simultaneous transmission of the fundamental and first order quasi transverse electric modes in C-band. It is used as the building block in a mode demultiplexer with −20 dB crosstalk, which can be reconfigured as a mode selecting switch with 10.9 μs switching time. An aggregated bandwidth of 2 × 10 Gb/s is achieved by the parallel transmission of two nonreturn-to-Zero (NRZ) PRBS31 data signals at 10−12 bit-error-rate with 2.8 dB BER power penalty. A 1.55 pJ/bit energy efficiency is estimated for a proposed multimode optical link.

A Wideband Inductorless dB-Linear Automatic Gain Control Amplifier Using a Single-Branch Negative Exponential Generator for Wireline Applications

This paper reports a wideband inductorless automatic gain control (AGC) amplifier for wireline applications. To realize a dB-linear AGC range, a pseudo-folded Gilbert cell driven by a single-branch negative exponential generator (NEG) is proposed as the core variable-gain amplifier. The NEG features a composite of dual Taylor series to extend the AGC approximation range without sacrificing the precision. Fabricated in 65-nm CMOS, the AGC amplifier occupies a tiny die area of 0.045 mm2 and consumes 28 mW at 1.2 V. Measured over a dB-linear gain range of ~40 dB, < ± 1 dB gain error is achieved and the 3-dB bandwidth stays roughly constant at 7 GHz. For the closed-loop AGC measurement, the input dynamic range is ~40 dB (10 mVpp to 1 Vpp) for a BER <10−12 under a 27 − 1 PRBS data at 10 Gb/s. The achieved figure-of-merit (FOM) of 2.8 pJ/bit compares favorably with state-of-the-art.

A 32 Gb/s, 4.7 pJ/bit Optical Link With −11.7 dBm Sensitivity in 14-nm FinFET CMOS

This paper presents a 32 Gb/s non-return-to-zero optical link using 850-nm vertical-cavity surface-emitting laser-based multi-mode optics with 14-nm bulk FinFET CMOS circuits. The target application is the integration of optics on to the first-level package, connecting high-speed optical I/O directly to an advanced CMOS host chip (e.g., processor and switch) to increase package I/O bandwidth density and lower overall system power and cost. The optical link is designed for maximum link margin to tolerate high optical losses created by low-cost optical packaging. The transmitter (TX) uses a three-tap, 1/2-unit-interval-spaced feed-forward equalizer to improve eye opening. The receiver (RX) uses a low-bandwidth, low-noise transimpedance amplifier and a speculative one-tap decision-feedback equalizer for high sensitivity. The TX and RX power efficiencies are 3.3 and 1.4 pJ/bit, respectively. The TX optical modulation amplitude (OMA) is 1.2 dBm, and the RX sensitivity is −11.7 dBm OMA at a bit error rate of 10−12 with PRBS31 data, providing 12.9-dB link margin.

A 64-Gb/s 1.4-pJ/b NRZ Optical Receiver Data-Path in 14-nm CMOS FinFET

A 64-Gb/s high-sensitivity non-return to zero receiver (RX) data-path is demonstrated in the 14-nm-bulk FinFET CMOS technology. To achieve high sensitivity, the RX incorporates a transimpedance amplifier whose gain and bandwidth are co-optimized with a 1-tap decision feedback equalization (DFE). The DFE, which operates at quarter-rate, features a look-ahead speculation to relax DFE timing to 4 unit-interval. The analog front end includes a transadmittance transimpedance inductorless variable gain amplifier, resulting in a low power and compact front end. The RX, wirebonded to a discrete GaAs photodiode, achieves an energy efficiency of 1.4 pJ/bit and −5-dBm optical modulation amplitude while recovering PRBS-7 data (bit-error-rate $ ) modulated by a VCSEL driver with a 2-tap feed forward equalization (FFE) (main + precursor) over 7 m of graded-index 50/125- $\mu \text{m}$ multimode fiber. The measured sensitivities at 56 and 32 Gb/s are −9- and −13-dBm optical modulation amplitude, respectively.

A 40-Gb/s Quarter-Rate SerDes Transmitter and Receiver Chipset in 65-nm CMOS

This paper presents a 40-Gb/s transmitter (TX) and receiver (RX) chipset for chip-to-chip communications in a 65-nm CMOS process. The TX implements a quarter-rate multi-multiplexer (MUX)-based four-tap feed-forward equalizer (FFE), where a charge-sharing-effect elimination technique is introduced into the 4:1 MUX to optimize its jitter performance and power efficiency. The RX employs a two-stage continuous-time linear equalizer as the analog front end and integrates a low-cost sign-based zero-forcing engine relying on edge-data correlation to automatically adjust the tap weights of the TX-FFE. By embedding low-pass filters with an adaptively adjusting bandwidth into the data-sampling path and adopting high-linearity compensating phase interpolators, the clock data recovery achieves both high jitter tolerance and low jitter generation. The fabricated TX and RX chipset delivers 40-Gb/s PRBS data at BER 16-dB loss at half-baud frequency, while consuming a total power of 370 mW.

Mode selecting switch using multimode interference for on-chip optical interconnects.

A novel mode selecting switch (MSS) is experimentally demonstrated for on-chip mode-division multiplexing (MDM) optical interconnects. The MSS consists of a Mach-Zehnder interferometer with tapered multi-mode interference couplers and TiN thermo-optic phase shifters for conversion and switching between the optical data encoded on the fundamental and first-order quasi-transverse electric (TE) modes. The C-band MSS exhibits a >25 dB switching extinction ratio and < -12 dB crosstalk. We validate the dynamic switching with a 25.8 kHz gating signal measuring switching times for both TE0 and TE1 modes of <10.9 μs. All channels exhibit less than 1.7 dB power penalty at a 10-12 bit error rate, while switching the non-return-to-zero PRBS-31 data signals at 10 Gb/s.

A Ring-Based 25 Gb/s DAC-Less PAM-4 Modulator

A novel PAM-4 12.5 Gbaud/s inter-coupling modulator based on a Mach–Zehnder interferometer assisted ring resonator is demonstrated. The 25 Gb/s PAM-4 optical signal is generated by driving the modulator with two independent electrical signals with an amplitude of 3 V $_{pp}$ at 2 V reverse bias. Reverse bias operation mode of the modulator enables achieving an electro-optic (EO) bandwidth of approximately 14 GHz without preemphasis of the electrical driving signals or equalization techniques. This configuration successfully simplifies the operation of the modulator in generating PAM-4 signals without the need for a digital-to-analog converter (DAC). Experimental results show proper generation of a PRBS data stream. The proposed modulator has a compact footprint of 0.48 mm $^2$ with a bandwidth density of 52.08 Gb/s/mm $^2$ .

Integrated optical deserialiser time sampling based SiGe photoreceiver.

A novel photoreceiver architecture enabling parallel processing in the electronic domain of a high-speed optical signal is demonstrated. This allows the electronics to operate at significantly lower frequency than the optical signal and hence reduce power consumption and the impact of parasitics. The photoreceiver performs optical time sampling with four integrated SiGe photodetectors connected in series by waveguide delay lines. Four variations of the optical time sampling receiver are designed and demonstrated which differ by the data rate (10 Gb/s and 20 Gb/s) and silicon delay waveguide loss (2.5 dB/cm and 0.2 dB/cm). The bit error rate performance of the photodetectors in the receiver was measured individually and reached a performance below 1 × 10⁻¹⁰ at an input optical power between 4.8 and 6.3 dBm through an off-chip 50 Ω load at the output. After O/E conversion, the electrical signal (one segment of 2¹⁵ - 1 PRBS data) from each of the photodetector is processed without errors at a quarter of the bit rate, leading to an overall more power efficient receiver front-end.

A 10 Gb/s adaptive analog decision feedback equalizer for multimode fiber dispersion compensation in 0.13 $${\upmu }$$ μ m CMOS

A 10 Gb/s adaptive analog decision feedback equalizer with 6 taps is realized in 0.13 $$\upmu$$ μ m CMOS. An analog implementation of the LMS algorithm is used to continuously adapt the feedback filter coefficients. A clock and data recovery circuit is used to extract the clock from the DFE output. The adaptive DFE dissipates 318 mW, not including output buffers, and can equalize PRBS data corrupted by a 300-m multimode fiber achieving BER $$< 10^{-13}$$ < 10 - 13 .

On-Chip Measurement of Clock and Data Jitter With Sub-Picosecond Accuracy for 10 Gb/s Multilane CDRs

On-chip jitter measurement can be used to optimize the performance of wireline transceivers. In this work, the jitter of random data is measured on-chip by correlating the phase detector outputs from two adjacent CDR lanes. This allows the jitter's autocorrelation function to be estimated, from which the jitter's RMS value and power spectral density are extracted without using any external reference clock. The RMS value of random jitter ranging from 0.85 ps to 1.89 ps, and sinusoidal jitter from 0.89 ps to 5.1 ps is measured in PRBS31 data with less than 0.6 ps of error compared to measurements by an 80 GS/s real-time oscilloscope. Correlating the phase detectors in the CDRs with a third phase detector, which measures the phase difference between the clocks recovered by the two CDRs, allows measurement of the recovered clock jitter. Sinusoidal jitter from 1.8 ps to 5.3 ps is measured in the recovered clock with an error of less than 1 ps.

A 16 Gb/s 3.7 mW/Gb/s 8-Tap DFE Receiver and Baud-Rate CDR With 31 kppm Tracking Bandwidth

A 16 Gb/s I/O link receiver fabricated in 22 nm CMOS SOI technology is presented. Attenuation and ISI of transmitted NRZ data across PCB channels are equalized with a CTLE feeding an 8-tap DFE. The first tap uses digital speculation and the following seven taps are realized by means of the switched-capacitor technique. Timing recovery and control are performed with a Mueller-Müller type-A baud-rate CDR. The architecture is half-rate and requires one phase rotator. In total, each slice has six comparators to recover data and timing information. The secondorder digital CDR operates at quarter-rate and features a low-latency implementation of the proportional path. At 16 Gb/s, 1 Vppd PRBS31 data transmitted without FFE equalization is recovered across a PCB channel with 34 dB attenuation at 8 GHz. The measured tracking bandwidth is 31 kppm (16 GHz ± 496 MHz), and an amplitude of 3 UIPP is tolerated at 1 MHz sinusoidal jitter. The sinusoidal jitter amplitude tolerance measured at 10 Gb/s is 0.4 UIPP at 10 MHz and remains above 0.2 UIPP up to 1 GHz with PRBS31 data recovered (BER <; 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup> ) across a PCB channel with 27 dB attenuation at 5 GHz. The power efficiency is 3.7 mW/Gb/s, including the full-rate clock receiver.

A Reference-Less Clock and Data Recovery Circuit Using Phase-Rotating Phase-Locked Loop

A reference-less half-rate digital clock and data recovery (CDR) circuit employing a phase-rotating phase-locked loop (PRPLL) as phase interpolator is presented. By implementing the proportional control in phase domain within the PRPLL, the proposed CDR decouples jitter transfer (JTRAN) bandwidth from jitter tolerance (JTOL) corner frequency, eliminates jitter peaking, and removes JTRAN dependence on bang-bang phase detector gain. Fabricated in a 90 nm CMOS process, the prototype CDR achieves error-free operation (BER <; 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup> ) with PRBS data sequences ranging from PRBS7 to PRBS31. At 5 Gb/s, it consumes 13.1 mW power and achieves a recovered clock long-term jitter of 5.0 ps rms/44.0 ps pp when operating with PRBS31 input data. The measured JTRAN bandwidth is 2 MHz and JTOL corner frequency is 16 MHz. The CDR is tolerant to 110 mV pp of sinusoidal noise on the DCO supply voltage at the worst case noise frequency of 7 MHz. At 2.5 GHz, the PRPLL consumes 2.9 mW and achieves -134 dBc/Hz phase noise at 1 MHz frequency offset. The differential and integral non-linearity of its digital-to-phase transfer characteristic are within ±0.2 LSB and ±0.4 LSB, respectively.

Real-time dual-band wireless videos in millimeter-wave radio-over-fiber system

A dual-band converged radio-over-fiber (RoF) access system at 60-GHz and 100-GHz millimeter-wave (mm-wave) is proposed. Real-time end-to-end delivery of two channels of independent high-definition (HD) video services simultaneously carried on 60-GHz and 100-GHz radios is demonstrated for the first time. PRBS data transmission with equivalent data rate and format is also tested to characterize the system performance. The analysis of the spectrum from the beating signal indicates the entire 60-GHz band and the W-band can be retrieved without interference. The real-time HD video display and error-free (BER<10–9) data transmission demonstrate the feasibility of the proposed wireless access system using converged fiber-optic and mm-wave RoF techniques.

A Fully-Integrated 40-Gb/s Transceiver in 65-nm CMOS Technology

This paper introduces a fully-integrated wireline transceiver operating at 40 Gb/s. The transmitter incorporates a 5-tap finite-inpulse response (FIR) filter with LC-based delay lines precisely adjusted by a closed-loop delay controller. The receiver employs a similar 3-tap FIR filter as an equalizer front-end with digital adaptation, and a sub-rate clock and data recovery circuit using majority voting phase detection. The transceiver delivers 40-Gb/s 27-1 PRBS data across a Rogers channel of 20 cm (19-dB loss at 20 GHz) with BER <; 10-12 while consuming a total power of 655 mW.

50 GHz Spaced 25 × 40 Gbit/s WDM Transmission Over 560 km Using SMF-Based Large Effective Area Fiber (LEAF)

In this paper, we present 50 GHz spaced 25 <img src=image/10.5923.j.ijoe.20120201.04_001.gif></img> 40 Gbit/s WDM transmission over 560 km using SMF-based Large Effective Area Fiber (LEAF) in a recirculating loop. The paper uses band-limited RZ signals carrying 2<SUP>31</SUP>-1 PRBS data, and shows that transmission distance of 560 km can be achieved with BER ≤ 10<SUP>-9 </SUP>using 1 mW peak power and 4 ps pulse-width for each data signal. To attain this, optical filters with sharp transmission characteristics are used in both transmitter and receiver. The results demonstrated in this paper are based on simulation, and the author believes that the propagation distance reached in the paper is the longest distance achieved for such system

A TDC-Less 7 mW 2.5 Gb/s Digital CDR With Linear Loop Dynamics and Offset-Free Data Recovery

A digital clock and data recovery circuit (CDR) employs hybrid analog/digital phase detection to achieve linear loop dynamics and to eliminate the nonlinearity and quantization error of a bang-bang phase detector. The proposed architecture achieves constant jitter transfer bandwidth independent of input data jitter and reduces the sensitivity to digitally-controlled oscillator's frequency quantization error and consecutive identical digits. The hybrid phase detection scheme also helps decouple jitter generation from jitter transfer characteristics of the CDR. The proto-type digital CDR fabricated in 0.13 μm CMOS technology achieves error-free operation (BER <; 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup> ) for PRBS data sequences ranging from 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">7</sup> - 1 to 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">31</sup> -1 sequence lengths over 0.5 Gb/s to 3.2 Gb/s data rates. At 2.5 Gb/s, the CDR consumes 7 mW power from a single 1.2 V supply and the recovered clock jitter is 5.7 ps rms.