Abstract
A novel photoreceiver architecture enabling parallel processing in the electronic domain of a high-speed optical signal is demonstrated. This allows the electronics to operate at significantly lower frequency than the optical signal and hence reduce power consumption and the impact of parasitics. The photoreceiver performs optical time sampling with four integrated SiGe photodetectors connected in series by waveguide delay lines. Four variations of the optical time sampling receiver are designed and demonstrated which differ by the data rate (10 Gb/s and 20 Gb/s) and silicon delay waveguide loss (2.5 dB/cm and 0.2 dB/cm). The bit error rate performance of the photodetectors in the receiver was measured individually and reached a performance below 1 × 10⁻¹⁰ at an input optical power between 4.8 and 6.3 dBm through an off-chip 50 Ω load at the output. After O/E conversion, the electrical signal (one segment of 2¹⁵ - 1 PRBS data) from each of the photodetector is processed without errors at a quarter of the bit rate, leading to an overall more power efficient receiver front-end.
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