Powering Circuits Research Articles

Development and Implementation of a RC Snubber to Suppress Breaker Arcing Present in High-Stored-Energy Superconducting Magnet Systems

Arc suppression Snubbers offer safety in high energy superconducting magnet systems. Large superconducting magnets may have arcing across their breakers at the moment of slow dump initiation resulting from a sudden current redistribution in the powering circuit. The ATLAS Experiment at CERN experiences such arcing with its 7.3 H Toroidal magnet powering circuit. To discharge the magnets, the current is redistributed to a parallel branch called the Run Down Unit (RDU) by means of a breaker. Due to the physical layout and other metallic components in the vicinity, the power supply and RDU branches have undesirable and unavoidable parasitic inductance, causing a voltage spike over the main breakers at the moment of opening. The resulting arcing deteriorates the breaker contacts, resulting in increased operating temperatures and a more frequent need for maintenance. The arc suppression system developed takes the form of an RC Snubber (Resistor-Capacitor). The Snubber offers the current a low-impedance path, thus smoothing out the current redistribution and suppressing the voltage spike. This initial charging period of the capacitors gives the current enough time to overcome the parasitic inductance, therefore allowing the RDU to smoothly ramp up without a sudden voltage spike. To test the concept, a 1/50th scale demonstrator was developed and showed successful results. After the demonstrator, endurance testing of the electrolytic capacitors was performed to ensure no degradation of the charging characteristics for an equivalent of 20 years of operation. The Snubber was manufactured and implemented with successful results on the ATLAS Toroidal powering circuit.

Electro-thermal analysis of the superconducting dipole circuit of SIS100

The heavy ion synchrotron SIS100, the core machine of the new international Facility for Antiproton and Ion Research (FAIR) in Darmstadt, is currently under construction. The 108 superconducting dipole magnets of SIS100 will be powered in series with a cycling rate up to 30kAs−1 which corresponds to 4Ts−1. The dipole magnet protection system considers 12 energy extraction resistors and two crowbars at the outputs of two power converters. As a part of the Failure Mode and Effects Analysis, the most critical failures of the magnet protection system are simulated. In this contribution, initial studies of the electrical and thermal behaviour of the SIS100 main dipole circuit during a quench are presented. The dipole magnet design and topology of the powering circuit (including the protection system) are described. The electro-thermal model in use is detailed. Finally, simulation of a failure mode of the magnet protection system is presented and results are discussed.

User defined elements in ANSYS for 2D multiphysics modeling of superconducting magnets

Dynamic simulation of superconducting magnets is critical for the design of quench protection systems to prevent potentially damaging temperatures and high voltage from developing after magnet quench. Modeling these scenarios is challenging due to the many multiscale phenomena which impact magnet behavior. These range from conductor scale effects of quench and interfilament coupling currents up to the behavior of the magnet in its powering and protection circuit. In addition, a strong coupling between electromagnetic and thermal domains is required to capture temperature and field dependent material properties and quench behavior. We present a finite element approach which integrates the various effects into the commercial software ANSYS by means of programming new element types. This is shown capable of simulating the strongly coupled transient electromagnetic, thermal, and circuit behavior of superconducting magnets required for quench protection studies. A benchmarking study is presented which shows close agreement between the new ANSYS elements and a COMSOL Multiphysics implementation developed at CERN for dump resistor and coupling loss induced quench based magnet protection of a Nb3Sn block dipole. Following this, the ANSYS implementation is shown reproducing strongly coupled quench back behavior observed during the test of a Nb3Sn superconducting undulator prototype at Lawrence Berkeley National Laboratory.

Car Security System using Fingerprint scanner and IOT

Objectives: This paper presents a noble system to detect vehicle thefts. If an unauthorized person tries to steal the vehicle, user and police station will be notified with GPS location. Methods: Fingerprints stored in the memory of the system. If the fingerprint and RFID matches with the stored ones then the controller triggers the powering circuit of the ECM else if the burglar tries to start the car in any other ways it sends the alert messages of the interventions as well as the car’s location to the owner’s mobile app via cloud. Findings: The system is implemented using Intel Galileo gen2 board. The GPS, GSM, Wi-Fi module as well as an SD Card is also connected to the board. Installing this smart system is helpful because this system won’t let the ECM to power on the engine as designed. The system also incorporates certain other sensors to stop the car burglary. If the burglar tries to turn on the battery by using paperclips in the fuses then the owner will be notified about the past proceedings along with GPS location of the car. Application: The system works well with low-price range car employed with keyless entry and self-start button and is unique because it uses IoT to protect the low price cars. Keywords: ECM, IoT, GPS, GSM, RFID

Advanced power analysis methodology targeted to the optimization of a digital pixel readout chip design and its critical serial powering system

A dedicated power analysis methodology, based on modern digital design tools and integrated with the VEPIX53 simulation framework developed within RD53 collaboration, is being used to guide vital choices for the design and optimization of the next generation ATLAS and CMS pixel chips and their critical serial powering circuit (shunt-LDO). Power consumption is studied at different stages of the design flow under different operating conditions. Significant effort is put into extensive investigations of dynamic power variations in relation with the decoupling seen by the powering network. Shunt-LDO simulations are also reported to prove the reliability at the system level.

Implantable Semi-Active UHF RFID Tag With Inductive Wireless Power Transfer

The objective of this letter was to design a compact, battery-less system for an implantable semi-active UHF radio frequency identification (RFID) tag with inductive wireless power transfer for the human body. An RFID chip of the tag, combining powering from a reader by communication and from another source through inductive wireless power transfer, was used. Tag sensitivity for communication was increased by about 21 dB with the help of wireless inductive powering when compared to tags that did not employ this system. Communication and powering circuits were integrated within compact structures on the sides of the reader and the tag. The structure for communication and powering on the side of the reader consists of a center-excised Archimedes spiral antenna and a circular loop, respectively. Similarly, the structure on the side of the tag consists of a folded dipole antenna for communication and a rectangular loop for powering.

Design, Assembly, and Test of the CERN 2-m Long 11 T Dipole in Single Coil Configuration

The upgrade of the LHC collimation system includes additional collimators in the LHC lattice. The longitudinal space for the collimators can be obtained by replacing some LHC main dipoles with shorter but stronger dipoles compatible with the LHC lattice and the existing powering circuits, cryogenics, and beam vacuum. A joint development programme aiming at building a 5.5 m long two-in-one aperture Nb 3 Sn dipole prototype suitable for installation in the LHC is being conducted by FNAL and CERN. As part of the first phase of the programme, 1 m and 2 m long single aperture models are being built and tested. Later on, the collared coils from these models will be assembled and tested in a two-in-one aperture configuration in both laboratories. A 2 m long practice model made of a single coil wound with Nb 3 Sn cable, MBHSM101, was developed and constructed at CERN. It has been completed, and tested at both 4.3 K and 1.9 K. This practice model features collared coils based on removable pole concept, S2-glass cable insulation braided over a mica layer, and coil end spacers made of sintered stainless steel with springy legs. The paper describes the main features of this practice model, the main manufacturing steps and the results of the cold tests.

Study of On-Line Monitoring Device for SF<sub>6</sub> Humidity

On-line monitoring device for SF6 humidity based on ZigBee was composed of processors, signal conditioning units (SCU), data-collection devices, ZigBee wireless network communication technology, control equipment of ventilation and alarm and powering circuits. Data information of humidity, temperature and pressure of SF6 gas can be monitored by the device. The application of information blending technique decreased the error of measuring, and achieved auto-calibration of measurement systems, compensation of measured data and signal output control, and improved precision of the reliability of measurement, and extended the service life.

Design and implementation of a RF powering circuit for RFID tags or other batteryless embedded devices.

A RF powering circuit used in radio-frequency identification (RFID) tags and other batteryless embedded devices is presented in this paper. The RF powering circuit harvests energy from electromagnetic waves and converts the RF energy to a stable voltage source. Analysis of a NMOS gate-cross connected bridge rectifier is conducted to demonstrate relationship between device sizes and power conversion efficiency (PCE) of the rectifier. A rectifier with 38.54% PCE under normal working conditions is designed. Moreover, a stable voltage regulator with a temperature and voltage optimizing strategy including adoption of a combination resistor is developed, which is able to accommodate a large input range of 4 V to 12 V and be immune to temperature variations. Latch-up prevention and noise isolation methods in layout design are also presented. Designed with the HJTC 0.25 μm process, this regulator achieves 0.04 mV/°C temperature rejection ratio (TRR) and 2.5 mV/V voltage rejection ratio (VRR). The RF powering circuit is also fabricated in the HJTC 0.25 μm process. The area of the RF powering circuit is 0.23 × 0.24 mm2. The RF powering circuit is successfully integrated with ISO/IEC 15693-compatible and ISO/IEC 14443-compatible RFID tag chips.

Designing a Real Time Redactor for Power Saving Utilization

Nowadays high importance is given to the development of green technologies which are designed with an emphasis on low energy consumption. Due to the financial crisis the need for such green technologies and devices is more important ever before. All home electric appliances like refrigerators, deep-freezes, washing machines, pumps, etc. produce waste current component, which can be stabilized. This technique can decrease electricity consumption from 10 to 30% - different depending on countries. Current modern devices for adjustment of power of target electrical appliances need a very fine measurement of an input voltage and current. In such cases remote monitoring of mentioned values can be a suitable solution. However, this solution contains some issues such as the need for pre-processing in remote sensor, or wireless transfer to central monitoring device, which need to be solved. Also the powering of such remote device is strictly limited. Sensor needs to be powered only by energy from the current sensor which results in the need for application of modern power source solutions. All of these findings result in a development of miniaturized solution based on 32b microcontroller unit with wireless communication unit and independent powering circuit. DOI: http://dx.doi.org/10.5755/j01.eee.19.6.4564

The Design and Construction of the MICE Spectrometer Solenoids

The purpose of the MICE spectrometer solenoid is to provide a uniform field for a scintillating fiber tracker. The uniform field is produced by a long center coil and two short end coils. Together, they produce 4T field with a uniformity of better than 1% over a detector region of 1000 mm long and 300 mm in diameter. Throughout most of the detector region, the field uniformity is better than 0.3%. In addition to the uniform field coils, we have two match coils. These two coils can be independently adjusted to match uniform field region to the focusing coil field. The coil package length is 2544 mm. We present the spectrometer solenoid cold mass design, the powering and quench protection circuits, and the cryogenic cooling system based on using three cryocoolers with re-condensers.

Toward Generic Fully IntegratedGate Driver Power Supplies

An original method to power supply gate drivers has been previously developed. This solution takes advantage of power switch commutations to recharge periodically a storage capacitor, and then to create the necessary floating power supply, useful for many power electronic converters. It is a low cost solution that can be integrated, but it presents some disadvantages: the storage capacitor must be adjusted with respect to the ON state time duration, and a permanent ON state operation is forbidden. Moreover, with the existing solution, a low frequency operation is problematic, because a large storage capacitor would be required. The proposed work presents here an improvement of the solution, in order to a allow flexible or even permanent ON state time duration operation of a self powered metal oxide semiconductor field effect transistor, using few additional elements. This solution exhibits unexpected and fairly good efficiency levels and presents a high ability for a simple implementation and monolithic integration. Added to these new features, smaller values for the storage capacitor can be used for this self powered driver power supply, allowing from very low up to high frequency operation and high duty cycle operation. This particular solution may simplify the integration of the storage capacitor, in the same substrate as the main switch and its self powering circuits.

Design and manufacture of the superconducting bus-bars for the LHC main magnets

The main magnets of the LHC are series-connected electrically in different powering circuits by means of superconducting bus-bars, carrying a maximum current of 13 kA. These superconducting bus-bars consist of a superconducting cable thermally and electrically coupled to a copper profile all along the length. The function of the copper profile is essentially to provide an alternative path for the current in case the superconducting cable loses its superconducting state and returns to normal state because of a transient disturbance or of a normal zone propagation coming from the neighboring magnets. When a superconducting bus-bar quenches to normal state its temperature must always stay below a safe values of about 100/spl deg/C while the copper is conducting. When a resistive transition is detected, the protection systems triggers the ramping down of the current from 13 000 A to 0. The ramp rate must not exceed a maximum value to avoid the transition of magnets series-connected in the circuit. This paper concerns the design and the manufacture of the high current superconducting bus-bars needed to interconnect the magnetic elements of the main dipoles, the main quadrupoles of the arcs and of the dispersion suppressors of the LHC.

Design and construction of a 1 m model of the low current superconducting quadrupole for the LHC insertions

About one hundred individually powered low current superconducting quadrupoles will be installed in the LHC insertions. One of the design requirements was to keep the excitation current of the magnet below 6 kA in view of minimizing the costs of the powering circuits. The design of the quadrupole is based on a 8.2 mm NbTi cable, and is designed for a nominal gradient of 200 T/m at 1.9 K. In this paper we present the design of the quadrupole and discuss the construction details of the 1 m single aperture model which has been recently completed.

Design of a 16 kbit superconducting latching/SFQ hybrid RAM

We have designed a 16 kbit superconducting latching/SFQ hybrid (SLASH) RAM, which enables high-frequency clock operation up to 10 GHz. The 16 kbit SLASH RAM consists of four 4 × 4 matrix arrays of 256 bit RAM blocks, block decoders, latching block drivers, latching block senses, impedance matched lines and the powering circuits. The 256 bit RAM block is composed of a 16 × 16 matrix array of vortex transitional memory cells, latching drivers, SFQ NOR decoders and latching sense circuits. We have also designed and implemented an SFQ NOR decoder that is composed of magnetically coupled multi-input OR gates and RSFQ inverters.

On Optimal Depth Threshold Circuits for Multiplication and Related Problems

Let $\widehat{LT}_d$ denote the class of functions that can be computed by depth-$d$ threshold circuits with polynomial size and polynomially bounded integer weights. Using the results in [M. Goldman, J. Hastad, and A. Razborov, in Proc. 7th Annual Conference on Structure in Complexity Theory], [M. Goldman and M. Karpinski, Constructing depth d+1 majority circuits that simulate depth d threshold circuits, unpublished] we show that multiple sum is in $\widehat{LT}_2$, and multiplication and division are in $\widehat{LT}_3$. Moreover, it follows from the lower-bound results in [A. Hajnal et al., IEEE Sympos. Foundations of Comput. Sci., 28 (1987), pp. 99--110], [T. Hofmeister and P. Pudlak, Forschungbericht Nr. 477 Uni Dortmund, 1992] that these threshold circuits are optimal in circuit depth. The authors also indicate that these techniques can be applied to construct polynomial-size depth-3 threshold circuits for powering and depth-4 threshold circuits for multiple product.