Power Supply Variations Research Articles

A high precision close-loop programmable CMOS delay generator for UWB and time domain RF applications

This article presents a novel programmable high precision delay generator with adjustable digital control for ultra-wideband and time-domain RF applications.Ring oscillator based phase locked loop (PLL) is embedded to achieve desired propagation delay in the delay cell against process, temperature, and power supply variations. A replica inverter delay line parallel to the PLL offers a separate delay path for input clock. Sub-nanosecond delay step with high accuracy can be obtained by shaping the input clock slope and keeping a careful matching between the replica delay line and the delay cell in PLL. The prototype of the delay generator is implemented on a 0.18-μm CMOS process. The measurement results show relative delay error of 0.8%. The circuit consumes 9.5 mA from a 1.8-V power supply. © 2010 Wiley Periodicals, Inc. Microwave Opt Technol Lett 53:390–392, 2011; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.25732

A Calibrated Phase and Amplitude Control System for a 1.9 GHz Phased-Array Transmitter Element

A system is proposed to allow the phase and amplitude of a signal to be accurately set and regulated over process and power supply variations. It uses a variable gain amplifier (VGA) in conjunction with the phase shifter to compensate for the variable losses of the phase shifter and simultaneously provide a means of adjusting the amplitude of the signal. The system has been fabricated in a 0.18 ?m CMOS process, and operates at 1.9 GHz. The phase can be set with 5 bits of control over a 240° range and the amplitude can be varied over a 20 dB range. The feedback loops reduce the variation in |S 21| across the phase control range from 12.1 to 0.4 dB. For a changing power supply voltage the feedback loops reduce the maximum phase deviation from 28° to 7° , and across different test chips the maximum standard deviation over the phase control range is reduced from 12° to 3°.

A Novel Adaptive Design Methodology for Minimum Leakage Power Considering PVT Variations on Nanoscale VLSI Systems

This paper proposes a novel design method to minimize the leakage power during standby mode using a novel adaptive supply voltage and body-bias voltage generating technique for nanoscale VLSI systems. The process, voltage, and temperature (PVT) variations are monitored and controlled independently by their own dedicated systems. The minimum level of <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> and the optimum body-bias voltage are generated for different temperature and process conditions adaptively using a lookup table method based on the PVT monitoring and controlling systems. The power supply variations is accurately compensated adaptively through the monitoring circuits based on the propagation delay change of the inverter chains. The subthreshold current as well as gate-tunneling and band-to-band-tunneling currents are monitored and minimized adaptively by the optimally generated body-bias voltage. The proposed design method reduces the leakage power at least by 500 times for ISCAS'85 benchmark circuits designed using 32-nm CMOS technology comparing to the case where the method is not applied.

A Current Mode, Parallel, Two-Rail Code Checker

A current mode, periodic outputs, parallel two-rail code (TRC) checker, suitable for the implementation of high fan-in embedded checkers, is presented. The new checker is characterised by high testability, high speed operation and low silicon area requirements. The circuit has been designed, for various fan-in values, in a 0.18 mum technology and electrical simulations have been carried out to validate its operation, considering process, power supply and temperature variations as well as variations of the electrical parameters.

CMOS RF mixer with digitally enhanced IIP2

A new method to enhance the IIP2 of a double-balanced Gilbert cell mixer through digital calibration is presented. The IIP2 calibration method consists of offset voltage cancellation in the switching pairs. The effectiveness of the method has been proven by calibrating a 0.18 mu m CMOS mixer at several combinations of worst-case mismatch conditions and corners. It has been found that the calibrated mixer can achieve its targeted IIP2 specification even at large process, temperature, and power supply variations.

Phase-Locked Loop with Leakage and Power/Ground Noise Compensation in 32nm Technology

This paper presents two novel compensation circuits for leakage current and power supply noise (PSN) in phase locked loop (PLL) using a nanometer CMOS technology. The leakage compensation circuit reduces the leakage current of the charge pump circuit and the PSN compensation circuit decreases the effect of power supply variation on the output frequency of VCO. The PLL design is based on a 32nm predictive CMOS technology and uses a 0.9 V power supply voltage. The simulation results show that the proposed PLL achieves 88% jitter reduction at 440 MHz output frequency compared to the PLL without leakage compensator and its output frequency drift is little to 20% power supply voltage variations. The PLL has an output frequency range of 40 M~725 MHz with a multipli-cation range of 1-1023, and the RMS and peak-to-peak jitter are 5psec and 42.7 psec, respectively.

Analysis of High-Performance Fast Feedthrough Logic Families in CMOS

This brief presents a new CMOS logic family using the feedthrough evaluation concept and analyzes its sensitivity against technology parameters for practical applications. The feedthrough logic (FTL) allows for a partial evaluation in a computational block before its input signals are valid, and does a quick final evaluation as soon as the inputs arrive. The FTL is well suited to arithmetic circuits where the critical path is made of a large cascade of inverting gates. Furthermore, FTL based circuits perform better in high fanout and high switching frequencies due to both lower delay and dynamic power consumption. Experimental results, for practical circuits, demonstrate that low-power FTL provides for smaller propagation time delay (4.1 times), lower energy consumption (35.6%), and similar combined delay, power consumption and active area product (0.7% worst), while providing lower sensitivity to power supply, temperature, capacitive load and process variations than the standard CMOS technologies.

A digitally controlled on-chip monotonic reference current generator with low LSB current for fast and accurate optical level monitoring

This paper describes a digitally controlled on-chip monotonic Reference Current Generator (RCG) with 8-bit resolution and a LSB (Least Significant Bit) current as low as 100 nA. It was designed as a building block of a generic DC-coupled Burst Mode Laser Diode Driver (BM-LDD) for GPON (Gigabit Passive Optical Network) applications and acts as an on-chip RCG with a settling time of 18 ns for fast and accurate optical level monitoring with guaranteed monotony. The proposed architecture of the on-chip RCG is based on an 8-bit segmented current-steering Digital-to-Analog Converter (IDAC) and a bandgap voltage reference. The (3 + 5) segmented architecture of the 8-bit IDAC is an optimum combination of a 3-bit MSBs (Most Significant Bits) unit-element sub-DAC and a 5-bit LSBs binary-weighted sub-DAC offering good DNL (Differential Nonlinearity) performance. The bandgap voltage reference deviates only 0.6% of the nominal value over temperature and power supply variations. A cascade current mirror with a super beta helper circuit is used to guarantee monotony and high accuracy. The linearity errors caused by systematic influences and random variations are reduced by the proposed 2-D double centroid symmetrical architecture. Experiments confirm a DNL of ±0.5 LSB for the proposed RCG. The tested performance of optical level monitoring and APC (Automatic Power Control) algorithm is compliant to ITU-T GPON standards. The design was realized in a 0.35 μm SiGe BiCMOS technology with 3.3 V power supply. The technology choice was made by heavy requirements of the innovative DC-coupled 1.25 Gbit/s BM-LDD chip. Although the proposed structure was designed as a building block for a BM-LDD chip, the design concept can be applied for developing other high linearity on-chip RCG for a wide junction temperature range (?40 to 110°C).

High performance low power CMOS dynamic logic for arithmetic circuits

This paper presents the design of high performance and low power arithmetic circuits using a new CMOS dynamic logic family, and analyzes its sensitivity against technology parameters for practical applications. The proposed dynamic logic family allows for a partial evaluation in a computational block before its input signals are valid, and quickly performs a final evaluation as soon as the inputs arrive. The proposed dynamic logic family is well suited to arithmetic circuits where the critical path is made of a large cascade of inverting gates. Furthermore, circuits based on the proposed concept perform better in high fanout and high switching frequencies due to both lower delay and dynamic power consumption. Experimental results, for practical circuits, demonstrate that low power feature of the propose dynamic logic provides for smaller propagation time delay (3.5 times), lower energy consumption (55%), and similar combined delay, power consumption and active area product (only 8% higher), while exhibiting lower sensitivity to power supply, temperature, capacitive load and process variations than the dynamic domino CMOS technologies.

A 32nm and 0.9V CMOS Phase-Locked Loop with Leakage Current and Power Supply Noise Compensation

This paper presents two novel compensation circuits for leakage current and power supply noise (PSN) in phase locked loop (PLL) using a nanometer CMOS technology. The leakage compensation circuit reduces the leakage current of the charge pump circuit which becomes more serious problem due to the thin gate oxide and small threshold voltage in nanometer CMOS technology and the PSN compensation circuit decreases the effect of power supply variation on the output frequency of VCO. The PLL design is based on a 32㎚ predictive CMOS technology and uses a 0.9V power supply voltage. The simulation results show that the proposed PLL achieves a 88% jitter reduction at 440㎒ output frequency compared to the PLL without leakage compensator and its output frequency drift is little to 20% power supply voltage variations. The PLL has an output frequency range of 40M~725㎒ with a multiplication range of 1-1023, and the RMS and peak-to-peak jitter are 5ps and 42.7ps, respectively.

High-performance CMOS variability in the 65-nm regime and beyond

Recent changes in CMOS device structures and materials motivated by impending atomistic and quantum-mechanical limitations have profoundly influenced the nature of delay and power variability. Variations in process, temperature, power supply, wear-out, and use history continue to strongly influence delay. The manner in which tolerance is specified and accommodated in high-performance design changes dramatically as CMOS technologies scale beyond a 90-nm minimum lithographic linewidth. In this paper, predominant contributors to variability in new CMOS devices are surveyed, and preferred approaches to mitigate their sources of variability are proposed. Process-, device-, and circuit-level responses to systematic and random components of tolerance are considered. Exploratory, novel structures emerging as evolutionary CMOS replacements are likely to change the nature of variability in the coming generations.

An accurate current source with on-chip self-calibration circuits for low-voltage current-mode differential drivers

An accurate CMOS current source for current-mode low-voltage differential transmitter drivers has been designed and fabricated. It is composed of binary weighted current mirrors with built-in self-calibration circuits. The proposed self-measurement and calibration circuits can calibrate upon the collective effects of different error contributors due to process, power supply, and temperature variations. The design has been fabricated in standard 0.35-/spl mu/m CMOS technology. Measurement results show that the differential output voltage can be self-calibrated to /spl plusmn/1% accuracy with 16% reference current variation, 60% power supply variation, or 13% load resistance variation, respectively.

General skew constrained clock network sizing based on sequential linear programming

We investigate the problem of clock network sizing subject to general skew constraints. A novel approach based on sequential linear programming is presented. The original nonlinear programming problem is transformed into a sequence of linear programs by taking the first-order Taylor's expansion of clock path delay with respect to buffer and/or wire widths. For each linear program, the sensitivities of clock path delay, with respect to buffer and/or wire widths, are efficiently updated by applying time-domain analysis to the clock network in a divide-and-conquer fashion. Our technique can take into account power supply and process variations. We demonstrate experimentally that the proposed technique is not only capable of optimizing effectively the skew and area of clock network, but also of providing more accurate delay and skew results compared to the traditional approaches.

Reliable study of digital IC circuits with margin voltage among variable DC power supply, electromagnetic interference and conducting wire antenna

This paper measures the margin voltage of a digital IC circuit in order to assess the deterioration of the margin voltage caused by variations in the DC power supply, electromagnetic interference (EMI), and the corresponding power induced in a conducting wire antenna (CWA). The present results confirm that these factors may influence the margin voltage to such an extent that the operation of the digital IC circuit may fail. This paper provides a theoretical analysis of the influence of these factors upon the margin voltage, and develops corresponding equations, which are then applied with appropriate parameter values to determine an optimal circuit operation. It is shown that the deteriorated margin voltage of the IC circuit is a function of the amplitude and frequency of the EMI source, and of the parasitic capacitance of the device, i.e. the greater the EMI amplitude and frequency, and the higher the capacitance of the device, the greater the likelihood that its operation will fail when subjected to a variable DC supply voltage, or to EMI and CWA effects. Furthermore, in the case of EMI, it is shown that an increased interference frequency will reduce the margin voltage of the device. Finally, it is noted that the smaller the input impedance of the IC device, the greater the influence of EMI is likely to be.

Design of a robust PWM power amplifier using approximate two‐degree‐of‐freedom digital integral‐type control only with voltage feedback

AbstractThere is a need for robust PWM power amplifiers whose transient response characteristics do not deteriorate in the presence of extensive load variation and/or direct‐current power‐supply voltage variation. In this paper, a methodology is proposed for designing a digital robust controller using only voltage feedback for PWM power amplifiers which can satisfy such demands. The controlled object (PWM power amplifier) is represented by a discrete‐time system with consideration of input dead‐time and the conversion of current feedback to voltage feedback. First, a model matching system using only voltage (output) feedback is created for this controlled object. Next, it is shown that an approximate two‐degree‐of‐freedom digital robust control system can be created by connecting the robust compensator obtained by approximating this model matching system. Furthermore, it is shown that a digital integral‐type controller using only voltage feedback is obtained by equivalent transformation. Methods for determining the parameters of the LC filter and the controller, and a sampling time which satisfies design specifications are shown. Finally, it is verified by simulation and experiment that all the given specifications are satisfied by the proposed digital controller and that the design method with consideration of input dead‐time is useful. © 2003 Wiley Periodicals, Inc. Electron Comm Jpn Pt 2, 86(6): 1–12, 2003; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/ecjb.10110

Clock and power gating with timing closure

Assuming that delay is linearly dependent on local power supply voltage, the authors show how to set up an analysis to determine the effect of power supply variations on delay. This analysis can drive the introduction of clock gating, an increasingly popular technique for reducing dynamic power dissipation.

Design of a robust PWM power amplifier using approximate two‐degree‐of‐freedom integral‐type control

AbstractA method is proposed for designing a robust controller for PWM power amplifiers, which are widely used as amplifiers and power supplies. The main technical requirements imposed on PWM power amplifiers are linearity in a wide frequency range and a well‐damped fast dynamic response in the presence of extensive load and DC power supply variations. Therefore, in order to satisfy the design specifications, namely, linearity in a wide frequency range and no overshoots during transients, an approximate two‐degree‐of‐freedom integral control structure is proposed and a design procedure for the robust controller is discussed. It is shown by some simulations and experiments that the designed controller shows especially good dynamic performance and effective disturbance rejection in the presence of external disturbances, that is, load and power‐supply variations. © 2003 Wiley Periodicals, Inc. Electr Eng Jpn, 144(1): 68–77, 2003; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/eej.10102

Reducing the Impact of False Alarms in Induction Motor Fault Diagnosis

Early detection and diagnosis of incipient faults is desirable for on-line condition assessment, product quality assurance, and improved operational efficiency of induction motors. At the same time, reducing the probability of false alarms increases the confidence of equipment owners in this new technology. In this paper, a model-based fault diagnosis system recently proposed by the authors for induction motors is experimentally compared for fault detection and false alarm performance with a more traditional signal-based motor fault estimator. In addition to the nameplate information required for the initial set-up, the proposed model-based fault diagnosis system uses measured motor terminal currents and voltages, and motor speed. The motor model embedded in the diagnosis system is empirically obtained using dynamic recurrent neural networks, and the resulting residuals are processed using wavelet packet decomposition. The effectiveness of the model-based diagnosis system in detecting the most widely encountered motor electrical and mechanical faults, while minimizing the impact of false alarms resulting from power supply and load variations, is demonstrated through extensive testing with staged motor faults. The model-based fault diagnosis system is scalable to motors of different power ratings and it has been successfully tested with fault data from 2.2kW,373kW, and 597kW induction motors.

2.5 Gbit∕s∕channel laser driver design for four-channel parallel optic transceiver using SiGe BiCMOS technology

A laser driver for a four-channel parallel fibre optic transceiver operating up to 2.5 Gbit/s is designed using a 0.35 /spl mu/m SiGe BiCMOS process. An 850 nm vertical cavity surface emitting laser diode array is used as a light source. The measurement was performed under the case temperature range 0-80/spl deg/C at 3.1 to 3.5 V power supply variations. Using a gigabit Ethernet filter, a 45% eye mask margin has been achieved at -4 dBm average optical power and 7 dB extinction ratio at 40/spl deg/C. The rise/fall time is less than 100 ps. The measured deterministic jitter is under 60 ps and the random jitter under 4 ps RMS.

Design of a Robust PWM Power Amplifier Using Approximate 2-Degree-of-Freedom Integral Type Control

A method is proposed for designing a robust controller for PWM power amplifiers, which are widely used as amplifiers themselves and power supplies. The main technical requirements imposed on PWM power amplifiers are linerarity in wide frequency range and well-damped fast dynamic response against extensive load and d. c. power supply variations. Therefore, in order to satisfy the design specifications-linearity in wide frequency range and no overshoots during the transients, an approximate 2-degree-of-freedom integral type control structure is proposed as well as a design procedure for the robust controller is discussed. It is clarified from some simulations and experiments that the designed controller shows highlighted good dynamic performances and effective disturbance rejection properties against external disturbances, i. e. load and power-supply variations.