Power Supply Rejection Performance Research Articles

A Fully Integrated High-Power-Supply-Rejection Linear Regulator With an Output-Supplied Voltage Reference

This study proposes an output capacitor-less linear regulator with high power supply rejection (PSR) for a wireless power transmission system. To achieve high PSR with a noisy input voltage, a fully integrated linear regulator with its reference circuit supplied by the output voltage is proposed. The proposed technique can isolate the reference circuit from the noisy $\text{V}_{IN}$ , thereby reducing the requirements of the conventional bulky low-pass filter loading the reference voltage node while achieving superior PSR performance. The regulator uses an N-type pass transistor and a dual-feedback structure to achieve wideband ripple-filtering and fast transient responses. The proposed regulator is compatible with typical biomedical implants requiring a 10mA load current at 1.1V output voltage while consuming a total quiescent current of $276~\mu $ A. A PSR performance was measured to be −48 and −56 dB against the $\text{V}_{IN}$ and charge pump at 10 MHz, respectively. The unity gain bandwidth (UGB) of the regulator was 291MHz. The proposed regulator was fabricated using commercial TSMC 0.18- $\mu \text{m}$ CMOS technology with an area of 0.1054 mm2 including the reference circuit.

A Sub-1 V Temperature-Insensitive-PSR Bandgap Reference with Complementary Loop Locking

This paper presents a novel low-voltage bandgap reference with improved power supply rejection (PSR). The proposed circuit adopts a complementary loop locking approach for stabilizing the drain-source voltages of the current mirrors, which gives rise to a boost of the PSR performance by more than 30[Formula: see text]dB over [Formula: see text]–110∘C and at 1-V supply. An analysis shows that the PSR of the proposed bandgap reference is typically characterized with its insensitivity to temperature variations. The circuit is designed with a commercial 0.18-[Formula: see text]m CMOS process. The experiment results of Monte Carlo simulation demonstrate that the average PSR with 1-V supply is [Formula: see text][Formula: see text]dB at DC and is [Formula: see text][Formula: see text]dB at 1[Formula: see text]kHz (attained under a room temperature condition of 27∘C). And the temperature coefficient of the DC-based PSR is about 0.83%/∘C at 1-V supply, significantly decreased by three–six folds compared to other conventional designs. The quiescent current consumed is only about 13.5[Formula: see text][Formula: see text]A.

0.18 mW/pole inverter‐based G m ‐C bandpass filter with automatic frequency tuning

A low-power Gm-C filter with the elliptic prototype targeting wireless application of the IEEE 802.15.4 (ZigBee) standard is presented. A modified inverter-based Gm cell is proposed to increase the current efficiency. Due to the tail current source, this Gm cell also shows better common-mode rejection and power supply rejection performance than traditional operational transconductance amplifier (OTA) structure. The filter is implemented in a 65 nm CMOS process. It achieves a figure of merit of 0.01 fJ with a power consumption of 0.18 mW/pole from a 1.2 V supply voltage. It provides stopband attenuation better than 40 dB, and an in-band IIP3 of 9 dBm. An automatic frequency tuning circuit based on sine-wave PLL method is introduced to compensate for the process variations. The centre frequency and bandwidth can be simultaneously tuned to satisfy the specifications. They are also stable over the process variations with only 2.3% deviation.

A Capacitor-less Low Dropout Regulator for Enhanced Power Supply Rejection

Various power supply noise sources in a system integrated circuit degrade the performance of a low dropout (LDO) regulator. In this paper, a capacitor-less low dropout regulator for enhanced power supply rejection is proposed to provide good power supply rejection (PSR) performance. The proposed scheme is implemented by an additional capacitor at a gate node of a pass transistor. Simulation results show that the PSR performance of the proposed LDO regulator depends on the capacitance value at the gate node of the pass transistor, that it can be maximized, and that it outperforms a conventional LDO regulator.

External Capacitor-Less Low Drop-Out Regulator With 25 dB Superior Power Supply Rejection in the 0.4–4 MHz Range

This paper presents design techniques for a high power supply rejection (PSR) low drop-out (LDO) regulator. A bulky external capacitor is avoided to make the LDO suitable for system-on-chip (SoC) applications while maintaining the capability to reduce high-frequency supply noise. The paths of the power supply noise to the LDO output are analyzed, and a power supply noise cancellation circuit is developed. The PSR performance is improved by using a replica circuit that tracks the main supply noise under process-voltage-temperature variations and all operating conditions. The effectiveness of the PSR enhancement technique is experimentally verified with an LDO that was fabricated in a 0.18 µm CMOS technology with a power supply of 1.8 V. The active core chip area is 0.14 mm², and the entire proposed LDO consumes 80 µA of quiescent current during operation mode and 55 µA of quiescent current in standby mode. It has a drop-out voltage of 200 mV when delivering 50 mA to the load. The measured PSR is better than –56 dB up to 4 MHz when delivering a current of 50 mA. Compared to a conventional uncompensated LDO, the proposed architecture presents a PSR improvement of 34 dB and 25 dB at 1 MHz and 4 MHz, respectively.

Class-D Amplifier Power Stage With PWM Feedback Loop

This paper presents a second-order pulsewidth modulation (PWM) feedback loop to improve power supply rejection (PSR) of any open-loop PWM class-D amplifiers (CDAs). PSR of the audio amplifier has always been a key parameter in mobile phone applications. In contrast to class-AB amplifiers, the poor PSR performance has always been the major drawback for CDAs with a half-bridge connected power stage. The proposed PWM feedback loop is fabricated using GLOBALFOUNDRIES' 0.18-μm CMOS process technology. The measured PSR is more than 80 dB and the measured total harmonic distortion is less than 0.04% with a 1-kHz input sinusoidal test tone.

Design of a CMOS Bandgap Reference with Low Temperature Coefficient and High Power Supply Rejection Performance

A high precision temperature compensated CMOS bandgap reference is presented. The proposed circuit employs current-mode architecture that improves the temperature stability of the output reference voltage as well as the power supply rejection when compared to the conventional voltage-mode bandgap referenc. Using only first order compensation the new architecture can generate an output reference voltage of 550mV with a peak-to-peak variation of 400μV over a wide temperature range from -25 o C to +100 o C which corresponds to a temperature coefficient of 5.8ppm/oC. The output reference voltage exhibits a variation of 2.4mV for supply voltage ranging from 1.6V to 2.0V at typical process corner. A differential cascaded three-stage operational amplifier is included in the bandgap circuit to improve the power supply rejection of the BGR. Simulation result shows that the power supply rejection ratio of the proposed circuit is 79dB from DC up to 1kHz of frequency. The proposed bandgap reference is implemented using UMC 0.18μm CMOS process and it occupies an active layout area of 0.14mm 2 .

A Low Quiescent Biased Regulator With High PSR Dedicated to Micropower Sensor Circuits

A new micropower high power-supply-rejection (PSR) regulator, on the basis of op-amp-less architectural design, is presented in this paper. The proposed regulator is based on the embodiment of the Brokaw bandgap regulator circuit in an additional feedback control loop so as to achieve high efficiency in terms of referenced PSR bandwidth per current. The measured PSR performance without any filtering capacitor for a 50-kΩ nominal resistive load at 1 kHz and 1 MHz are obtained as -76 and -43 dB, respectively. The regulator, making use of native driving devices to improve the headroom, supports the supply range from 2 to 3.3 V. The output voltage is close to 1.8 V, having an untrimmed temperature coefficient of 117 ppm/°C from - 40°C to 125°C while drawing the quiescent current of only 5.65 μA. The regulator occupies an area of 0.047 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> using current source model 1.8 V/3.3 V CMOS 0.18 μm triple-well process technology. The circuit is verified using the realistic BSIM3 models for simulation. Finally, the performance comparison with respect to the measured results of reported works, using technology normalized figure of merit, has validated that the proposed circuit technique offers good PSR results while having the advantages of low quiescent power, small size, and full integration without any off-chip capacitor. The proposed regulator is particularly suitable for micropower sensor circuits.