Power Semiconductor Research Articles

Capacitor Lifetime-Based Power Routing of ISOP-DAB Converter Within Comprehensive Constraint

Power routing (PR) provides a good choice to improve the modular converter reliability by equalizing the lifetime among multi-cells. The existing PR strategies just equalize the lifetime of power semiconductor devices by routing lighter loads for aged cells. However, the neglect of capacitor may mislead the multi-cell lifetime convergence. Besides, the light load allocation of the aging cell does not always mean the lifetime extension considering topologies and operation principles. Hence, this article proposed a capacitor lifetime-based PR for input-series-output-parallel connected dual active bridge converter. The proposed strategy can achieve the same accuracy as existing PR strategies, greatly reducing computation time and the complexity of the hardware circuit. Moreover, the nonmonotonic relationship between the damage growth rate and load of each cell is revealed and a damage growth rate constraint is developed to ensure the PR feasibility. Simulation is performed to verify the validity of the proposed strategy and constraints. Finally, a scaled down prototype has been developed to verify the PR feasibility and obtain the nonmonotonic relationship, verifying the necessity of proposed constraints. In addition, the effect of PR on the thermal stress and cumulative damage of capacitors is verified by a temperature test.

Transformerless High-Gain Three-Port Converter With Low Voltage Stress and Reduced Switches for Standalone PV Systems

This article proposes a high-gain transformerless three-port converter (TPC) for standalone photovoltaic (PV) systems. The TPC is designed and developed based on a dual-inductor high-gain two-port converter by utilizing one of the buffer capacitors to derive the third part for PV input. A hybrid pulse-frequency modulation scheme unified with a pulsewidth modulation control strategy is adopted, which realizes the maximum power point tracking control, load voltage regulation, and bidirectional energy flow at the battery port. The proposed TPC offers the unique advantages of high voltage gain, continuous battery port current, reduced power semiconductors, lower voltage stresses, common ground shared by all the ports, low-cost gate driver, and small size of the rear-end inductor. The working principle, steady-state characteristics, small-signal models, and the control method, including design conditions, are comprehensively analyzed. The correctness of the theoretical analysis is verified by developing a 300-W experimental prototype, which shows that the maximum efficiency is 97.7%.

Degradation Behavior of High Power Semiconductor Modules by Low-Temperature Sintering Technology

This paper presents a degradation behavior of high-power semiconductor modules, i.e., IGBT, with sintered silver by power cycle test and thermal cycle test. The electrical characteristics, such as on-state voltage drop, thermal resistance and leakage current, were studied. For power cycle test, the IGBT module still has an acceptable electrical performance after the 30 K power cycles. No noticeable changes can be found in the die-attach layer, while the DBC-attach layer begins to fail after 30 K power cycles. For the thermal cycling test, the electrical characteristics of the IGBT module were only tested within the first 300 cycles because the Al2O3 DBC substrate failed first before the failure of the bonding layers. Finally, finite element methods (FEM) were used to analyze thermal and mechanical stress distribution and failure mechanism of the bonding layers.

Evaluating On-State Voltage and Junction Temperature Monitoring Concepts for Wide-Bandgap Semiconductor Devices

Monitoring or estimating the junction temperature of power semiconductor devices is a requirement for degradation monitoring and predictive maintenance of power-electronic converters and usually achieved by online measurement of a temperature-sensitive electrical parameter (TSEP). Many TSEPs rely on switching transients and, thus, depend on the design of a switching cell, driving significant calibration efforts. Instead, utilizing the on-state voltage of a power semiconductor device as TSEP is attractive, as it only depends on the load current and the output characteristic of the device. This independence of the switching cell design enables on-state voltage monitoring circuits to be seamlessly integrated into products that are already mass produced. However, an effective on-state voltage monitoring circuit has to measure small on-state voltages accurately and fast while withstanding high off-state voltages. This article experimentally evaluates three candidate circuits that take on this challenge: a circuit derived from a Wheatstone bridge, a dynamically compensated voltage divider, and a circuit using an auxiliary MOSFET. PCBs are designed, featuring all three circuit concepts, and experiments are carried out to compare the candidate circuits in terms of dynamic performance and resolution. Finally, the potential for integration into commercial products is outlined, illustrated, and discussed.

Influence of Humidity on the Power Cycling Lifetime of SiC MOSFETs

Power cycling test (PCT) is widely used to accelerate power semiconductor device aging and assess its packaging reliability. Standard PCT only considers thermomechanical stress and neglects the effect of humidity from the environment. In this article, the power cycling lifetime of three groups [Group 1: devices under test (DUTs) preaged with 3600-h high-voltage high-humidity high-temperature reverse bias test (HV-H3TRB), Group 2: DUTs preaged with 3600-h high-temperature high-humidity storage, and Group 3: DUTs without preaging] is compared to explore the contribution of high humidity and high voltage. The results show that Groups 1 and 2 have a shorter lifetime, and the shape factor of Group 2 in Weibull analysis drops below 1, indicating that a sign of infant mortality and moisture is the root cause. After decapsulation, optical inspection, and scanning electron microscope (SEM), it is found that the bubbles form at edge termination, and the corrosion signs of moisture appear on the chip surface and bond wire in DUTs of Groups 1 and 2. This phenomenon is caused by the elements of C, O, and Si migration and deposition on the bond wire, which radically come from epoxy molding compound (EMC) and finally result in a shorter power cycling lifetime of discrete silicon carbide metal–oxide–semiconductor field-effect transistors (SiC MOSFETs).

Importance of the micro-lattice structure of selective laser melting processed Mo/Mo(x)S(x+1) composite: Corrosion studies on the electrochemical performance in aqueous solutions

Selective laser melting (SLM) based processing of Mo-based samples is challenging due to solidification cracking. We here demonstrate that the addition of 2 wt% MoS2 to the Mo feedstock markedly improves crack mitigation of SLM-processed Mo/MoS2/Mo2S3 composite micro-lattice structures (SLM-Mo/Mo(x)S(x+1)). Crack inhibition is suggested to be a result of Mo2S3 formation, decreased lattice strain (0.044%), and a decrease in accumulated residual stresses. The increased values of polarization resistance from 42.3 and 19.2 kΩ cm2 to 437 and 78.2 kΩ cm2, respectively verified the hindering effect of the composition on stress corrosion cracking (SCC) and surface oxidation cracking. However, an increased corrosion current density, from 1.22 to 10.2 μA/cm2, and cathodic Tafel constant, from 175 to 260.5 mV, confirmed the decreased polarization resistance and occurrence of different types of corrosion such as SCC and pitting. The strategy to add 2 wt% MoS2 to the Mo feedstock enables the fabrication of high-temperature micro-lattice structure components with improved corrosion resistance properties applicable in e.g., electronic, power semiconductor heat sinks, offshore-, aerospace-, defense-, or particularly novel sodium-ion energy storage applications.

An energy efficient modified passive power filter for power quality enhancement in electric drives

In most industrial applications, AC drives are used. These drives require power electronic modules to convert AC to DC and also DC to AC. The power modules used for power conversion consist of power semiconductor switches. There is distortion in the voltage and current obtained from the power modules due to non-linear behaviors of semiconductor switches. To reduce the distortion in the input current, inductors are used along with the line impedance. A high value of inductance is required to maintain the percentage of THD within limits set by the latest standards. Along with the increased size and cost, it also reduces the power factor and output DC voltage at higher loads. The use of a passive power filter (PPF) is the conventional method followed for the reduction of percentage THD and promotion of the power factor. PPFs comprise passive elements such as the resistor, inductor, and capacitor. These passive elements are connected at the point of common coupling (PCC) in shunt to compensate for the harmonics present in the input current. In this study, a modified multi-tuned passive filter is considered to reduce the source current harmonics. A bridge rectifier with resistive load, three-phase induction motor drive, and linear resistive–inductive load is connected at the point of common coupling to analyze the harmonics present in the source current, and also unbalanced created in one phase. To achieve proper selection of the resistance value for the passive filter, the class topper optimization technique is used. To validate the simulation results obtained for the multi-tuned passive filter, the hardware is implemented with a three-phase AC induction motor drive load, in which the speed of the motor is controlled with voltage by a frequency control algorithm using an FPGA controller; The 50% THD is reduced by using the fifth-order filter alone, 75% by combining the fifth- and seventh-order filters, 85% by combining the 5th-, 7th-, 11th-, 13th-, and higher-order filters, and 90% for varying loads. For single-phase AC induction motor load, THD % is reduced to 4%, and for three-phase AC induction motor drive, THD % is reduced to 10% with the same value of the filter.

Survey of 99.9% Class EfficiencyDC‐ACPower Conversion and Technical Issues

This study provides a survey overview of the literatures with the goal of maximizing the efficiency of DC‐AC power conversion from an engineering science perspective. With the advent of wide band gap power semiconductors, the published literature on realizing high efficiency DC‐AC converters has increased. Therefore, a literature survey of high‐efficiency DC‐AC inverters was first conducted. We demonstrated the importance of the measurement accuracy in measuring high efficiency losses, and then presented the literature on new measurement methods, as well as examples of analysis of the breakdown of these losses. Furthermore, we reviewed the literature on high‐efficiency inverters. We presented measurement data (99.83%) on an inverter with a high efficiency energy conversion system circuit topology using Silicon Carbide (SiC) and Gallium Nitride (GaN) devices to demonstrate how the procedure was used to achieve loss minimization. We summarized the challenges hindering high efficiency. © 2022 Institute of Electrical Engineers of Japan. Published by Wiley Periodicals LLC.

Design and fabrication of an interleaved high step‐up DC–DC converter with soft‐switching capability to implement in renewable energy systems

AbstractThis paper presents a soft‐switching non‐isolated interleaved high step‐up topology to implement in renewable energy systems. By using low number of power electronic devices and incorporation with the coupled inductors (CIs) and built‐in transformer (BIT), simultaneously, mixed with a voltage multiplier cell (VMC), an ultra‐large gain can be obtained. In addition, the interlevead structure in the input side causes to diminish the input current ripple. Moreover, the automatic current sharing is another characteristic of the proposed converter. The voltage stresses across power semiconductors are decreased by increasing the turns ratio of the implemented CIs and BIT and also reverse recovery losses are attenuated which improves the efficiency. Furthermore, zero‐current‐switching (ZCS) condition for diodes is achieved at turn off instant, due to the leakage inductances of the magnetic means. Also, power MOSFETs are switched with zero‐voltage‐switching (ZVS) performance by adding active clamp. A 600‐W experimental prototype with 24‐V input to 400‐V output voltage at a switching frequency of 100 kHz is built and tested to examine the merits of the proposed topology

Research of Static and Dynamic Properties of Power Semiconductor Diodes at Low and Cryogenic Temperatures

Systems with high-temperature superconductors (HTSC) impose new requirements on power conversions, since the main part of the losses in such systems is induced in the semiconductors of the converters. Within the framework of this study, the possibility of improving the static and dynamic characteristics of power semiconductor diodes using cryogenic cooling was confirmed; in some cases, a loss reduction of up to 30% was achieved.

Failure quantitative assessment approach to MOSFET power device by detecting parasitic parameters

With the emerging wide bandgap (WBG) semiconductor development, the increasing power density and efficiency of power electronic converters may cause more switching oscillation, electromagnetic interference noise, and additional power loss, further increasing the probability of device failure. Therefore, determining and quantifying the failure of a metal-oxide-semiconductor-field-effect transistor (MOSFET), which assembled using WBG semiconductor in some applications, is crucial to improving the reliability of a power converter. This study proposes a novel failure quantitative assessment approach based on MOSFET parasitic parameters. According to the two-port network theory, MOSFET is equivalent to some second-order RLC circuits composed of independent inductances, capacitances, and resistances in series. Then, the frequency-domain impedance associated with the physical failure of MOSFET is identified through frequency domain reflectometry. Accelerated aging and bond wires cut-off experiments are employed to obtain various quality states of the MOSFET device. Result shows that the MOSFET quality level and its number of bond wire lift-offs can be quantified effectively. Drain-to-source on-resistance (RDS(on)) that normally represents the MOSFET quality shows a positive linear function relationship on drain-to-source parasitic resistance (RD + RS) during the quality degradation proceeding. This finding matches with the correlation established between RDS (on) and RD + RS in theory. Meanwhile, source parasitic inductance (LS) increases with the severity of bond wires faults, and even the slight fault shows a high sensitivity. The proposed approach would be an effective quality screening technology for power semiconductor devices without power on treatment, which can effectively avoid the impact of junction temperature and test conditions (current and voltage) on test results, and does not need to design additional test circuits. The test frequency range we used in this approach was 10–300 MHz, which to some extent is suitable for providing an on-line quality monitoring technology for high-frequency WBG power devices manufacturing.

(Invited) Deep Level Defects in AlN Studied By UV-Visible Spectroscopy

The ultrawide-bandgap (UWBG) AlGaN alloy system is emerging as a promising material for next generation power semiconductor devices. The increase in bandgap as the alloy composition is varied from the binary endpoints GaN to AlN leads to an increase in the critical electric field, which is a key parameter determining the performance of power semiconductor devices. As development of GaN and SiC materials for high-frequency and high-power devices reaches a state of maturity, pursuit of improved device performance is generating interest in UWBG materials with larger bandgaps. High Al composition AlGaN alloys, in addition to offering increased critical electric fields, offer prospects for improved device performance in high temperature operation. Fundamental challenges to the development of AlGaN-based devices, such as controllable doping, electrical contacts, and effective passivation, remain, but a variety of power devices have already been demonstrated (1-3).Point defects strongly affect the material properties of semiconductors, with important consequences for device performance. In traditional semiconductors, such as Si, point defects have been studied extensively, and point defect engineering methods have been developed to enhance device performance. However, the properties of point defects in UWBG materials are not as well understood. Point defects may be introduced during device growth, fabrication, and operation. On the one hand, intentionally introduced impurities (dopants) are critical to the control of electrical transport, while on the other hand, unintentionally introduced impurities may act deleteriously as carrier traps or recombination centers. In AlGaN, compensation by deep level, native point defects or unintentionally incorporated impurities limits achievable free carrier concentrations in electronic devices, while defects and their complexes affect the optical properties in optoelectronic devices. Since point defects exert such a strong influence on material properties, and are often responsible for device degradation, knowledge of their formation mechanisms and material effects are essential to develop strategies for the required control of point defect concentrations (4).In this work, we studied the optical signatures of deep level defects in single crystal AlN substrates. AlN possesses a high thermal conductivity and a close lattice match to high Al composition alloys, which make it an excellent substrate choice for growth of AlGaN-based power electronic and optoelectronic devices. High-quality, 2-inch diameter AlN substrates with average threading dislocation densities below 103 cm-2 were recently demonstrated (5). However, high optical absorption in the ultraviolet-C (UV-C) region was observed in AlN substrates grown by physical vapor transport (PVT), due to a deep level absorption band related to the carbon impurity. This absorption band negatively impacts the efficiency of UV-C optoelectronic devices that require light propagation through the substrate. In order to reduce the unwanted UV-C absorption, we studied the optical properties of double-side polished, 2-inch, c-plane AlN substrates by ultraviolet-visible (UV-Vis) spectroscopy and developed strategies for point defect control. Spatially uniform absorption coefficients below 30 cm-1 at 265 nm were demonstrated across 2-inch substrates (6). In this talk, UV-Vis absorption, photoluminescence (PL) emission, and PL excitation spectra will be presented and correlated with measured impurity concentrations from secondary ion mass spectrometry (SIMS) data, in order to identify deep level defects in AlN. Finally, the mechanisms for reduction of UV-C absorption in PVT AlN will be discussed.References R. J. Kaplar, A. A. Allerman, A. M. Armstrong, M. H. Crawford, J. R. Dickerson, A. J. Fischer, A. G. Baca, and E. A. Douglas, ECS J. Sol. State Sci. and Technol. 6(2), Q3061 (2017).P. H. Carey IV, F. Ren, A. G. Baca, B. A. Klein, A. A. Allerman, A. M. Armstrong, E. A. Douglas, R. J. Kaplar, P. G. Kotula, and S. J. Pearton, IEEE Trans. Semicond. Manuf. 32(4), 473 (2019).A. G. Baca, A. M. Armstrong, B. A. Klein, A. A. Allerman, E. A. Douglas, and R. J. Kaplar, J. Vac. Sci. Technol. A 38, 20803 (2020).S. Washiyama, P. Reddy, B. Sarkar, M. H. Breckenridge, Q. Guo, P. Bagheri, A. Klump, R. Kirste, J. Tweedie, S. Mita, Z. Sitar, and R. Collazo, J. Appl. Phys. 127, 105702 (2020).R. Dalmau, J. Britt, H. Fang, B. Raghothamachar, M. Dudley, and R. Schlesser, Mater Sci. Forum 1004, 63 (2020).R. Dalmau, S. Kirby, J. Britt, and R. Schlesser, ECS Trans. 104(7), 49 (2021).

(Invited) Recent Progress in Wide-Bandgap Semiconductor Devices for a More Electric Future

Wide-bandgap (WBG) semiconductors, with their excellent electrical properties, offer breakthrough performance in power electronics enabling low losses, high switching frequencies, and high temperature operation. WBG semiconductors are likely candidates to replace silicon-based semiconductors in the near future seeing as Silicon is fast approaching its performance limits for high power requirements. Wide-bandgap power semiconductor devices offer breakthrough circuit performance enabling low losses, high switching frequencies, and high temperature operation which will allow for enormous energy efficiency gains in a wide range of potential applications. In the past ten years, the U.S. Department of Energy’s Advanced Research Project Agency - Energy (ARPA-E), which was established to fund creative, out-of-the-box, transformational energy technologies that are too early for private-sector investment, has invested in WBG semiconductors including material and device-centric programs along with application specific programs targeting the barriers to widespread adoption in power electronics. Under these ARPA-E programs, medium voltage (10-20kV) WBG device development has commenced to push the voltage boundaries of the devices including the development of WBG super-junction devices. Light triggered photoconductive WBG devices are also being investigated for MV applications. The WBG MV devices will enable MVDC grid distribution applicable to markets including electrified transportation, renewable interconnections, and offshore oil, gas, and wind production. Other WBG device ideas are also being explored under ARPA-E programs including WBG integrated circuits and neutron detectors. The progress and challenges of the WBG devices being developed under ARPA-E programs will be reviewed along with thoughts on the future trends of WBG device development.

(Invited) Advances in High Power, High Voltage, Reliable GaN Products for Multi Kilo-Watt Power Conversion Applications.

Gallium Nitride has been proven to be a superior material system for high performance, reliable, high power transistors enabling high efficiency in power conversion applications [1,2]. In this paper we highlight some recent advances in GaN technology which expand the capabilities and applications of GaN power switches.Transphorm, Inc, is a pioneer and leader in GaN power electronics with a wide product portfolio of products spanning <100W to >10kW applications with JEDEC and AEC-Q101 qualified products including qualified 650V and 900V products (Fig. 1), as well as demonstrated 1200V devices in development. Transphorm’s vertical integration allows for control over device design, GaN epitaxial growth, and device fabrication resulting in industry leading performance and reliability.Transphorm’s breadth of volume production applications from 45 W through 10 kW is in part due to its impressive Failure in Time (FIT) rate of < 0.3 failures per billion hours is based on Field Reliability Data collected over 40 billion hours.[3]Transphorm’s normally-off devices are built by combining a state-of-the-art high voltage (HV) GaN HEMT with a low voltage (LV) Silicon MOSFET into a cascode GaN FET configuration to offer superior reliability, performance, and ease of use. The LV Si MOSFET features low gate charge and high threshold voltage which makes for a very easy to drive switch with a large gate voltage drive margin and the HV GaN HEMT offers high performance due to the superior material and transport properties of GaN combining the best of both materials.The latest GenV 15 mΩ 650V SuperGaN® FET (TP65H015G5WS) is the lowest Ron packaged GaN FET in the market enabling >10kW output powers with a single switch [4]. Inductive switching waveforms in a half-bridge at 400 V/65 A for the SuperGaN FET and SiC MOSFET were compared (Fig. 2) and the GaN device delivered current and voltage switching speeds of 4 kA/μs and 60 kV/μs which is about 2x faster than that of the SiC MOSFET, resulting in a 50% reduction in switching loss.To assess the performance of the SuperGaN FET vs similarly rated SiC MOSFETs and SiC JFETs, the devices were configured into a 240V:400V boost converter operating at 70kHz (Fig. 3). The GaN FET based boost converter was able to operate up to 12kW of output power with a maximum junction temperature of just 139 oC while the SIC MOSFET and JFET boost converters were limited 11kW and 9.2kW respectively due to junction temperature reaching 165oC. At 9.2Wk output power, the SuperGaN FET power loss was 38% and 21% lower than the loss in the SiC JFET and SiC MOSFET respectively. This combination of lower temperature and higher output power demonstrates the importance of the high efficiency of the SuperGaN FET.The unparalleled efficiency of Transphorm’s SuperGaN FETs has enabled to the development of unique products such as a 3KVA datacenter UPS released by and industry leading supplier, which is the smallest, lightest, and most powerful 3KA datacenter UPS on the market with 93.3% peak efficiency and 2.5x higher power density which enabled the form factor to shrink form a 2U to 1U enclosure.Until recently, commercial GaN power electronic devices have only available up to 650V with Transphorm’s qualified 900V GaN FET (TP90H050WS) device being the exception. We have recently announced a breakthrough in GaN technology with the demonstration of a 1200V, 70mΩ lateral GaN FET in a TO-247 packageThe 1200V GaN FET achieved > 99% peak efficiency in a 450V:900V synchronous boost converter operating at 50kHz which is similar to the peak efficiency of our 650V Gen IV and Gen V products. Additionally, the 1200V GaN FET achieved higher efficiency than a similarly rated state-of-the-art 1200V SIC MOSFET in a 900V:450V buck converter at 100kHz and 5.5kW (Fig 4) demonstrating GaN can excel in 1200V applications [5].[1] Y.F. Wu, J. Gritters, L. Shen, R.P. Smith, J. McKay, R. Barr, R. Birkhahn, “Performance and robustness of first generation 600-V GaN-on-Si power transistors”, The 1st IEEE Workshop on Wide Bandgap Power Devices and Applications, 6-10, Oct, 2013.[2] Parikh, Y.F. Wu, L.K. Shen, "Commercialization of High 600V GaN-on-Silicon Power Devices", Materials Science Forum, Vols. 778-780, pp. 1174-1179, October 2014. [3] https://www.transphormusa.com/en/gan-technology/#quality-reliability [4] C. J. Neufeld, Y.-F. Wu, S. Wienecke, R.P. Smith, Y. Huang, M. Kamiyama, J. Ikeda, T. Hosoda,B. Swenson and R. Birkhahn, “650V/780A GaN Power HEMT Enabling 10kW-Class High-efficiency Power Conversion”, IEEE 8th Workshop on Wide Bandgap Power Devices and Applications, 7-11 Nov. 2021.[5] Gupta, et al. IEEE International Symposium on Power Semiconductor Devices 2022 (accepted for publication) Figure 1

Strain Analysis of High Energy Implanted 4H-SiC Epiwafer By Synchrotron X-Ray Plane Wave Topography

Silicon Carbide (SiC) is a promising wide bandgap semiconductor for power devices. Due to excellent properties of SiC, such as wide band gap, high break down voltage and thermal stability, SiC devices are able to be operated under harsh environment, such as high temperature, high voltage and high frequency environment [1]. 4H-SiC high voltage devices are highly sought for applications, such as hybrid vehicles, shipboard and power grid systems, and high-speed trains. Usually, such medium or high voltage devices are fabricated on 4H-SiC wafers with thick epilayers that will increase the resistance of the device specially at high temperatures. Deep implanted SiC superjunction devices have the potential to replace planar devices for medium voltage applications [2] However, forming deep implanted pillars into thick epilayers is quite challenging. An optimized solution of selective area doping is utilizing multi-steps high energy ion implantation system. Such a system has been developed at the Tandem Van de Graaff accelerator facility at Brookhaven National Laboratory with the capability of multi-steps high energy implantation at energies up to 150 MeV [3]. By employing such a system, medium voltage charge balance devices and 2 kV superjunction structure PIN diode have been demonstrated [4-5]. Implantation employing high energy ions can create lattice strain in the epilayer by displacing the host atoms. Therefore, characterization of strain in as-implanted epilayer is critical to understand the nature of damage introduced by the high energy implantation.Here, we employ synchrotron X-ray plane wave topography (SXPWT), where X-rays with energy of 8 keV is initially monochromatized by double crystal Si (111) monochromator followed by tuning with an asymmetric Si (331) beam conditioner. The effective width of the resultant X-ray beam is lowered to 0.5” due to the asymmetric factor of the beam conditioner [6]. Therefore, the angular resolution of SXPWT is vastly enhanced, enabling miniscule distortions in the lattice to be detected.The diffraction intensity profile from a 4H-SiC epiwafer implanted with Al ions to (concentration) using this effectively plane wave X-ray beam is shown in Fig. 1. Two high intensity peaks and weak intensity fringes in between, with an angular separation of only 2ʹʹ can be observed. This illustrates non-uniform strain in the implanted epilayer. Intensity profile of peaks and fringes is extracted from the topograph then fitted with commercial Rocking-curve Analysis by Dynamical Simulation (RADS) software developed by Bede to obtain the strain profile. The fitted curve and strain profile are shown in Fig.2. The strain profile will be analyzed and compared with doping profile obtained by Secondary Ion Mass Spectrometry (SIMS).[1] J. Guo, Y. Yang, B. Raghothamachar, T. Kim, M. Dudley, J. Kim, J. Cryst. Growth[2] L. C. Yu and K. Sheng, Solid State Electron., vol. 50, no. 6, pp. 1062-1072, 2006.[3] P. Thieberger, C. Carlson, D. Steski, R. Ghandi, A. Bolotnikov, D. Lilienfeld, P. Losee, Nucl. Instrum. Methods Phys. Res. B: Beam Interact. Mater. At.[4] R. Ghandi, C. Hitchcock, S. Kennerly, ECS Transactions 104, 67 (2021)[5] R. Ghandi, A. Bolotnikov, S. Kennerly, C. Hitchcock, P.-m. Tang, T.P. Chow, 2020 32nd International Symposium on Power Semiconductor Devices and ICs (ISPSD), IEEE, 2020, pp. 126-129.[6] H. Peng, Z. Chen, Y. Liu, B. Raghothamachar, X. Huang, L. Assoufid and M. Dudley, J. Appl. Crystallogr. (accepted) Figure 1

Design and Analysis of Front Side Modular Multilevel Converter for Smart Transformer in 15 kV Arba Minch Distribution Network Using Diverse Controllers and Multicarrier Modulation

This paper presents design and analysis of a bidirectional medium voltage (MV) front-side converter of smart transformer (ST) for Arba Minch Town distribution system. A modular multilevel converter (MMC) configuration is used in the MV side of the ST. The grid side MV is 15 kV RMS line value and the desired MVDC voltage is 24.5 kV for ensuring bidirectional operation of the converter in the time of grid outage. A half bridge semiconductor power module is used to model the front-side MMC. Based on the MV DC voltage requirement, the number of submodules per phase leg is designed to be four (four in the upper arm and four in the lower arm). Multicarrier modulation techniques such as phase-shifted PWM and level-shifted PWM are used to generate gate signals. The model is developed in MATLAB/Simulink, and its performance with respect to input side voltage harmonics, current harmonics, and output DC voltage value has been tested by carrying out several case studies under different controllers such as proportional integrator(PI), fuzzy inference system (FIS), and adaptive neuro fuzzy inference system (ANFIS) for obtaining reference signal for modulation. Level-shifted PWM is used with PI, FIS, and ANFIS, whereas phase-shifted PWM with a technique of introducing DC bias is used with PI controller alone. From the simulation results, it has been observed that better power system current quality of FS-MMC is obtained for PS-PWM (2.16%) than level-shifted PWM (5.22%). Use of FIS and ANFIS with level shift PWM method slightly brings down the current THD values to 2.98% and 2.72%, respectively (decrease by 2.5%). Also, a maximum output DC voltage of 24650 V is obtained for ANFIS with level shift PWM as compared to values obtained by PI with level shift PWM and PI with phase shift PWM.

Large‐scale plasma grafts voltage stabilizer on hexagonal boron nitride for improving electrical insulation and thermal conductivity of epoxy composite

AbstractBetter electrical insulation and thermal management are both urgently required in integrated power semiconductors. Electrical insulation epoxy encapsulation suffers from poor heat conduction, which has increasingly become a bottleneck of power semiconductors integration. Although incorporating high thermal conductivity ceramics, such as hexagonal boron nitride (hBN), aluminium nitride etc. into epoxy promotes the thermal conductivity, the eco‐friendly scalable fabrication of these composites with sufficient electrical breakdown strength remains a formidable challenge. Suitable voltage stabilizers are known to provide additional benefits to breakdown strength. Herein, a high‐throughput approach combining plasma with roll‐to‐roll was developed. The voltage stabilizer (acetophenone) was grafted on interfaces between hBN and epoxy matrix through plasma. The high‐energy electrons are consumed by the grafted interface, which leads to the significant suppression of partial discharge in Epoxy/hBN. Meanwhile, interfacial phonon scattering is repaired by grafting. Therefore, the epoxy composite concurrently exhibits improved breakdown strength (by 27.4%) and thermal conductivity (by 142.9%) at about 11.9 wt.% filler content, outperforming the pure epoxy. Consequently, a promising modification strategy for mass production is provided for the encapsulation materials in various high‐power‐density semiconductor devices.

A Review of Open-Circuit Switch Fault Diagnostic Methods for Neutral Point Clamped Inverter

Due to numerous advantages, a neutral point clamped (NPC) inverter is a preferred choice for high-power applications and renewable technology. The reliability of the NPC inverter is a major concerning factor during the assessment of system performance as power semiconductor switches are vulnerable to abnormal conditions. Open-circuit (OC) switch faults are not as dangerous as short circuit (SC) faults but eventually have enough potential to cause cascaded failure to other components in the system and thus need to be supervised carefully. The OC faults result in a distortion of voltage and current signals in the NPC converter. Based on these signals, over the past few years, many efforts have been made to identify and localize the OC switch fault to the switch level in the NPC topology. In this paper, a review of different OC switch fault diagnostic methods is provided. Starting from the NPC inverter operation under healthy and faulty conditions, the various possible and unavailable switching states along with the deviation in pole voltage under different switch fault conditions is discussed. Then, based on the approach used for system-based fault detection, the OC fault detection methods are classified. The various OC methods are further discussed on the basis of signal, i.e., current, voltage or a combination of both signals used as a signature for fault detection. Emphasis is given to the principle involved, diagnostic variables utilized, the implementation approach and the diagnostic time required. Finally, the approaches are tabulated so as to provide a quick reference for NPC fault diagnostics.

Condition Monitoring of Power Electronic Systems Through Data Analysis of Measurement Signals and Control Output Variables

A major disadvantage of existing condition monitoring methods is the need for additional sensors and measuring equipment. In this work, this disadvantage is eliminated by completely avoiding additional hardware. Instead, software-based methods from the field of machine learning are used. Therefore, measurement signals and control output variables are utilized, which are acquired and processed in any power electronic system for the purpose of converter control. The publication focuses on two main converter components: power semiconductors and dc-link capacitor. For each component, the aging mechanisms that have been studied in the literature are explained. Based on the aging mechanisms, the degradation indicators are identified. Then, a converter model is built that allows the variation of degradation indicators in order to analyze their effects on the available dataset. These findings form the basis for mathematical models, which detects future failure mechanisms of this type during converter operation. The test setup must offer the possibility of generating reproducible failure cases in various components with the aid of additional failure equipment. Finally, failure mechanisms are intentionally introduced at the test bench in order to validate the methodology of the developed approach.

Non-isolated high voltage gain DC to DC converter based on the diode a capacitor switches

&lt;p&gt;&lt;span&gt;Many researchers have put great endeavor to develop DC converter’s designs, into studying how to increase voltage gain with low switching stress and low ripple current. This paper has proposed a circuit to boost the voltage with a high gain conversion ratio. It is a combined adverse parallel two boost conversion. Two inductors are connected on both sides of the input source to decrease the current-ripple of the input current and output sides utilizing the interleaving technique. The proposed converter integrated with an active-network circuit is based on multiplier cells and two output capacitors. The voltage gain and voltage stresses across power semiconductors have been determined using a steady-state analysis. In addition, the input current- ripple and output voltage-ripple are analysis have been reported. This converter's inductors operate in a continuous conduction mode (CCM). The designed converter is capable of achieving significant voltage gain while maintaining a low duty ratio. Furthermore, the active switches and output diodes are under low voltage stress. As a result, low voltage components can be used to decrease conduction loss and cost. Finally, this converter was simulated in MATLAB/Simulink software to verify the theoretical calculations.&lt;/span&gt;&lt;/p&gt;