LDMOS RF Power Research Articles

Analysis of impact ionization on RF power LDMOS reliability under RF life test in radar system

This paper focuses on correlation between the electrical parameter shifts and the failure phenomena that appeared after pulsed RF life tests applied to RF power LDMOS transistor (Radio Frequency Laterally Diffused-Metal–Oxide–Semiconductor). The results of the test bench (radar circuit) are measured in real time. The failure rate is more significant at low temperatures after the aging life test. The electrical performances are shifted, notably, IGS, VTH, GM, RDSON, CRSS, gain, and S-parameter S21. A 3D physical simulation (SILVACO-TCAD) is used to highlight the phenomena linked to the characteristic's degradation. The impact ionization induces physical degradations in the study of transistors, which are manifested by a variation in their electrical performance. It showed that the located failure zone is due to the device's shifted characteristics, which are deeply correlated with the structure area. The goal of the paper is to prove the failure mechanism through the characteristics evaluation origin, that is started by the carrier generation, because of the impact ionization phenomenon. The demonstration is based on the physical simulations are conducted at RF power NLDMOS. The outcomes show that the mechanism is due to the augmented carrier injection into the advanced silicon dioxide layer (SiO2) or/and in the Si/SiO2 interface state. The consistency between the physical simulations and experimental results emphasizes the theoretical analysis performed in this work.

An analytical model for the drain—source breakdown voltage of RF LDMOS power transistors with a Faraday shield

An analytical model for the drain—source breakdown voltage of an RF LDMOS power transistor with a Faraday shield is derived on the basis of the solution of the 2D Poisson equation in a p-type epitaxial layer, as well as an n-type drift region by means of parabolic approximation of electrostatic potential. The model captures the influence of the p-type epitaxial layer doping concentration on the breakdown voltage, compared with the previously reported model, as well as the effect of the other device parameters. The analytical model is validated by comparing with a numerical device simulation and the measured characteristics of LDMOS transistors. Based on the model, optimization of LDMOS device parameters to achieve proper trade-off between the breakdown voltage and other characteristic parameters such as on-resistance and feedback capacitance is analyzed.

Nonlinear modeling and analysis of a Doherty power amplifier driven by non-constant envelope signals

A circuit-level CAD method based on circuit envelope (CE) simulation is presented to analyze the nonlinear behavior of Doherty power amplifiers (DPAs) in LDMOS technology, when driven by non-constant envelope signals. In this paper, a general nonlinear model has been extracted for an RF LDMOS power transistor. Then, a complete CE analysis is applied to a designed DPA using the extracted model at 3.5 GHz. To solve the CE equation at specific envelope samples, analytic expressions are developed for the Jacobian matrix and an effective method for quick calculation is suggested. Employing this nonlinear analysis gives insight for optimum design of DPAs and provides an accurate tool to precisely model the nonlinearity of the amplifier in order to predict its distortion effects in modern communication systems.

Steady State Temperature Study on RF LDMOS with Structure Modification

This paper is devoted to temperature analysis on power RF LDMOS with different feature parameters of die thickness, pitch S length and finger width. The significance of these three parameters is determined from temperature comparison obtained by 3D Silvaco-Atlas device simulator. The first three simulations focus on temperature variation with the three factors at different output power density respectively. The results indicate that both the thinner die thickness and the broaden pitch S length have distinct advantages over the shorter finger width. The device, at the same time, exhibits higher temperature at a larger output power density. Simulations are further carried out on structure with combination of different pitch s length and die thickness at a large 1W/mm output power density and the temperature reduction reaches as high as 55%.

Evaluation of hot-electron effects on critical parameter drifts in power RF LDMOS transistors

This paper presents a synthesis of hot-electron effects on power RF LDMOS performances, after accelerated ageing tests with electrical and/or thermal stress. Which can modify and degrade transistor physical and electrical behaviour. The effects of reliability degradation mechanisms on the S-parameters and in turn on static and dynamic parameters are pointed out. The RF performance degradation is explained primarily by the transconductance and miller capacitance shifts. To reach a better understanding of the physical mechanisms of parameter’s shift after ageing tests, a numerical device model (2D, Silvaco-Atlas) was used to confirm degradation phenomena. Finally, the paper demonstrates that N-LDMOS degradation is linked to hot carriers generated interface states (traps) and trapped electrons, which results in a build up of negative charge at Si/SiO 2 interface. More interface states are created due to a located maximum impact ionization rate at the gate edge.

Study of hot-carrier effects on power RF LDMOS device reliability

This paper reports comparative reliability of the hot carrier induced electrical performance degradation in power RF LDMOS transistors after RF life-tests and novel methods for accelerated ageing tests under various conditions (electrical and/or thermal stress): thermal shock tests (TST, air–air test) and thermal cycling tests (TCT, air–air test) under various conditions (with and without DC bias, TST cold and hot, different channel current I DS and different extremes temperatures Δ T values). It is important to understand the effects of the reliability degradation mechanisms on the S-parameters and in turn on static and dynamic parameters. The analysis of the experimental results is presented and the physical processes responsible for the observed degradation at different stress conditions are studied by means of 2D ATLAS-SILVACO simulations. The RF performance degradation of hot-carrier effects power RF LDMOS transistors can be explained by the transconductance and miller capacitance shifts, which are resulted from the interface state generation and trapped electrons, thereafter results in a build up of negative charge at Si/SiO 2 interface.

Analysis of punch-through breakdown in bulk silicon RF power LDMOS transistors

The design and electrical performance of bulk silicon power LDMOS transistors for base station applications are analyzed in this paper. Power LDMOS transistors have been fabricated with a seven mask levels process technology including a LOCOS oxide in the drift region and a polysilicon field plate. Specific on-state resistances in the range of 3 mΩ × cm 2 have been experimentally measured on fabricated LDMOS transistors with a voltage capability of 80 V and a threshold voltage around 2.5 V. Moreover, the impact of the basic geometrical and technological parameters on the voltage capability and on the on-state resistance is also analyzed. Special emphasis has been made on the existence of a premature breakdown by a punch-through mechanism due to the combination of a low Boron dose in the body region and an excessive phosphorous dose in the drift region. Technological solutions for avoiding this undesired phenomenon are also discussed.

2-D simulation and analysis of temperature effects on electrical parameters degradation of power RF LDMOS device

This paper presents a synthesis of temperature effects on power RF Laterally Diffused (LD) MOS performances, which can modify and degrade transistor physical and electrical behaviour. In this work, the temperature influence on device electrical characteristics is discussed with regard to physical limits for device operation. A developed 2-D structure was implemented and simulated using the physical simulator Silvaco-Atlas to explain the observed data and offer insight into the physical origin of LDMOS temperature behaviour. The temperature dependence of most important electrical parameters such as channel current Ids, threshold voltage Vth and inter-electrodes capacitances (Cds, Cgs) is investigated. The temperature effects on mobility, electron concentration, electric field, current flow lines and Fermi level are taken into account. Finally, initial failure analysis is discussed.

Reliability study of power RF LDMOS device under thermal stress

This paper presents the results of comparative reliability study of two accelerated ageing tests for thermal stress applied to power RF LDMOS: Thermal Shock Tests (TST, air–air test) and Thermal Cycling Tests (TCT, air–air test) under various conditions (with and without DC bias, TST cold and hot, different extremes temperatures ΔT). The investigation findings of electrical parameter degradations after various ageing tests are discussed. On-state resistance (Rds_on) is reduced by 12% and feedback capacitance (Crss) by 24%. This means that the tracking of these parameters enables to consider the hot carrier injection as dominant degradation phenomenon. To reach a better understanding of the physical mechanisms of parameter's shift after thermal stress, a numerical device model (2D, Silvaco-Atlas) was used to confirm degradation phenomena.

Electrical parameters degradation of power RF LDMOS device after accelerated ageing tests

This paper reports novel methods for accelerated ageing tests, with comparative reliability between them for stresses applied on power RF LDMOS: Thermal Shock Tests (TST), Thermal Cycling Tests (TCT), High Voltage Drain (HVD) and coupling thermal and electrical effects under various conditions. The investigation findings obtained after various ageing tests show the degradation and the device’s performance shifts for most important electric parameters such as transconductance (Gm), on-state resistance (R ds_on), feedback capacitance (C rss) and gatedrain capacitance (C gd). This means that the tracking of these parameters enables to consider the hot carrier injection as the dominant degradation phenomenon. However, this is explained by excitation and trapping of electrons in the oxide-silicon interface at the drain side. A physical simulation software (2D, Silvaco-Atlas) has been used to locate and confirm degradation phenomena.

Comparative analysis of accelerated ageing effects on power RF LDMOS reliability

We present in this paper results of comparative reliability study of three accelerated ageing tests applied on power RF LDMOS: Thermal Shock Tests (TST, air-air test), Thermal Cycling Tests (TCT, air-air test) and High Temperature Storage Life (HTSL). The two first tests are carried out with a drain current flowing through the device during stress. The results obtained show the variation and the Device’s performance quantitative shifts for some macroscopic electric parameters such as threshold voltage (V th), transconductance (G m), drain-source current (I ds), on-state resistance (R ds_on) and feedback capacitance (C rs) under various ageing tests. To understand the degradation phenomena that appear after ageing, we used a new electro-thermal model implemented in Agilent’s ADS as a reliability tool.

Power transistors fabricated using isotopically purified silicon (/sup 28/Si)

It is well known that isotopic purification of group IV elements can lead to substantial increases in thermal conductivity due to reduced scattering of the phonons. The magnitude of the increase in thermal conductivity depends on the level of isotopic purification, the chemical purity, as well as the test temperature. For isotopically pure silicon (/sup 28/Si) thermal conductivity improvements as high as sixfold at 20 K and 10%-60% at room temperature have been reported. Device heating during operation results in degradation of performance and reliability (electromigration, gate oxide wearout, thermal runaway). In this letter, we discuss the thermal performance of packaged RF LDMOS power transistors fabricated using /sup 28/Si. A novel technique allows the cost effective deployment of this material in integrated circuit manufacturing. A clear reduction of about 5/spl deg/C-7/spl deg/C in transistor average temperature and a corresponding 5%-10% decrease in overall packaged device thermal resistance is consistently measured by infrared microscopy in devices fabricated using /sup 28/Si over natural silicon.

Reliability study of Power RF LDMOS for Radar Application

This paper presents an innovative bench specifically dedicated to high RF power device lifetime tests under pulse conditions for radar application. This bench is able to stress eight devices in order to have a statistic sample for MTTF estimation. The bench allows to apply and keep track of all RF powers, voltages and temperatures. Both electrical and thermal stresses applied should lead to modifications of the device performances. A commercial LDMOS transistor has been chosen for the first tests. This paper presents the electrothermal modelling performed to understand the degradation phenomenons that appear during device ageing. The model will be used as a reliability tool in order to correlate RF LDMOS electrical parameters with any kind of degradation phenomenon.

Simulation and modeling of the substrate contribution to the output resistance for RF-LDMOS power transistors

High frequency substrate losses for RF MOSFETs are analyzed using numerical device simulation. The results show that losses in devices made on low resistivity substrate occur through the substrate while losses in devices made on high resistivity substrate in the high frequency region occur along the surface through the device (source–drain). An equivalent circuit model is developed which accurately describes the off-state losses. Based on the model significant improvements in terms of output resistance are demonstrated, using an improved device on high resistivity substrate.

1 W/mm RF power density at 3.2 GHz for a dual-layer RESURF LDMOS transistor

We present state-of-the-art performance, in terms of output power density, for an RF-power LDMOS transistor. The novel device structure has a dual-layer RESURF of the drift region, which allows for a sub-μm channel length and a high breakdown voltage of 110 V. The output power density is more than 2 W/mm at 1 GHz and a V/sub DS/=70 V, with a stable gain of 23 dB at V/sub DS/=50 V. At 3.2 GHz the power density is over 1 W/mm at V/sub DS/=50 V and 0.6 W/mm at V/sub DS/=28 V. These results are to our knowledge the best ever for silicon power MOSFETs.