Power Management Chip Research Articles

A Study of High Transient Response Low Dropout Linear Regulator Chips

Abstract. With the rapid development of the microelectronics industry in the world, electronic products are being updated more and more quickly. This has created a growing large market demand for power management chips. Low drop-out linear regulators have become one of the most widely used types of power management chips due to their advantages of high stability, low drop-out voltage, and fast response. This paper is a data collection study and comparison of improvement methods based on high transient response low drop-out linear regulators. It describes the basic principles of LDOs as well as the principles, advantages and disadvantages of different improvement methods. It was found that the method of shortening the overshoot and undershoot durations by constructing transient enhancement circuits was the best in terms of performance among the following research methods. The stability of capacitor-less LDO is harder to control. Using compensation circuits to improve stability will increase circuit complexity. The capacitor-coupled current mirror method has a longer startup time, because it takes some time for it to reach homeostasis. The high complexity and energy consumption of the dual feedback loop structure makes the circuit costly.

Recent advances in LDO chip research

Abstract. With the rapid development of integrated circuit technology and the wide application of Internet of things devices, the demand for power management chips is increasing. Low-dropout regulators (LDO) play an important role in modern electronic devices. It provides a stable low output voltage while maintaining low power consumption. Recently some progress has been made in the research of LDO chips, focusing on improving power efficiency, reducing static current, and enhancing transient response. The study shows that the static current has been significantly reduced by using the subthreshold MOS tube and dynamic current bias technology. In terms of power supply rejection ratio (PSRR), by improving the circuit design, the PSRR of LDO can be maintained above -80 dB under various conditions. In addition, improvements to the transient response result in significantly optimized overshoot and recovery times of the output voltage, ensuring voltage stability when the load changes rapidly. These advances enable LDO chips to meet the demanding requirements of high-performance and Internet of things device applications. Future challenges include further reducing static current, improving PSRR performance in high-frequency environments, and effectively addressing thermal management issues.

Total ionization dose and electromagnetic pulse synergistic effects on low dropout linear regulator

As a power management chip widely used in various electronic systems, the low dropout regulator (LDO) plays a crucial role in the normal operation of electronic systems. Ionizing radiation and electromagnetic pulse (EMP) radiation can cause interference and damage to the LDO, posing risks to the proper functioning of electronic systems in large-scale scientific devices. In this study, through separate experimental investigations on the Total Ionizing Dose (TID) effects, EMP effects, and synergistic effect of the LDO, it was found that parameters such as the LDO output voltage decreases with increasing irradiation dose, with more severe degradation observed under grounded bias. The EMP effects mainly cause oscillations in the LDO output voltage and a slight increase in its mean value. The results of the synergistic effect experiments indicate that there is a certain synergistic interaction between the TID effects and the EMP effects. The synergistic effects lead to an increase in the amplitude of the oscillations and changes in the mean value of the output voltage.

Design and Research of Oscillator Circuit with Soft Starting in Power Management Chip

In this paper, an oscillator circuit with a soft start function is designed for DC-DC converters, and its working principle is analyzed. Based on the NUVOTON 0.35 μm BCD technology, the circuit is fully simulated and optimized via Cadence software. Under the typical environment of 5 V and 27°C, the typical oscillation frequency of the oscillator is 800 kHz and the duty ratio is 20%. The expected index is reached and the circuit function is realized. At the same time, a temperature-independent current bias is designed to charge and discharge a capacitor in the oscillator so that the frequency of the oscillator is very little affected by temperature. Under the simulation condition of -40°C–140°C, the operation of the oscillator is stable and its frequency variation is 2.95% over the above temperature range.

Design of a High PSRR Low-pressure Bandgap Reference Source with Curvature Compensation

Based on the NUVOTON 0.35 μm BCD process, a low voltage bandgap reference with an input voltage of 5 V and output voltage of 0.6 V is designed in this paper. The traditional low-voltage bandgap reference output voltage has a large temperature coefficient and poor ability to suppress power supply fluctuations. In this paper, a circuit with high order compensation is proposed to reduce the temperature coefficient of the circuit, and a pre-regulated circuit is used to increase the power supply rejection ratio. The simulation results are at -30 °C∼130 °C. The output voltage of reference voltage is 947.5 μV, the temperature coefficient is 9.58 ppm/°C, and the power suppression ratio is -104.62 dB, which meets the design requirements of the power management chip.

Low Temperature Wafer Bonding of Silicon Carbide/Aluminum Nitride

Because of the wide energy gap material properties and high compatibility with existing silicon material processing, silicon carbide (SiC) has become the preferred material for power management chips that have been used in electric vehicles. On the other hand, aluminum nitride (AlN) material has become the first choice for carrying wafers due to its high strain-resistant mechanical properties, strong dielectric coefficient, excellent thermal conductivity, and high etching resistance. In this study, the surface chemistry of silicon carbide was changed into an AlN-based material to perform wafer bonding processing to develop low-temperature bonding technology for silicon carbide/aluminum nitride materials. We found through experiments that it is quite difficult for a SiC wafer to bond with an AlN wafer even if the surfaces ofthe SiC wafer and the AlN wafer are subjected to conventional surface activation treatment using oxygen plasma or argon plasma. The possible reason is that although the surface of the SiC wafer is bombarded by oxygen or argon plasmas to generate some dangling bonds, the chemical properties of Si-C and Al-N, such as electronegativity, make it difficult to generate chemical bonds between the matching surfaces of SiC/AlN. Through a material modification technology, a high-temperature sputtering method is used to make highly active AlN clusters sputtered from the target directly bond with SiC and finally form a thin AlN layer that strongly adheres to the surface of the SiC wafer. And then through the bonding of AlN/AlN homogeneous materials, although the surface roughness measurement (RMS) cannot satisfy the condition of being less than 5 angstroms for wafer bonding, the goal of low-temperature bonding can be achieved by capillary bonding. Therefore, the SiC surface is changed into an AlN-based thin layer by high-temperature sputtering, which can further chemically bond with the AlN wafer surface by capillary bonding to achieve the low-temperature bonding of SiC/AlN, as shown in Figure 1.Reference1. Shao-Ming Nien, Jian-Long Ruan, Yang-Kuao Kuo, and Benjamin Tien-Hsi Lee, Low-temperature rough-surface wafer bonding with aluminum nitride ceramics implemented by capillary and oxidation actions, Ceramics International, Volume 48, Issue 6, 2022 Figure 1

`Design-technology-co-hardening for voltage reference and linear voltage regulator based on bipolar technology

This article presents a radiation-hardened voltage reference and a radiation-hardened low-dropout (LDO) voltage regulator manufactured in bipolar technology for space environment applications. The output of voltage reference is adjustable in 2.5 V ∼ 30 V, with a supply voltage of 24 V. The LDO regulator operates from an input voltage range of 2.5–26 V and provides an output voltage of 1.5 V, with output voltage accuracy of ±0.5 %. The dropout voltage <700 mV at the full load current of 7A. It achieves line regulation and load regulation are <0.5 % over the entire operating temperature range. Through the circuit design of radiation hardening and the optimization of anti-radiation technology, both power management chips have single-event transient (SET) immunity at linear energy transfer (LET) of 37.4 MeV·cm2/mg. The output voltage deviation of rad-hard voltage reference is <0.6 % with total dose radiation tolerance of 100krad(Si) at 0.1 rad(Si)/s.

A Fast Transient Low-Dropout Regulator with High-Power Supply Rejection

With the continuous popularization of portable electronic products in electronic information, aerospace, biomedicine and other fields, low-dropout regulator (LDO) has become an important part of modern power management chips. Compared with other power management modules, it has the advantages of low power consumption, high power supply rejection, and strong anti-noise capability. However, the LDO power tube has a large width-to-length ratio, so when the load changes transiently, the gate of the power tube cannot respond in time, resulting in an overshoot and undershoot of the output voltage and a long recovery time. In this paper, the LDO transient enhancement circuit is designed. When the load changes transiently, the power tube gate capacitor is quickly charged and discharged, which overcomes the overshoot voltage and undershoot voltage. While improving the transient response of traditional LDO, the structure ensures the power supply rejection (PSR) and other performance of the circuit. According to the results, with an input of 2.5 V, the output voltage is regulated to 1.2 V, and PSR is -80 dB. When the load changes by 20 mA in 1 μs, it is stable within 1.2 μs while the undershoot voltage is controlled at 51 mV and the overshoot voltage is controlled at 65 mV.

Application of Wireless Sensor Network Technology Using Intelligent Algorithm in Mismatch Detection of Photovoltaic Power Generation

The paper was aimed at ensuring the stable operation of the photovoltaic power generation system (PVPGS) and improving the accuracy of automatic mismatch detection. Consequently, this paper presents a PVPGS-oriented mismatch detection system based on wireless sensing technology (WSN). Firstly, the photovoltaic array (PVA) is constructed using a microcontroller, power management chip, nRF24L01, temperature sensor, voltage, and current sensor. Then, a fault detection and localization (FDL) scheme based on the Hampel algorithm is optimized, and Matlab/Simulink implements the PVA simulation model. Finally, several typical mismatch faults are simulated to verify the feasibility of the proposed FDL scheme using the measured voltage and current data. The empirical findings corroborate that the proposed FDL scheme can automatically and regularly collect photovoltaic (PV) electrical characteristic data and quickly and accurately identify and position a mismatch. In the case of a PVA open-circuit fault, the output current loss of the PVA is equal to the sum of the current of the open-circuit fault string in the array during normal operation. When the PVA is short-circuited, the PVA output voltage loss equals the sum of the output voltages of the faulty components in the most serious fault string under normal operation. Overall, the classification accuracy of the proposed FDL scheme is 97.556%. Lastly, the experiment reveals that the classification accuracy of the proposed FDL scheme is 100% for array aging, shadow, and the open circuit. Therefore, the research proposal has a good application prospect.

Fully-integrated DCDC buck converter based on PID algorithm

With the continuous development of power supply technology, the application of power management chips becomes more extensive, and the requirements for fully integrated power management chips are getting higher. This paper designs a buck converter with a fully integrated digital control circuit and power circuit with an output voltage of 2V. In voltage mode, digital pulse width modulation (DPWM) technology and PID algorithm are used, and a digital closed-loop control buck circuit system is designed by cadence tools. The performance of analog and digital closed-loop control circuits is compared at the same buck power stage. Under rated load conditions, the lock-up time of the digital control buck circuit is 826us, the output voltage ripple is 14.75mV, the response time of load sudden change at light load is about 900us, and the response time of load sudden change at heavy load is about 2ms.

Design of Unlicensed Dual Band Quasi-Yagi Antenna Using Semi-Bowtie for Indoor Wireless Power Transfer Application

This paper focuses on antenna for harvesting energy from a dedicated transmitter. The potential novel quasi-Yagi antenna with semi-bowtie driven element can be used as part of rectenna due to its characteristic of having directional properties and considerably wide bandwidth covering the Industrial, Scientific, and Medical (ISM) band consists of 863-870 MHz band and 902-928 MHz band. The modified quasi-Yagi is designed on a low-cost FR4 substrate with a physical size of 130 x 100 mm2 equivalent to 0.35λo x 0.27λo. The antenna has a peak directivity of 2.7 dBi and peak gain of 2.2 dBi in the targeted unlicensed bands with bandwidth of 14.4% for the range between 0.820-0.944 GHz. The shift in the resonant frequency is achieved by varying the phase shifter length and maintaining the same width for consistency. The antenna's operating frequency range varies between 0.8 GHz until 1 GHz which is less than 1 GHz by using semi-bowtie as driven element with a specific 7.22⸰ flare angle. The phase shift arm length of the antenna has been studied and simulated by using Computer Simulation Technology (CST) software and verified by using analytical equations. The simulated results are in accordance with the results obtained using analytical method. The same antenna geometry except variation in phase shifter arm length has been used throughout the study for consistency. The proposed antenna is promising to be used as part of rectenna for powering power management chip such as BQ25570 in a smart house environment operating at the indicated ISM bands.

Thermal improvement in 3D embedded modules using copper bar vias

Abstract The combination of increased I/O density, reduced footprint, and multi-die capability within a single platform makes embedded die an attractive solution. The benefits of embedding active die include miniaturization, improved electrical &amp; thermal performance, heterogeneous integration, and an opportunity for cost reduction. Currently vertical integration is happening in power management chips with embedded components integrated into modules. Heat dissipation in integrated 3D high efficiency power modules is challenging when die is embedded inside the substrate. Heat dissipation affects efficiency and electro-migration of the packaged structures. Copper bar vias can be replaced for circular vias in the substrate design for thermal improvement. The thermal improvement is simulated using Ansys FEM (Finite Element Method) tools.

Design and Simulation of Error Amplifier used in Power Management chips

This paper discusses the design procedure of error amplifier, which is used in the power factor correction circuit built with dc-dc Boost converter. The error amplifier is the heart of the power management IC’s which indicates the accuracy of the entire circuitry. The specifications are considered which is suitable for power management applications. The gain of the amplifier is chosen to be 60db, UGB of 75MHz, slew rate of 50V/uS, PM greater than 60’, technology 180nm. The design is simulated using tsmc 180nm technology with Analog Device’s LT-SPICE simulator.

A Multi-Beam Shared-Inductor Reconfigurable Voltage/SECE Mode Piezoelectric Energy Harvesting Interface Circuit.

This paper presents an autonomous multi-input (multi-beam) reconfigurable power-management chip for optimal energy harvesting from weak multi-axial human motion using a multi-beam piezoelectric energy harvester (PEH). The proposed chip adaptively operates in either voltage-mode or synchronous-electrical-charge-extraction-mode (VM-SECE) to improve overall efficiency, extract maximum energy regardless of the PEH beams' impedance/voltage/frequency variations, and protect the chip against large inputs, eliminating the need for high-voltage processes. It can simultaneously harvest energy from up to 6 beams using only one shared off-chip inductor. It uses an active negative voltage converter to extend the input-voltage range to as low as 35mV. In addition, an active voltage doubler with a small footprint is implemented for faster cold start. A prototype VM-SECE chip was fabricated in a 0.35-μm 2P4M standard CMOS process occupying 1.9 mm2 active area. To fully characterize the chip performance, it was tested with both a commercial single-beam PEH and a custom-made PEH with five mechanically plucked thin-film beams. With the commercial PEH, compared to an on-chip full-wave active rectifier (FAR) with 95.6% efficiency, the VM-SECE chip harvested 3.28x more power for shock inputs at 1 Hz frequency and 4.39 g acceleration. With the custom 5-beam PEH for a pseudo-walking condition, compared to the on-chip FAR, the VM-SECE chip harvested 1.59x and 2.38x more power for 1-and 5-beam operations, respectively.

Voltage Regulation and Power Management for Wireless Flow Sensor Node Self-Powered by Energy Harvester With Enhanced Reliability

This paper reports a voltage regulation method with power management to enhance the reliability and stability of the self-powered flow rate sensor. Triboelectric energy harvesters are used both as the sensing signals and the power supply. One channel of the raw voltage from wind flow is regulated to a stable signal by the integral circuit, while the other channel is used for energy harvesting to provide the power for the whole circuit. Power management chip with ultra-low power consumption has been utilized with micro controller unit and antenna for wireless transmission. A low deviation of less than 2.5% has been achieved for the flow sensing signal and the temperature has also been monitored simultaneously, which shows promising application for the central air-conditioning system in smart buildings.

A High-precision Current Sense Circuit with Trimming for DC-DC Converts

A high-precision current sense circuit with trimming is proposed to realize the over-current protection of the power management chip and improve its conversion efficiency. Based on solving the problem of voltage offset and current inrush caused by process deviation, this circuit can detect the value of the inductor current accurately. By designing the bandgap reference circuit and the reference voltage bias network, the required stable reference voltage and bias current can be obtained. The trimming bit selection circuit can realize the trimming function. This circuit is designed with TSMC 180nm 1P3M GEN2 process, and all circuits are verified by Cadence Spectre.

Self-Regulated Reconfigurable Voltage/Current-Mode Inductive Power Management

A reconfigurable power management structure for inductive power delivery has been proposed by adaptively employing either resonant voltage or current mode (VM or CM) to improve the inductive power transmission performance against coils’ coupling distance (d), orientation ( $\phi $ ), and load impedance (R L ) variations. At the presence of these variations, unlike conventional VM and CM power managements with poor voltage- and power-conversion efficiencies (VCE and PCE), respectively, the proposed voltage/current-mode inductive power management (VCIPM) chip can achieve high VCE by automatically switching to CM when the receiver (Rx) coil voltage (V R ) is smaller than the required load voltage (V L ), and achieve high PCE by operating in VM when V R > V L . In addition, since VM and CM are only suitable for small and large R L within the range of hundreds of ohms and above, respectively, the VCIPM chip can extend the R L range. The VCIPM chip also eliminates the need for two off-chip capacitors by performing rectification, regulation, and over-voltage protection (OVP) in one step with one off-chip capacitor. In VM, intentional reverse current is employed for both voltage regulation and OVP, while the Rx coil switching frequency (f sw ) is adjusted for voltage regulation in CM. The theory behind the proposed VCIPM structure has been presented and validated by simulations and measurements. A VCIPM prototype chip was fabricated in a 0.35- $\mu \text{m}$ 2P4M standard CMOS process occupying 0.52-mm2 active area. In measurements, the VCIPM chip, operating at 1 MHz, achieved a high VCE of 4.1 V/V for R L of 100 $\text{k}\Omega $ by operating in CM with fsw = 166.6 kHz, and extended d and $\phi $ from 6 to 13.5 cm (125%) and 30° to 75° (150%), respectively, compared to its VM counterpart by adaptively switching from VM to CM.

Concept Design for a 1-Lead Wearable/Implantable ECG Front-End: Power Management.

Power supply quality and stability are critical for wearable and implantable biomedical applications. For this reason we have designed a reconfigurable switched-capacitor DC-DC converter that, aside from having an extremely small footprint (with an active on-chip area of only 0.04 mm), uses a novel output voltage control method based upon a combination of adaptive gain and discrete frequency scaling control schemes. This novel DC-DC converter achieves a measured output voltage range of 1.0 to 2.2 V with power delivery up to 7.5 mW with 75% efficiency. In this paper, we present the use of this converter as a power supply for a concept design of a wearable (15 mm × 15 mm) 1-lead ECG front-end sensor device that simultaneously harvests power and communicates with external receivers when exposed to a suitable RF field. Due to voltage range limitations of the fabrication process of the current prototype chip, we focus our analysis solely on the power supply of the ECG front-end whose design is also detailed in this paper. Measurement results show not just that the power supplied is regulated, clean and does not infringe upon the ECG bandwidth, but that there is negligible difference between signals acquired using standard linear power-supplies and when the power is regulated by our power management chip.

90W Off-Line High Power Factor Correction Module Design

The design is based on Onsemi power management chip NCP1652, in the input range of voltage 85V~265V, to achieve of 19V 90W off-line high power factor output. Using the NCP1652 double working mode, comparing with a single stage flyback converter, when it works in light/heavy load conditions, the circuit can still have a stable output and a high PF by controlling the circuit working in the CCM/DCM mode. Where, Input voltage: 110V, Output: XV; Input voltage 220V, Output: XV; Input voltage: 110V, Output: XV. Under-Voltage Point: 16V; Over-Voltage Point: 23V; Over-Current Point: 5A; heavy loaded with 1s from the start, the standby power consumption &lt; 1W. Key words:high PFC; NCP1652; flyback converter; off-line

Silicon Process and Manufacturing Technology Evolution: An overview of advancements in chip making

silicon process technology is the dominant technology for the fabrication of a majority of the consumer electronics chips that are the building blocks of smartphones, tablets, microcontrollers, data converters, power management chips, and computers [1]. The functional block diagram of the silicon chips for a typical smartphone is shown in Figure 1: the applications processors, FLASH memory, power and battery management, touch-screen drivers, the 2G/3G/4G long-term evolution radio-frequency transceiver, the baseband modem, Wi-Fi, Bluetooth, GPS chips, audio CODEC, and CMOS image sensors, among others. The exception to this may be the power amplifier, which is still mainly fabricated by the gallium arsenide (GaAs) bipolar process as a niche area in the chip industry. Since the invention of the integrated circuit and the metal?oxide?semiconductor field-effect transistor (?MOSFET), the silicon process for making transistors and chips has become the driving force for the chip industry. The evolution of the cell phone and computers is intrinsically linked to the evolution of the silicon fabrication process advancement.