Microprocessor Power Research Articles

Control system design of an intelligent food delivery robot

Contemporary many young people more and more choose to enjoy a variety of food outside, followed by a variety of food service industry emerging in an endless stream of new ideas, new changes. Nowadays, more and more intelligent food delivery robots are appearing in restaurants in many cities, making great contributions to the improvement of the cost and efficiency of food delivery in the catering industry. This paper designs a low-cost, efficient and intelligent food delivery robot, which can receive background instructions, choose the route and order for automatic food delivery, and automatically return after the task. The intelligent food delivery robot adopts a modular design method, mainly including power supply, microprocessor, the keys, drive, positioning, tracking navigation, obstacle avoidance and Wi-Fi communication parts.

Improvement of control devices for road sections of railway automation and telemechanics

In this scientific article, control sensors and control devices have been improved based on the method of counting arrows of the rolling stock of railway transport. The microprocessor-controlled control unit and control system have been simplified to manage traffic between two stations, and a self-monitoring, reliable and risky scheme has been developed. Wiring diagrams of existing transport relays have been updated for uninterruptible power supplies, microprocessor devices, and sensors. An automated schematic diagram with a microprocessor for signaling a collision of a railway with wagons has been created, and the order in which the speed of train movement approaches the crossing has been maintained. The complex functional control of rolling stock was improved based on the method of counting bullets, electronic archiving of the movement of orders of the train attendant and dispatcher, as well as the operation of devices for monitoring the technical condition of the station.

Hardware in the loop co-simulation of finite set-model predictive control using FPGA for a three level CHB inverter

Along with the development of powerful microprocessors and microcontrollers, the applications of the model predictive controller, which requires high computational cost, to fast dynamical systems such as power converters and electric drives have become a tendency recently. In this paper, two solutions are offered to quickly develop the finite set predictive current control for induction motor fed by 3-level H-Bridge cascaded inverter. First, the field programmable gate array (FPGA) with capability of parallel computation is employed to minimize the computational time. Second, the hardware in the loop (HIL) co-simulation is used to quickly verify the developed control algorithm without burden of time on hardware design since the motor and the power switches are emulated on a real-time platform with high-fidelity mathematical models. The implementation procedure and HIL co-simulation results of the developed control algorithm shows the effectiveness of the proposed solution.

Implementation of space vector modulation for two level Three-phase inverter using dSPACE DS1104

With increasing research and advancement in solid-state power electronic devices and microprocessors, various inverter control techniques employing Pulse Width Modulation (PWM) are becoming popular especially in AC motor drive applications. The most commonly used techniques are Sinusoidal PWM (SPWM) and Space Vector modulation PWM (SVPWM). SVPWM is considered to be superior to the SPWM because of better DC bus utilization. In this paper, a real-time digital implementation of SVPWM algorithm for three-phase two level inverter using dSPACE DS1104. The results obtained from the experimentation are closer to that of simulation, which confirms the validity of the implemented algorithm.

Ensuring the Reliability and Efficiency of the Power Industry in the Agricultural Sector of the Republic of Belarus in Modern Conditions

The necessity of improving the power supply system in the agricultural sector is substantiated by the growing share of first-category loads that require targeted reliability. Improving values of the technical and economic indicators of centralized energy generation and its transmission through main and distribution grids cannot ensure high reliability of consumers of the first category, the number of which is constantly growing in agriculture. It is noted that if the power system in outage of the generating source of the high power supply is provided by inputting the emergency reserve, then at emergency switching-off phase of the section of the mains, power supply of the consumers powered by the schemes for both radial and looped distribution network may be absent for a long period of time (several hours). The ways and methods of improving the power supply system, such as integration of a single power system with distributed generation sources, ensuring their parallel operation, load management using complex tariffs for electric energy that take into account the form of load schedules, modernization of technological processes taking into account their automation and improvement of technical and economic indicators, are considered. Taking into account the increase in electricity consumption for heating and hot water supply, we consider the option of eliminating cross-subsidization, which stimulates the interest of consumers in saving electricity and reducing the fee for electricity consumption by changing the operating modes of equipment and devices. The analysis of promising energy-saving measures in agricultural power engineering demonstrated that routine measures are being supplemented by other measures induced by the fact that power electronics and microprocessor technology have significantly advanced in their development in the agricultural energy sector over the past decades, for example, for frequency control of asynchronous motors equipped by a short-circuited rotor that has high values of energy and dynamic indicators. Since there are a number of technologies in agriculture where electric energy is used without the electric drive units application and each of the technological processes has its own requirements for the reliability and quality of electric energy, the scheme of mutual redundancy from adjacent substations using distributed generation sources and technical means of automated energy accounting, control and management of electrical loads, is considered.

Comparative Harmonic Analysis of Various PWM Techniques for Diode Clamped Multi-Level Inverter in MATLAB/Simulink

Advances in solid state power electronic devices and microprocessors has led to the development of various pulse-width-modulation (PWM) techniques for industrial applications. For example, PWM based 3-phase voltage source inverters (VSI) convert Solar cell DC power to AC power with variable voltage magnitude and variable frequency. To analyze the applications and advantages of three different PWM techniques over one another, inverter with different techniques have been modelled in the MATLAB/ Simulink environment. The Techniques compared in the paper are: the sinusoidal PWM (SPWM) technique, the third-harmonic-injection PWM (THIPWM) technique, and the bus-clamped PWM (BCPWM) technique. These three methods are compared by discussing their ease of implementation and by analyzing the output harmonic spectrum of various output voltages (poles voltages, line-to-neutral voltages, and line-to-line voltages) and their total harmonic distortion (THD).

Implementation of space vector modulation for two level three-phase inverter using dSPACE DS1104

With increasing research and advancement in solid-state power electronic devices and microprocessors, various inverter control techniques employing pulse width modulation (PWM) are becoming popular especially in AC motor drive applications. The most commonly used techniques are sinusoidal PWM (SPWM) and space vector modulation PWM (SVPWM). SVPWM is considered to be superior to the SPWM because of better DC bus utilization. In this paper, a real-time digital implementation of SVPWM algorithm for three-phase two level inverter using dSPACE DS1104. The results obtained from the experimentation are closer to that of simulation, which confirms the validity of the implemented algorithm.

Evaluation of the minimum required length to study improved heat exchangers via computational fluid dynamics

Heat exchangers are fundamental for energy plants and the operation of industrial processes. As a result, active and passive techniques are needed to increase heat transfer and develop efficient and reliable designs. The design of heat exchangers has been based on iterative methods that require experimentation to be validated. These circumstances, added to the development of powerful microprocessors, promote the use of numerical methods to study flow distribution and pressure drop, as well as thermal analyses applying different turbulence models and several coupling speed-pressure schemes. This paper examines flow development through curved and twisted tube heat exchanger by means of a computational fluid dynamics numerical model developed in ANSYS® in order to establish the minimum length required to infer conclusions for the complete exchanger. This work tries to reduce the computational cost while maintaining the balance between desired accuracy and available computational resources. Finally, this study shows that the flow can be considered fully developed after it has traveled 360° inside the helix; after that point, secondary flows and re-circulation regions improve the heat transference in these devices can be verified.

Leakage Current Analysis of 6T & 7T-SRAM using FINFETs at 22nm Technology

Persistent scaling of planar MOSFET results in increase in transistor package density and performance of chip. However at nanometer regime , it has become a very challenging issue due to the increase in the short channel effects. In nanoscaled MOSFETs, the channel loses control from gate terminal due to potential at drain. Due to this, it is difficult to turn off MOSFET completely which inturn leads to leakage currents. Since cache memory occupies more area of processors, it is difficult to reduce leakage power in microprocessors. Double gate transistors have become replacement for MOS transistors at nano level. Since FINFETs have double gates, the leakage currents can be controlled effectively than planar MOSFET. In this paper, leakage currents of 6T & 7T-SRAM memory cell are analyzed using FINFETs at 22nm technology in hspice software

An Instruction-Driven Adaptive Clock Management Through Dynamic Phase Scaling and Compiler Assistance for a Low Power Microprocessor

This paper presents an instruction-driven adaptive clock management scheme using a dynamic phase scaling (DPS) operation and compiler-assisted cross-layer design methodology for a low power microprocessor. The intrinsic instruction-level timing variation is explored on an ARMv7 ISA pipeline architecture. The clock period can be dynamically adjusted by a multi-phase all-digital PLL, with the timing encoded into the instruction set at the compiler level. Special compiler optimization schemes are also presented through reorganizing the runtime instruction sequences to better exploit the dynamic timing slack. In addition, an instruction timing calibration scheme is proposed to characterize the instruction delay under process, voltage, and temperature (PVT) variations, which can be integrated with the conventional dynamic voltage and frequency scaling (DVFS). The implementation of 55-nm CMOS process shows a 20% performance improvement from the proposed instruction-driven adaptive clock management. The performance improvement can be equivalently converted up to 32% energy saving benefit.

Підвищення інформаційної ефективності мереж та засобів інтернету речей

The basis of the information efficiency increasing of networks and means of Internet of Things is the implementation by processor means of object systems of wireless networks of complex algorithms of processing, compact coding and protection of signal samples, video data frames and measuring values, crypto- proof and noise-proof transmission of monitoring information packets directly in the places of origin of network streams. The algorithms of compression and monitoring data protection should be optimized for the speed and accuracy of data encoding, taking into account the minimization of computing operations by micro power microprocessors and microcontrollers of object systems of the Internet of Things. The reduction of information flows in places of installation of object systems of Internet networks of things is achieved on the basis of adaptation of data coding algorithms, depending on the conditions of input and the accuracy of the presentation of monitoring data and the formation of code-signal sequences of monitoring information packets with increased information capacity. Parameters of noise-proof transmission of crypto-proof information packets are selected depending on the current level of noise in the radio channel. The key characteristic of the operation efficiency of object systems of Internet of things networks is the current speed of the transmission of the compressed and protected monitoring information. With existing computing and channel resources of object systems taking into account the current conditions of input and transfer of monitoring data that are variables, the implementation of reliable and secure data transmission in networks of Internet of Things is carried out by constant support of processor means of object systems the maximum speed of packets of compressed and encrypted monitoring data. In practice, the transmission of such packets is the transmission of pseudo-chaotic break-even information

Lower-Limb Prostheses and Exoskeletons With Energy Regeneration: Mechatronic Design and Optimization Review

Lower-limb biomechatronic devices (i.e., prostheses and exoskeletons) depend upon onboard batteries to power wearable sensors, actuators, and microprocessors, therein inherently limiting their operating durations. Regenerative braking, also termed electrical energy regeneration, represents a promising solution to the aforementioned shortcomings. Regenerative braking converts the otherwise dissipated mechanical energy during locomotion into electrical energy for recharging the onboard batteries, while simultaneously providing negative mechanical work for controlled system deceleration. This paper reviewed the electromechanical design and optimization of lower-limb biomechatronic devices with electrical energy regeneration. The technical review starts by examining human walking biomechanics (i.e., mechanical work, power, and torque about the hip, knee, and ankle joints) and proposes general design principles for regenerative braking prostheses and exoskeletons. Analogous to electric and hybrid electric vehicle powertrains, there are numerous mechatronic design components that could be optimized to maximize electrical energy regeneration, including the mechanical power transmission, electromagnetic machine, electrical drive, device mass and moment of inertia, and energy storage devices. Design optimization of these system components is individually discussed while referencing the latest advancements in robotics and automotive engineering. The technical review demonstrated that existing systems (1) are limited to level-ground walking applications and (2) have maximum energy regeneration efficiencies between 30% and 37%. Accordingly, potential future directions for research and innovation include (1) regenerative braking during dynamic movements like sitting down and slope and staircase descent and (2) utilizing high-torque-density electromagnetic machines and low-impedance mechanical power transmissions to maximize energy regeneration efficiencies.

CAPE: A cross-layer framework for accurate microprocessor power estimation

State-of-the-art system-level simulators can deliver fast power estimates for microprocessor designs, but often at the expense of reduced accuracy. The inaccuracies mainly stem from incorrect or over-simplified modeling of the target architecture. On the other hand, modern register-transfer level (RTL) simulators are cycle-accurate but overwhelmingly time consuming for most real-life workloads. Consequently, the design community often has to make a compromise between accuracy and speed. In this work, we propose a novel cross-layer power estimation (CAPE) technique that carefully integrates system-level and RTL profiling data for the target design in order to attain better accuracy. Our proposed methodology first leverages the SimPoint tool to transform a workload into weighted simulation points. We, then, present two different strategies to represent the critical segment of an application - either with a workload-specific simulation point (CAPE-WSSP) or, with the highest-weighted simulation point (CAPE-HWSP). Next, we profile the critical simulation point with an RTL simulator for maximum accuracy, while the other simulation points are simulated at system-level for fast evaluation. Finally, we input the integrated set of profiling data to the power simulator (McPAT). Our evaluation results show that CAPE can improve the power estimation accuracy by up to 15% for individual simulation points and by ∼8% for the full application, compared to that of a system-level only simulation scheme while adding minimal runtime overhead.

An Isolated Multilevel Quasi-Resonant Multiphase Single-Stage Topology for 380-V VRM Applications

In order to increase the efficiency of modern microprocessor power supplies used in data centers, 380-V dc power distribution systems have been attracting attention due to their high efficiency and high reliability. This paper presents an innovative single-stage approach for 380-V voltage regulator modules (VRMs) based on a quasi-resonant multilevel topology constant on -time operation. The proposed topology inherently integrates the multiphase approach, providing fast phase shedding and flat high-efficiency curves even at light-load conditions. This is a unique advantage, which is not possible to establish in the two-stage approach, which is very important in server architectures, and where high efficiency is required even at light-load conditions. This paper analyzes the circuit topology and proposes a control architecture for fast transient response, including current-sharing capabilities. The digital controller has been implemented in 0.16- $\mu$ m lithography together with a digital pulsewidth modulation with a 195-ps resolution and a 40-MS/s 7-bit analog-to-digital converter. Experimental results show an efficiency of 93% for a 120-A 380–1.8-V VRM power supply.

Two-Way Traffic Ahead: RF\/Analog Self-Interference Cancellation Techniques and the Challenges for Future Integrated Full-Duplex Transceivers

Integration of discrete radios onto a single-silicon CMOS substrate [1]-[6], followed by commercialization of single-chip cellular, Bluetooth, and Wi-Fi radios [7]-[9], has shaped the wireless world that we live in today. Although integration of wireless transceivers with powerful microprocessors in very large systems on chip (SoCs) is currently commonplace in consumer electronics, the demand for lower power consumption, higher effective data rates, and higher network capacity continues to drive research on integrated radios. By some estimates, the demand for mobile data per volume area will increase 1,000x during the next decade, with end-user data rates increasing by as much as 10-100x [10].

The role of speech technology in biometrics, forensics and man-machine interface

<span lang="EN-US">Day by day Optimism is growing that in the near future our society will witness the Man-Machine Interface (MMI) using voice technology. Computer manufacturers are building voice recognition sub-systems in their new product lines. Although, speech technology based MMI technique is widely used before, needs to gather and apply the deep knowledge of spoken language and performance during the electronic machine-based interaction. Biometric recognition refers to a system that is able to identify individuals based on their own behavior and biological characteristics. Fingerprint success in forensic science and law enforcement applications with growing concerns relating to border control, banking access fraud, machine access control and IT security, there has been great interest in the use of fingerprints and other biological symptoms for the automatic recognition. It is not surprising to see that the application of biometric systems is playing an important role in all areas of our society. Biometric applications include access to smartphone security, mobile payment, the international border, national citizen register and reserve facilities. The use of MMI by speech technology, which includes automated speech/speaker recognition and natural language processing, has the significant impact on all existing businesses based on personal computer applications. With the help of powerful and affordable microprocessors and artificial intelligence algorithms, the human being can talk to the machine to drive and control all computer-based applications. Today's applications show a small preview of a rich future for MMI based on voice technology, which will ultimately replace the keyboard and mouse with the microphone for easy access and make the machine more intelligent.</span>

PMSM Servo-Drive Fed by SiC MOSFETs Based VSI

Abstract The article presents modern PMSM servo-drive with SiC MOSFETs power devices and microprocessor with ARM Cortex core. The high switching frequency is obtained due to the application of high efficient power switching components and powerful microprocessor. It allows to achieve good dynamical properties of current control loop, proper disturbance compensation and silent operation of servo-drive. Experimental tests results obtained for two different control schemes (i.e., cascade control structure and state feedback position control) are presented.

Speed Control of DC Motor Using Interval Type-2 Fuzzy Logic Controller

Direct current (DC) motors are widely used for speed control and position control in industry. The simplicity of DC motor speed control is also the main reason for its widespread use. Recently, in parallel with rapid developments in power electronics, microprocessors and semiconductor materials, many control structures are designed for DC motors. In this study, the speed control of the DC motor is carried out using the Matlab/Simulink package program. Type-2 Fuzzy Logic controller (T2FLC) which has efficient performance in modelling uncertainties is proposed for the speed control of DC motor. The classical PI controller and Type-2 Fuzzy Logic controller (T2FLC) are applied to the speed control unit of the DC motor. Simulation studies have also been realized for the designed DC motor model under the same conditions. The results obtained from the classical PI controller and T2FLC have been examined and compared to disturbances such as tracking reference speeds and load changes. According to the obtained simulation results, it has been observed that T2FLC has better results than the classical PI controller in whole conditions.

Ultrahigh Conductive Copper/Large Flake Size Graphene Heterostructure Thin-Film with Remarkable Electromagnetic Interference Shielding Effectiveness.

To guarantee the normal operation of next generation portable electronics and wearable devices, together with avoiding electromagnetic wave pollution, it is urgent to find a material possessing flexibility, ultrahigh conductive, and superb electromagnetic interference shielding effectiveness (EMI SE) simultaneously. In this work, inspired by a building bricks toy with the interlock system, we design and fabricate a copper/large flake size graphene (Cu/LG) composite thin film (≈8.8 μm) in the light of high temperature annealing of a large flake size graphene oxide film followed by magnetron sputtering of copper. The obtained Cu/LG thin-film shows ultrahigh thermal conductivity of over 1932.73 (±63.07) W m-1 K-1 and excellent electrical conductivity of 5.88 (±0.29) × 106 S m-1 . Significantly, it also exhibits a remarkably high EMI SE of over 52 dB at the frequency of 1-18 GHz. The largest EMI SE value of 63.29 dB, accorded at 1 GHz, is enough to obstruct and absorb 99.99995% of incident radiation. To the best of knowledge, this is the highest EMI SE performance reported so far in such thin thickness of graphene-based materials. These outstanding properties make Cu/LG film a promising alternative building block for power electronics, microprocessors, and flexible electronics.

An efficient solution of real-time data processing for multi-GNSS network

Global navigation satellite systems (GNSS) are acting as an indispensable tool for geodetic research and global monitoring of the Earth, and they have been rapidly developed over the past few years with abundant GNSS networks, modern constellations, and significant improvement in mathematic models of data processing. However, due to the increasing number of satellites and stations, the computational efficiency becomes a key issue and it could hamper the further development of GNSS applications. In this contribution, this problem is overcome from the aspects of both dense linear algebra algorithms and GNSS processing strategy. First, in order to fully explore the power of modern microprocessors, the square root information filter solution based on the blocked QR factorization employing as many matrix–matrix operations as possible is introduced. In addition, the algorithm complexity of GNSS data processing is further decreased by centralizing the carrier-phase observations and ambiguity parameters, as well as performing the real-time ambiguity resolution and elimination. Based on the QR factorization of the simulated matrix, we can conclude that compared to unblocked QR factorization, the blocked QR factorization can greatly improve processing efficiency with a magnitude of nearly two orders on a personal computer with four 3.30 GHz cores. Then, with 82 globally distributed stations, the processing efficiency is further validated in multi-GNSS (GPS/BDS/Galileo) satellite clock estimation. The results suggest that it will take about 31.38 s per epoch for the unblocked method. While, without any loss of accuracy, it only takes 0.50 and 0.31 s for our new algorithm per epoch for float and fixed clock solutions, respectively.