Power High Electron Mobility Transistors Research Articles

Performance improvement of enhancement-mode GaN-based HEMT power devices by employing a vertical gate structure and composite interlayers*

In this work, p-n junction vertical gate (JVG) and polarization junction vertical gate (PVG) structures are for the first time proposed to improve the performance of GaN-based enhancement-mode (E-mode) high electron mobility transistor (HEMT) devices. Compared with the control group featuring the vertical gate structure, a highly improved threshold voltage (V th) and breakdown voltage (BV) are achieved with the assistance of the extended depletion regions formed by inserting single or composite interlayers. The structure dimensions and physical parameters for device interlayers are optimized by TCAD simulation to adjust the spatial electric field distribution and hence improve the device off-state characteristics. The optimal JVG-HEMT device can reach a V th of 3.4 V, a low on-state resistance (R on) of 0.64 mΩ cm2, and a BV of 1245 V, while the PVG-HEMT device exhibits a V th of 3.7 V, an R on of 0.65 mΩ cm2, and a BV of 1184 V, which could be further boosted when an additional field plate design is employed. Thus, the figure-of-merit value of JVG- and PVG-HEMT devices rise to 2.4 and 2.2 GW cm−2, respectively, much higher than that for the VG-HEMT control group (1.0 GW cm−2). This work provides a novel technical approach to realize higher-performance E-mode HEMTs.

(Invited) Benchmarking of Beyond the State-of-the-Art Vertical GaN Devices

In this paper theoretical benchmarking of semi-vertical and vertical gallium nitride (GaN) MOSFETs with rated voltage of 1.2 kV to 3.3 kV is performed against corresponding silicon carbide (SiC) devices. Specific design features and technology requirements for realization of high voltage vertical GaN MOSFETs are discussed and implemented in simulated structures. The main findings are that a) specific on-resistance of vertical GaN devices is expected to be 75% and 40% of that for 1.2 kV and 3.3 kV SiC MOSFETs, respectively, b) semi-vertical GaN do not offer any advantage over SiC MOSFETs for medium and high voltage devices (>1.0 kV), and c) vertical GaN has largest potential advantage for high and ultra-high voltage devices (>2.0 kV).Gallium nitride (GaN) devices experience an explosive and rapid development with new device providers entering the market at an impressive speed. However, the devices are HEMT (High Electron Mobility Transistor) type lateral devices utilizing the two-dimensional electron gas (2DEG) properties of the GaN/AlGaN interface. The required GaN layers in the devices are grown epitaxially on hetero substrates like Si, SiC, sapphire and poly-AlN using buffer layers to control the strain caused by lattice mismatch which prevents the vertical current flow. For power applications the lateral current flow close to the surface leads to thermal limitations and complicates thermal management in packaging. Furthermore, it leads to large footprint of the devices for large currents. The devices also lack the robust avalanche breakdown characteristics. At present the HEMT power devices are limited to operational voltages of less than 650V with some first devices from VisIC and iGaNPower demonstrating 1200V capability. For these reasons there is an interest in the development of vertical GaN devices opening the possibilities of small footprint and thus lower cost due to smaller chip sizes, high power densities and robust avalanche breakdown characteristics with large avalanche energy capability [1]. The development of vertical devices has been hindered by the lack of large area freestanding GaN substrates facilitating homoepitaxial growth of drift layers. An alternative are semi-vertical structures grown on Si which are the subject of this study along with true vertical structures on GaN. In addition to the material issues there are technological issues that require further attention like dopant compensation and activation and Mg implantation technology for junction termination. This paper focuses on prospective benchmarking of semi-vertical and vertical GaN MOSFETs against SiC devices. A beyond the state-of-the-art benchmarking, in wide voltage range, is missing in the literature. Most of the benchmarking publications report results of experimental structures based on state-of-the-art technology and simple junction termination [2], [3], [4].The main objective of the work has been to design competitive semi-vertical and vertical GaN structures and perform benchmarking against SiC devices in the voltage range 1.2 kV to 3.3 kV. The structures have been characterized by calculating the output, transfer and voltage blocking characteristics using default Sentaurus models. In the next step, the structures have been modified based on the experience and know-how from SiC devices. The electric field crowding occurring at the trench gate corners must be mitigated both with respect to the breakdown voltage in the bulk material and the reliability of the gate dielectric [5]. Efficient junction termination (JT) is also necessary for both types of structures. This is especially important in the semi-vertical structures where junction termination is an integral part of each device segment and has a significant impact on the resulting on-state resistance. The structure design was optimized by reducing the cell pitch and introducing a multi-cell-per-device-segment design in semi-vertical structures to improve the on-resistance. Removal of the performance limitations in the structures based on the state-of-the-art GaN technology and device cell optimization was done to make benchmarking with more mature SiC devices based on the prediction of what may become feasible beyond the state-of-the-art.1. Matteo Meneghini et al., Journal of Applied Physics, vol. 130, p. 181101, 2021.2. Oka, T. Ina, Y. Ueno and J. Nishii, 2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD), pp. 303-306, 2021.3. A. Khadar, C. Liu, R. Soleimanzadeh and E. Matioli, IEEE Electron Device Letters, vol. 40, no. 3, pp. 443-446, 2019.4. Wei He et al., Nanoscale Research Letters, 17:14, 2022.5. Nakamura et al., 2011 International Electron Devices Meeting, pp. 26.5.1-26.5.3, 2011.

(Invited) Wide Bandgap Semiconductor Based Devices for Digital and Industrial Applications

Wide bandgap (WBG) semiconductor devices based on SiC, GaN and Ga2O3 provide advantages for many strategic initiatives in various industrial sectors, such as data centers, electric vehicles, renewable energy systems like solar and wind power inverters. Innovations in WBG technologies would enable new paths on energy efficiency for pushing towards sustainable perspectives. For instance, higher efficiency and lower power dissipation are always desirable for digital economy/society and power electronic applications owing to the energy saving at the end with the goal to reduce CO2 emissions.Here we will emphasize our ongoing WBG semiconductor related research/development and innovation activities, especially on GaN technology owing its rapid/huge demanding in the market nowadays. Thus, the GaN material growth, device processing/packaging and characterization/verification will be elaborated in detail in this talk.In recent years an epitaxy technique to grow large diameter GaN-on-Si wafers by coalesced nanowire has been established at RISE ProNano Lab. The GaN nanowires are epitaxially grown and then merged into a planar epitaxial film with reduced dislocation density as compared to commercially available substrates. It allows for fabrication of thick GaN layers that required for high-voltage vertical devices on Si. A 4.1-µm-thick GaN device layer on a GaN-on-Si template has been grown successfully. It has a threading dislocation density on the order 108 cm-2 and a root mean square roughness of < 0.4 nm. This result has laid the foundation for scaling to the thicker (10-12 µm) crack-free GaN drift layer on lager wafer diameters up to 200 mm.RISE has long term experience working on GaN based High Electron Mobility Transistors (HEMTs). Since 2019 we have worked on high performance and cost-competitive power HEMTs on buffer-free GaN-on-SiC wafers in frame of EU UltimateGaN project. It has focused not only on verification of the high device performance but also on its yield for revealing its competitiveness in the cost-sensitive power electronics market. The fabricated HEMTs demonstrated the expected threshold voltage, good linearity with gate length and width, Ion/Ioff ratio of 1010 as well as high output current up to 16 A with multiple fingers. In such wafer level device fabrication, different types of multi-finger HEMTs could be included with designed electrodes for flip-chip soldering them into package modules. The power module was designed and produced in house by ceramic additive manufacturing (AM), also known as three-dimensional (3D) printing. The package design has aimed to address the stringent thermal and electrical requirements of these types of HEMTs for power electronic applications. Importantly the ceramic AM package design also enables the incorporation of intricate 3D features into the package structure for achieving increased electrical isolation distance between the source and drain contact pads of the HEMT in the package.In addition, SiC and Ga2O3 based sensors/devices will be briefed in this talk, which will provide a glance for design and fabrication of the hybrid WBG components for various greener applications.

First-principles calculations of [formula omitted]-Ga2O3 /Al2O3 superlattice band structures

Ga2O3 devices are expected to be used for high-power applications such as power converters and high electron mobility transistors. To improve the device performance, band-engineering of superlattice structures consisting of Ga2O3 and Al2O3 has been of interest. Here, the bandgap dependencies of α-Ga2O3/Al2O3 superlattices on the superlattice period thickness and the lattice strain were investigated using first-principles calculations. The conduction and valence band offsets at the Ga2O3/Al2O3 interface were also examined. The bandgaps decreased with increasing superlattice period thickness, increased under compressive strain along the a- and b-axes, and decreased under tensile strain.

Design of a wideband highly efficient GaN HEMT power amplifier for multiband applications

AbstractA distributed basic matching network (MN) designed method that can achieve multioctave bandwidth and highly efficient power amplifier (PA) for multiband applications is presented in this letter. The distributed network unit with a left-rotating T-type structure is employed to construct the wideband MN, whose topology and circuit parameters are acquired through optimization. Finally, the impedance realized by the designed MN falls into the target impedance region obtained by using multi-harmonic bilateral pull technique in the desired frequency band. For the proof of the method, a broadband highly efficient PA has been designed, fabricated, and measured using commercialized GaN high electron mobility transistors (HEMT). The measured results show that the implemented PA achieves a bandwidth of 137.8% from 0.7 to 3.8 GHz. The drain efficiency is between 59% and 70% with an output power of greater than 39 dBm and a gain ranging from 9 to 12.1 dB.

Physical design guidelines to minimize area-specific ON-resistance for rated ON-current and breakdown voltage of GaN power HEMTs

In this article, we report on the development of an analytical model to estimate area-specific ON-state resistance (R ds,on) of GaN-based power high electron mobility transistor (HEMT) using rated device specifications—ON-state drain current (I ON) and maximum operating drain-to-source voltage (V DSO)—as input parameters. The rated I ON and V DSO are considered as fractions k and S, of the maximum possible drain current (I DS,max) and breakdown voltage (V BR), respectively, deliverable by the power device. The developed model is utilized to obtain the optimal physical design space parameters for a comb-like power HEMT design. Due consideration has been given to the trade-off between R ds,on and area-specific R ds,on of the transistor, device processing limitations for all the physical device parameters. The developed model has been validated with experimental results of prior literature. Our calculations impose a lower-bound for the best possible R ds,on as well as the area-specific on-resistance product (R ds,on AA) that can be obtained for a given starting channel sheet resistance in the comb architecture for a desired I ON − V DSO rating.

Mechanism of Linearity Improvement in GaN HEMTs by Low Pressure Chemical Vapor Deposition-SiN x Passivation

The mechanism of linearity improvement in AlGaN/GaN high-electron mobility transistors (HEMTs) by low pressure chemical vapor deposition (LPCVD)-SiNx passivation is verified using an asymmetric passivation structure, based on different two-dimensional electron gas (2DEG) enhancement capability between LPCVD-SiNx and SiO2 passivation grown by plasma-enhanced CVD (PECVD). The fabricated AlGaN/GaN HEMTs with a hybrid LPCVD-SiNx/PECVD-SiO2 passivation structure deliver a linearity figure of merit third-order intermodulation point (OIP3)/PDC of 4.36 dB, which is 2.84 dB higher than HEMTs with pure PECVD-SiO2 passivation. Benefiting from the charge and electric field modulation effect of the LPCVD-SINx in the source-gate access region of HEMTs, the current-dependent nonlinear source access resistance is remarkably improved, especially at high current level over 500 mA/mm and high temperature. LPCVD-SINx could be a compelling passivation for the fabrication of high linearity GaN-based power HEMTs.

Interference effects in GaN high electron mobility transistor power amplifier induced by microwave pulses

Owing to the rapid development of wireless communication, radar and pulse power technology, the electromagnetic environment faced by electronic systems is increasingly complex and the intensity of electromagnetic field can be significant. In this study, a new interference phenomenon was observed when the microwave pulses were injected into the gallium nitride (GaN) high electron mobility transistor (HEMT) power amplifier through the output port. We investigated the relationship between the peak power of reverse injection microwave pulses and the duration or the amplitude of the interference by effect experiments. The interference duration could reach the magnitude of millisecond. Deep traps in GaN HEMT power amplifiers are proved to be the cause of this interference effects.

Cumulative Hot-Electron Trapping in GaN-Based Power HEMTs Observed by an Ultrafast (10 V/Ns) On-Wafer Methodology

The goal of this article is to advance the understanding of the impact of hard switching on the dynamic performance of GaN-based high electron mobility transistors (HEMTs). To this aim, we developed a fast (10 V/ns) on-wafer system for testing devices in hard switching. The system has been used to study the reliability of several <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$W_{G}=2$ </tex-math></inline-formula> mm p-type GaN HEMTs with different <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$L_{\text {GD}}$ </tex-math></inline-formula> or buffer properties. First, we show that by optimizing the drain node capacitance, we can speed up the hard-switching transition to a few ns, even on-wafer level. Second, repeating the experiment by using multiple frequencies, from 1 to 100 kHz, we demonstrate that, in real-world applications, cumulative turn-on stress has a much stronger effect on <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$R_{\mathrm {ON}}$ </tex-math></inline-formula> compared with OFF-state stress. Third, by comparing the results on identical devices having shorter <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$L_{\text {GD}}$ </tex-math></inline-formula> , we pinpoint hot electrons as the main mechanism in the device degradation, ruling out the contribution of self-heating. Finally, by comparing three wafers with different processing conditions (different passivation, different buffer), we suggest that trapping phenomena related to hot electrons happen in ns time scale and that the properties of the buffer can significantly impact the dynamic performance of the devices in hard switching.

An Integrated GaN Overcurrent Protection Circuit for Power HEMTs Using SenseHEMT

GaN power high-electron-mobility transistors (HEMTs), with their fast switching transients and poor overcurrent tolerance, require overcurrent protection (OCP) circuits that can respond in under <inline-formula><tex-math notation="LaTeX">$\text{0.5}\, \mu \text{s}$</tex-math></inline-formula>. Monolithically integrating digital and analog circuits with GaN power devices is enabled by recent advancements in high-voltage GaN integrationplatforms. Thus, integrated OCP designs can be used to reduce the protection response time, the area penalty, and the assembly complexity. This work presents the first fully integrated, senseHEMT-based GaN OCP integrated circuit (IC) with an adjustable current limit and programmable blanking time, suitable for a wide range of power applications. The IC, implemented on a 200-V GaN-on-Silicon-on-Insulator (GaN-on-SOI) process, contains a power HEMT with a senseHEMT for current sensing, a totem-pole-based gate driver, an analog comparator, and a set of logic circuits to enable high-speed closed-loop OCP. The fabricated design is tested in both a clamped switching setup and a 12&#x2013;48 V boost converter. The minimum OCP response time is estimated to be 36 ns with <inline-formula><tex-math notation="LaTeX">$dI_{D}/dt\geq \text{30}\,\text{A}/\mu \text{s}$</tex-math></inline-formula>, one of the fastest amongst state-of-the-art OCP circuits for GaN.

The Effect of Heavy Fe-Doping on 3D Growth Mode and Fe Diffusion in GaN for High Power HEMT Application.

The high electron mobility transistor (HEMT) structures on Si (111) substrates were fabricated with heavily Fe-doped GaN buffer layers by metalorganic chemical vapor deposition (MOCVD). The heavy Fe concentrations employed for the purpose of highly insulating buffer resulted in Fe segregation and 3D island growth, which played the role of a nano-mask. The in situ reflectance measurements revealed a transition from 2D to 3D growth mode during the growth of a heavily Fe-doped GaN:Fe layer. The 3D growth mode of Fe nano-mask can effectively annihilate edge-type threading dislocations and improve transfer properties in the channel layer, and consequently decrease the vertical leakage current by one order of magnitude for the applied voltage of 1000 V. Moreover, the employment of GaN:C film on GaN:Fe buffer can further reduce the buffer leakage-current and effectively suppress Fe diffusion.

Comparison of the parasitic impedances from the drain‐source path of power transistor packages at up to 2 GHz

AbstractIn this article, we compare several concepts for gallium‐nitride (GaN) power high electron mobility transistor (HEMT) packages in terms of their drain‐to‐source parasitic inductance and resistance values. Unlike in previous studies, however, due to several fast transient use cases the investigated frequencies are extended to 2 GHz. Since the device's dimensions are already a significant fraction of the corresponding wavelength at 2 GHz, full wave simulation tools have been employed to more accurately assess the problem. The results reveal how the considered package concepts affect the overall parasitic device impedances and show a clear improvement of the parasitic impedance over each generation of package implementation. Furthermore, full wave analysis results are compared to method of moments results to emphasize the necessity of full wave simulations at these frequencies.

Fabrication and characterization of AlGaN/GaN HEMTs with high power gain and efficiency at 8 GHz

State-of-the-art AlGaN/GaN high electron mobility structures were grown on semi-insulating 4H-SiC substrates by MOCVD and X-band microwave power high electron mobility transistors were fabricated and characterized. Hall mobility of 2291.1 cm2/(V·s) and two-dimensional electron gas density of 9.954 × 1012 cm–2 were achieved at 300 K. The HEMT devices with a 0.45-μm gate length exhibited maximum drain current density as high as 1039.6 mA/mm and peak extrinsic transconductance of 229.7 mS/mm. The f T of 30.89 GHz and f max of 38.71 GHz were measured on the device. Load-pull measurements were performed and analyzed under (–3.5, 28) V, (–3.5, 34) V and (–3.5, 40) V gate/drain direct current bias in class-AB, respectively. The uncooled device showed high linear power gain of 17.04 dB and high power-added efficiency of 50.56% at 8 GHz when drain biased at (–3.5, 28) V. In addition, when drain biased at (–3.5, 40) V, the device exhibited a saturation output power density up to 6.21 W/mm at 8 GHz, with a power gain of 11.94 dB and a power-added efficiency of 39.56%. Furthermore, the low f max/f T ratio and the variation of the power sweep of the device at 8 GHz with drain bias voltage were analyzed.

On the operating speed and energy efficiency of GaN-based monolithic complementary logic circuits for integrated power conversion systems

Gallium nitride (GaN)-based power conversion systems exhibit striking competitiveness in realizing compact and high-efficiency power management modules. Recently emerging GaN-based p-channel field-effect transistors (FETs) and monolithic integration techniques enable the implementation of GaN-based complementary logic (CL) circuits and thereby offer an additional pathway to improving the system-level energy efficiency and functionality. In this article, holistic analyses are conducted to evaluate the potential benefits of introducing GaN CL circuits into the integrated power systems, based on the material limit of GaN and state-of-the-art experimental results. It is revealed that the propagation delay of a single-stage CL gate based on the commercial p-GaN gate power HEMT (high-electron-mobility transistor) platform could be as short as sub-nanosecond, which sufficiently satisfies the requirement of power conversion systems typically with operating frequencies less than 10 MHz. With the currently adopted n-FET-based logic gates (e.g., directly coupled FET logic) replaced by CL gates, the power consumption of peripheral logic circuits could be substantially suppressed by more than 103 times, mainly due to the elimination of the pronounced static power loss. Consequently, the energy efficiency of the entire system could be substantially improved.

A 50 W dual‐band high‐efficiency gallium nitride high electron mobility transistor power amplifier with three‐stage L‐type DC bias circuit at 1.8 and 2.6 GHz

AbstractA 50 W dual‐band high‐efficiency gallium nitride (GaN) high electron mobility transistor (HEMT) power amplifier with a three‐stage L‐type DC bias circuit capable of individually adjusting second‐harmonic impedances is proposed for 1.8 and 2.6 GHz frequencies. The output network of this power amplifier is composed of an output matching network comprising five‐stage transmission lines and a three‐stage L‐type DC bias circuit with three L‐type circuits and one transmission line. The one‐stage L‐type circuit comprises a series transmission line and a quarter‐wavelength open‐ended shunt stub. For the high‐efficiency performance of the power amplifier, the output matching network is matched to the optimum impedances of the fundamental frequencies, and the DC bias circuit optimizes the impedances individually at the second‐harmonic frequencies without affecting the matched fundamental frequency impedances in the output matching network. Measured results show that the proposed dual‐band GaN HEMT power amplifier achieved gains of 15.6 and 13.8 dB as well as maximum power‐added efficiencies of 70.5% and 66.3% with 47 dBm output power at 1.8 and 2.6 GHz, respectively.

On the Modeling of the Donor/Acceptor Compensation Ratio in Carbon-Doped GaN to Univocally Reproduce Breakdown Voltage and Current Collapse in Lateral GaN Power HEMTs.

The intentional doping of lateral GaN power high electron mobility transistors (HEMTs) with carbon (C) impurities is a common technique to reduce buffer conductivity and increase breakdown voltage. Due to the introduction of trap levels in the GaN bandgap, it is well known that these impurities give rise to dispersion, leading to the so-called “current collapse” as a collateral effect. Moreover, first-principles calculations and experimental evidence point out that C introduces trap levels of both acceptor and donor types. Here, we report on the modeling of the donor/acceptor compensation ratio (CR), that is, the ratio between the density of donors and acceptors associated with C doping, to consistently and univocally reproduce experimental breakdown voltage (VBD) and current-collapse magnitude (ΔICC). By means of calibrated numerical device simulations, we confirm that ΔICC is controlled by the effective trap concentration (i.e., the difference between the acceptor and donor densities), but we show that it is the total trap concentration (i.e., the sum of acceptor and donor densities) that determines VBD, such that a significant CR of at least 50% (depending on the technology) must be assumed to explain both phenomena quantitatively. The results presented in this work contribute to clarifying several previous reports, and are helpful to device engineers interested in modeling C-doped lateral GaN power HEMTs.

Resonances on GaN-on-Si Epitaxies: A Source of Output Capacitance Losses in Power HEMTs

GaN-on-Si high-electron-mobility transistors (HEMTs) exhibit excellent properties for efficient power conversion. Nevertheless, a considerable energy loss associated with the charging and discharging of the output capacitance ( C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OSS</sub> ) in these transistors severely limits their application at high switching frequencies. In this work we report the observation of unexpected resonances in GaN-on-Si HEMTs. These high-frequency resonances lead to considerable energy losses in fast charging and discharging of the C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OSS</sub> during switching transients. We propose a simple wafer-level measurement technique to evaluate such losses at the epitaxy level, prior to the transistor fabrication. Experimental results from this technique revealed that the Silicon substrate is the main origin of these losses. Such wafer-level evaluation of C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> OSS</sub> losses opens opportunities to characterize and optimize epitaxies for future power devices, especially those operating at high switching frequencies.

Analysis of Instability Behavior and Mechanism of E-Mode GaN Power HEMT with p-GaN Gate under Off-State Gate Bias Stress

In this study, we investigate the degradation characteristics of E-mode GaN High Electron Mobility Transistors (HEMTs) with a p-GaN gate by designed pulsed and prolonged negative gate (VGS) bias stress. Device transfer and transconductance, output, and gate-leakage characteristics were studied in detail, before and after each pulsed and prolonged negative VGS bias stress. We found that the gradual degradation of electrical parameters, such as threshold voltage (VTH) shift, on-state resistance (RDS-ON) increase, transconductance max (Gm, max) decrease, and gate leakage current (IGS-Leakage) increase, is caused by negative VGS bias stress time evolution and magnitude of stress voltage. The significance of electron trapping effects was revealed from the VTH shift or instability and other parameter degradation under different stress voltages. The degradation mechanism behind the DC characteristics could be assigned to the formation of hole deficiency at p-GaN region and trapping process at the p-GaN/AlGaN hetero-interface, which induces a change in the electric potential distribution at the gate region. The design and application of E-mode GaN with p-GaN gate power devices still need such a reliability investigation for significant credibility.

Small- and Large-Signal Dynamic Output Capacitance and Energy Loss in GaN-on-Si Power HEMTs

The origin of C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">oss</sub> and the energy dissipation due to output capacitance can be roughly separated into two types: resistive loss and capacitive hysteresis loss. The resistive losses are due to the resistance of gallium nitride (GaN) buffer layers and Si-substrate. These loss components can be potentially improved by reengineering the doping concentrations in the buffer stacks and substrate layer. However, the capacitive hysteresis loss that is suspected to be due to trapping dynamics remains largely unexplained. This article presents a physics view of the trapping dynamics related to C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">oss</sub> in the GaN high-electron-mobility transistor (HEMT) under small- and large-signal excitations. It is observed that, under large-signal excitation, traps with shallow energy levels (in the range of 0.5 eV above valence band) are mostly responsible for the charge imbalance and energy dissipation. Under small-signal conditions, deep traps with an energy level of around 0.98 eV from the valence band are the causes for the hysteresis at dc. By identifying dominating types of traps and relevant trap energy levels in GaN HEMT, we can gain important insights on how to optimize the device stack design for high-frequency applications.

Recent Advances in GaN‐Based Power HEMT Devices

AbstractThe ever‐increasing power density and operation frequency in electrical power conversion systems require the development of power devices that can outperform conventional Si‐based devices. Gallium nitride (GaN) has been regarded as the candidate for next‐generation power devices to improve the conversion efficiency in high‐power electric systems. GaN‐based high electron mobility transistors (HEMTs) with normally‐off operation is an important device structure for different application scenarios. In this review, an overview of a series of effective approaches to improve the performance of GaN‐based power HEMT devices is given. Modified epistructures are presented to suppress defects and current leakage, and low‐damage recess‐free processes are discussed in fabricating normally‐off HEMTs. Possible effects of dielectrics on a metal–insulator–semiconductor (MIS) structure are also intensively introduced. Metal/semiconductor contact engineering is investigated, and fabrication of Au‐free ohmic contact and graphene insertion layer to enhance the device performance is emphasized. Finally, the effects of field plates are studied through the use of simulated and fabricated devices.