Power HFETs Research Articles

New Approaches to Realizing High Power Nitride Based Field Effect Transistors

High breakdown voltage, excellent current carrying capabilities, high electron saturation velocity, high mobility, good thermal properties, chemical inertness, and radiation hardness of nitride semiconductors make them uniquely suited for high power applications. However, new approaches are needed to achieve their full potential. We report on several key innovations that include (1) the use of Perforated Channel (PC) design (to control and minimize the parasitic and on resistances and off and on transistor capacitances for faster switching and sharply reduced losses); (2) surface application of Low Conducting Layers (LCLs) (to control the properties and stability of ungated surfaces and dramatically increase the breakdown voltage); (3) the combination of these two approaches (for achieving the ultimate power performance at the highest switching frequencies with minimum losses); (4) novel device geometries (combining the best features of lateral and vertical devices for normally-off transistors with unprecedented power handling capability); (5) improved control of self-heating and better heat dissipation using the PC channel design. We also review our recent results exploring the PC channel and LCL designs [1-3]. These experimental and simulation results demonstrated a sharp increase in the breakdown voltage, a large enhancement of the cutoff frequency, a better device stability and smaller spreading of the device parameters for higher yield, improved manufacturability, and smaller self-heating due to a lower thermal impedance.[[1]] G. Simin, M. Islam, M. Gaevski, J. Deng, R. Gaska, and M. Shur, “Low RC-constant Perforated-Channel HFET”, IEEE Electron Device Letters, 35 (2014)[2] M. Gaevski, Jianyu Deng, A. Dobrinsky, R. Gaska, M. Shur, and G. Simin, Static and transient characteristics of GaN power HFETs with low-conducting coating, physica status solidi, Article first published online: 24 MAR 2014 | DOI: 10.1002/pssc.201300541[3] G Simin, M Shur, R Gaska, Semiconductor device with low-conducting buried and/or surface layers - US Patent Application 20,130,126,905 (2013)

Static and transient characteristics of GaN power HFETs with low‐conducting coating

AbstractWe report on a design of GaN based HFET with a low‐conducting layer (LCL) coating. The LCL coating dramatically improves the electric field uniformity and increases the breakdown voltage. A major advantage is consistent control of the breakdown characteristics, which is expected to dramatically improve yield and reliability. Initial experimental studies demonstrated a three‐fold increase in the breakdown voltage compared with conventional HFETs. The LCL also leads to a much more uniform underlying channel depletion evidenced by a significantly lower HFET channel capacitance in the off state for the HFET based RF switches. This results in a lower loss and higher isolation. Another advantage is a faster transient enabled by LCL, which should improve efficiency and reduce loss for power HFET switches.(© 2014 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

Effects of SiN passivation and high-electric field on AlGaN-GaN HFET degradation

The authors report on the effects of silicon nitride (SiN) surface passivation and high-electric field stress (hot electron stress) on the degradation of undoped AlGaN-GaN power HFETs. Stressed devices demonstrated a decrease in the drain current and maximum transconductance and an increase in the parasitic drain series resistance, gate leakage, and subthreshold current. The unpassivated devices showed more significant degradation than SiN passivated devices. Gate lag phenomenon was observed from unpassivated devices and removed by SiN passivation. However, SiN passivated devices also showed gate lag phenomena after high-electric field stress, which suggests possible changes in surface trap profiles occurred during high-electric field stress test.

High performance BCB-bridged AlGaAs/InGaAs power HFETs

A novel low-k benzocyclobutene (BCB) bridged and passivated layer for AlGaAs/InGaAs doped-channel power field effect transistors (FETs) with high reliability and linearity has been developed and characterized. In this study, we applied a low-k BCB-bridged interlayer to replace the conventional air-bridged process and the SiN/sub x/ passivation technology of the 1 mm-wide power device fabrication. This novel and easy technique demonstrates a low power gain degradation under a high input power swing, and exhibits an improved adjacent channel power ratio (ACPR) than those of the air-bridged one, due to its lower gate leakage current. The power gain degradation ratio of BCB-bridged devices under a high input power operation (P/sub in/ = 5 /spl sim/ 10 dBm) is 0.51 dB/dBm, and this value is 0.65 dB/dBm of the conventional air-bridged device. Furthermore, this novel technology has been qualified by using the 85-85 industrial specification (temperature = 85 C, humidity = 85%) for 500 h. These results demonstrate a robust doped-channel HFET power device with a BCB passivation and bridged technology of future power device applications.

Physical investigation of trap-related effects in power HFETs and their reliability implications

This paper presents a detailed physical investigation of trapping effects in GaAs power HFETs. Two-dimensional numerical simulations, performed using a hydrodynamic model that includes impact ionization, are compared with experimental results of fresh as well as hot-carrier-stressed HFETs in order to gain insight of intertwined phenomena such as the kink in the dc output curves, the hot-carrier degradation of the drain current, and the impact-ionization-dominated reverse gate current. Thoroughly consistent results show that: 1) the kink effect is dominated by the traps at the source-gate recess surface; and 2) as far as the hot-carrier degradation is concerned, only a simultaneous increase of the trap density at the drain-gate recess surface and at the channel-buffer interface (again at the drain side of the channel) is able to account for the simultaneous decrease of the drain current and the increase of the impact-ionization-dominated reverse gate current.

High-electric-field effects and degradation of AlGaAs/GaAs power HFETs: a numerical study

This work presents a numerical study of high-field degradation and reliability issues of AlGaAs/GaAs power HFETs. A commercial two-dimensional drift–diffusion tool is used to investigate electric-field distributions, the effects of electron capture at the device surface under hot-carrier conditions, and the impact of drain recess scaling on such effects. Wherever experimental data are available for direct comparison, a good match is observed with our simulations. The main results of this study are (1) a validation of the hypothesis that attributes the main high-field degradation effects to electron capture over the gate–drain access region, and (2) design indications pointing out to the possibility of a reverse correlation between the gate–drain breakdown voltage and the device hot-carrier reliability.

Electric-field-related reliability of AlGaAs/GaAs power HFETs: bias dependence and correlation with breakdown

This work shows experimental and simulated data of hot electron degradation of power AlGaAs/GaAs HFETs with different gate lengths and recess widths, and uses them to infer general indications on the bias and geometry dependence of the device high-field degradation, the meaningfulness of the breakdown voltage figure of merit from a reliability standpoint, and the physical phenomena taking place in the devices during the stress and leading to performance degradation. Possible formulations of a voltage-acceleration law for lifetime extrapolation are also tested.