Power HFET Research Articles

High Efficiency and High Output Power HFET GaN Doherty Power Amplifier with Linearity Region Extension for Wireless Applications

High Efficiency and High Output Power HFET GaN Doherty Power Amplifier with Linearity Region Extension for Wireless Applications

Static and transient characteristics of GaN power HFETs with low‐conducting coating

AbstractWe report on a design of GaN based HFET with a low‐conducting layer (LCL) coating. The LCL coating dramatically improves the electric field uniformity and increases the breakdown voltage. A major advantage is consistent control of the breakdown characteristics, which is expected to dramatically improve yield and reliability. Initial experimental studies demonstrated a three‐fold increase in the breakdown voltage compared with conventional HFETs. The LCL also leads to a much more uniform underlying channel depletion evidenced by a significantly lower HFET channel capacitance in the off state for the HFET based RF switches. This results in a lower loss and higher isolation. Another advantage is a faster transient enabled by LCL, which should improve efficiency and reduce loss for power HFET switches.(© 2014 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

Performance stability of AlGaN/GaN HFET: effect of plasma processing

AbstractEffect of fluoride‐based plasma treatment on performance stability of AlGaN/GaN HFET was systematically investigated. The plasma‐based processes can introduce different type of damage that can be permanent or temporary, depending on electrical field in the device, plasma density, and energy of radicals and total process thermal budget. In order to understand more clearly the mechanism of fluorine based plasma treatment on device performance, we compare the effects of Ar, O2 and CF4 based plasma treatments applied before gate definition. Ar plasma was chosen for comparison with CF4 because of high ionization rate of Ar and chemically neutral behavior of Ar ions. Under the same medium range of 40 V DC bias in RIE system for these two gases, the shift of drain current and threshold voltage was similar that indicate the common mechanism of plasma damage. We supposed that the major effect for this phenomenon is a negative electron charge inserted in semiconductor during plasma treatment, because at the same accelerated field the penetration depth for electrons is higher than the penetration depth for fluoride ions. Devices stressed under impact ionization conditions show an improvement of breakdown voltage (for O2 plasma treatment) and some recovery of threshold voltage similar to “walkout effect”. This performance non‐stability raise the serious concern about application of fluorine based technology for power applications, where large voltage/current swing may push device to the impact ionization region. The experimental results show that the implementation of fluoride based plasma treatment for power device manufacturing can affect the performance stability of AlGaN/GaN power HFET. (© 2008 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

Hot electron induced degradation of undoped AlGaN/GaN HFETs

This work presents the effects of hot electron stress on the degradation of undoped Al 0.3GaN 0.7/GaN power HFET’s with SiN passivation. Typical degradation characteristics consist of a decrease in the drain current and maximum transconductance, an increase in the drain series resistance, gate leakage and a subthreshold current. Degradation mechanism has been investigated by means of gate lag measurements (pulsed I– V) and current-mode deep level transient spectroscopy (DLTS). Stressed devices suffered from aggravated drain current slump (DC to RF dispersion) which indicates possible changes in surface charge profiles occurred during hot electron stress test. The DLTS was used to identify the trap creation by hot electron stress. The DLTS spectra of stressed device revealed the evidence of trap creation due to hot electron stress.

Gate-lag effects in AlGaAs/GaAs power HFET's

Gate-lag effects in AlGaAs/GaAs power HFET's

Hot electron effects on Al/sub 0.25/Ga/sub 0.75/As/GaAs power HFET's under off-state and on-state electrical stress conditions

This work shows a detailed comparison of the degradation modes caused by off-state and on-state room temperature electrical stress on the DC characteristics of power AlGaAs/GaAs heterostructure field effect transistors (HFET's) for X- and Ku-band applications. The devices are stressed under DC bias conditions that result in electron heating and impact ionization in the gate-drain region. Incremental stress experiments carried out at gate-drain reverse currents up to 3.3 mA/mm (for a total of more than 700 h) show a remarkably larger degradation for the off state stress, due to more pronounced electron heating at any fixed value of gate reverse current. This represents an important piece of information for the reliability engineer when it comes to designing the accelerated stress experiments for hot electron robustness evaluation. The degradation modes observed, all of a permanent nature, include threshold voltage and drain resistance increase and drain current and transconductance reduction.

Degradation of power HFET's under on-state and off-state breakdown conditions

This work shows a detailed comparison of the degradation caused by off-state and on-state breakdown conditions in power AlGaAsGaAs HFET's. Stress experiments carried out at gate-drain reverse currents up to 3.3 mA/mm (for a total of more than 700 h) show a remarkably larger degradation for the off-state stress, due to more pronounced electron heating at any fixed value of gate reverse current. The degradation modes include VT and RD increase and lDSS and gm reduction.

Self-aligned emitter power HBT and self-aligned gate power HFET for low/unity supply voltage operation in PHS handsets

A new power HBT and HFET were developed for low unity supply voltage operation in PHS handsets. The emitter region, the emitter electrode, the buried collector and the base electrodes in the power HBT are formed using the emitter electrode self-alignment process in order to reduce parasitic resistance and capacitance. The wirings on each electrode of the HBT are formed by Au plating technique for high current operation. The gate electrode in the power HFET is self-aligned to the drain/source electrodes by using the drain/source contact mesas as a mask, where the distance between the drain and the source is minimized and the parasitic resistances are reduced. In addition, an asymmetrical double-doped structure of AlGaAs/GaAs/InGaAs/AlGaAs is applied to the HFET in order to obtain a high current density. Both the power HBT and HFET exhibited the knee voltage less than 1 V with the maximum current more than 500 mA. The power HBT performed a power gain of 14.2 dB, an efficiency of 33.8% and the power HFET performed 12.5 dB and 34.5%, with a sufficient margin of distortion for PHS standard at an output power of 22 dBm, a supply voltage of 3.5 V and a frequency of 1.9 GHz under the unity operation.

High breakdown voltage InGaAs/InAlAs HFET using In0.5Ga0.5P spacer layer

A highly strained In0.5Ga0.5P spacer is introduced into an HFET grown by MOVPE on InP substrate for the first time. Despite the large lattice mismatch and the group V exchange at the channel-spacer interface the transport data are not affected (µH, 300K = 11 300 cm2/Vs, ns = 2 x 1012 cm-2). However the large bandgap energy of InGaP results in improved gate leakage, drain-conductance and drain breakdown. At VDS = 10 V a voltage gain of vu > 100 is maintained. HFETs with Lg = 0.7µm exhibit gm = 360 mS/mm, ID, max(VDS = 6V) = 550 mA/mm and a cutoff frequency fmax of 150 GHz. At VDS = 5.5V an AC output power of 0.6 W/mm is achieved indicating the capability for high power HFET application on InP substrates.