Power Gating Design Research Articles

Addressing Power Efficiency and Stability in SRAM: A 4x4 Cell Array Design with Enhanced Power Gating

In order to lower power consumption and leakage currents during active operation, the suggested SRAM architecture with power gating design trims the source voltage across the SRAM cell, ranging from 50 to 150 mV. Power gating based on sectors is utilized, using a self-biasing approach where the gate terminal and source of a PMOS transistor act as a diode, controlling the virtual ground. However, three challenges arise with this method in nanometer technology: the additional self- biasing transistor (SBT) occupies 5% more space, the source voltage adjustment mechanisms are not effectively implemented, and the increase in virtual ground voltage leads to bias temperature instability. To implement this design, a 4x4 SRAM cell array is constructed, consisting of 4 rows and 4 columns of 10T SRAM cells. A decoder addresses these cells, and each row represents half a byte, with control circuitry managing input and output data. Additionally, the outputs of individual cells in each column are combined using a 4-bit OR, producing a single data output point. This architecture effectively reduces power consumption while maintaining operational efficiency, making it suitable for nanometer-scale SRAM designs.

Performance Analysis of Power Gating designs in Low Power VLSI Circuits

Performance Analysis of Power Gating designs in Low Power VLSI Circuits

REE: Reconfigurable and energy-efficient router architecture in wireless network-on-chip

Currently, on-chip routers consume the majority of the power budget. Moreover, the static power consumption has taken up a significant fraction of the total power consumption in the router. Especially in the light traffic state, the router idle time is notable, but fragmented owing to the impact of some burst traffic, increasing the challenge of reducing static power consumption through power gating. In this paper, a reconfigurable and energy-efficient router architecture design (REE) is proposed: bypass connections are set for routers, and deflection rules are formulated to ensure that routers maintain connectivity in the network under power gating situation, and reduce the deflection rate of packets encountering sleeping routers. Meanwhile, a reusable predictor is introduced to efficiently predict the idle time to wake up the sleeping router appropriately. In addition, the fine-grained power gating (PG) design is introduced in the wireless interface of wireless routers (WRs) to obtain the scheme REE+, which reduces the idle time of transmitter (TX) components and effectively saves the static power consumption of Wireless Interface. Experiments demonstrate that both the REE and REE + schemes in this paper have negligible impact on latency as well as throughput, while the energy savings are significant: 64.5% and 68.3% average static power savings for REE and REE + schemes, respectively, compared to No_PG, and 13.7% and 20.5% average improvement in terms of static power saving compared to Turn-on on Turn (TooT), respectively.

NBTI-Aware Power Gating Design with Dynamically Varying Stress Probability Control on Sleep Transistor

With the aggressive scaling of the transistor, Negative Bias Temperature Instability (NBTI) has become the most dominant aging effect which causes the device parameter to degrade over its lifetime. This device parameter degradation of logic gates in nanometer technology is a major concern for the reliability of the digital circuit. It becomes even more critical when it comes to power gating structure, as small NBTI effect on PMOS sleep transistor used in header-based power gating structure would seriously affect the reliability, performance of the whole logic circuit. The conventional method of mitigating the NBTI effect is to oversize the sleep transistor, but it also gives rise to leakage overhead. In this work, a novel NBTI aware power gating architecture is presented to improve the lifetime of the circuit. Here, sleep transistors (STs) are switched ON/OFF periodically and a greater number of STs are turned ON, when NBTI related degradation reaches to its threshold value so that STs get more time to anneal NBTI degradation and improve its lifetime. Simulation result on ISCAS’85 benchmark circuits shows for 40% sleep signal, an average of 51.2% and 14% lifetime improvement with respect to the conventional over-sizing (OS) technique and normal stress probability control method, respectively with some power and area overhead.

NVLCFF: An Energy-Efficient Magnetic Nonvolatile Level Converter Flip-Flop for Ultra-Low-Power Design

Power dissipation has become a major concern in nanoscale integrated circuits. The power gating and dual-supply design methods are among the most effective approaches for reducing the static and dynamic power consumptions. However, these methods require efficient data retention and voltage level conversion. In this paper, a nonvolatile level converter flip-flop (NVLCFF) is proposed to be used in ultra-low-power integrated circuits. Our proposed NVLCFF employs the magnetic tunnel junction (MTJ) for data retention. Spin transfer torque along with the spin Hall effect is used for reconfiguring the MTJs. The peripheral circuitry is designed using 7-nm FinFET as one of the leading industrial technologies. Furthermore, to facilitate the use of the dual-supply approach, voltage level conversion is performed in the structure of the proposed NVLCFF. According to the HSPICE simulations, the power consumption, backup energy and restore energy of the proposed circuit are on average 59%, 48% and 92% lower than the other NVLCFFs based on the previous nonvolatile flip-flops with different MTJ structures. Furthermore, the comprehensive Monte Carlo simulations indicate the robustness of the proposed design in the presence of major MTJ and FinFET process variations as compared to the previous designs.

LOW LEAKAGE CHARGE RECYCLING TECHNIQUE FOR POWER MINIMIZATION IN CNTFET CIRCUITS

Carbon Nanotube Field Effect Transistor (CNTFET) is one of the most promising candidates in the near future for digital design due to its better electrostatics and higher mobility characteristics. Parameters that determine the CNTFET performance are the number of tubes, pitch, diameter and oxide thickness. In this paper, a power gating design methodology to realise low power CNTFET digital circuits even under device parameter changes is presented. Investigation about the effect of different CNTFET parameters on dynamic and standby power is carried out. Simulation results reveal that the power gated circuits suppress a maximum of about 67% dynamic power and 59% standby power compared to conventional circuits.

Leakage Current Analysis for Diagnosis of Bridge Defects in Power-Gating Designs

Manufacturing defects that do not affect the functional operation of low power integrated circuits (ICs) can nevertheless impact their power saving capability. We show that stuck-ON faults on the power switches and resistive bridges between the power networks can impair the power saving capability of power-gating designs. For quantifying the impact of such faults on the power savings of power-gating designs, we propose a diagnosis technique that targets bridges between the power networks. The proposed technique is based on the static power analysis of a power-gating design in stand-by mode and it utilizes a novel on-chip signature generation unit, which is sensitive to the voltage level between power rails, the measurements of which are processed off-line for the diagnosis of bridges that can adversely affect power savings. We explore, through SPICE simulation of the largest IWLS’05 benchmarks synthesized using a 32 nm CMOS technology, the tradeoffs achieved by the proposed technique between diagnosis accuracy and area cost and we evaluate its robustness against process variation. The proposed technique achieves a diagnosis resolution that is higher than 98.6% and 97.9% for bridges of ${R}~{\gtrsim }~{10~{ M}\Omega }$ (weak bridges) and bridges of ${R~\lesssim~10~{ M}\Omega }$ (strong bridges), respectively, and a diagnosis accuracy higher than 94.5% for all the examined defects. The area overhead is small and scalable: it is found to be 1.8% and 0.3% for designs with 27 K and 157 K gate equivalents, respectively.

Coarse-Grained Online Monitoring of BTI Aging by Reusing Power-Gating Infrastructure

In this paper, we present a novel coarse-grained technique for monitoring online the bias temperature instability (BTI) aging of circuits by exploiting their power gating infrastructure. The proposed technique relies on monitoring the discharge time of the virtual-power-network during standby operations, the value of which depends on the threshold voltage of the CMOS devices in a power-gated design (PGD). It does not require any distributed sensors, because the virtual-power-network is already distributed in a PGD. It consists of a hardware block for measuring the discharge time concurrently with normal standby operations and a processing block for estimating the BTI aging status of the PGD according to collected measurements. Through SPICE simulation, we demonstrate that the BTI aging estimation error of the proposed technique is less than 1% and 6.2% for PGDs with static operating frequency and dynamic voltage and frequency scaling, respectively. Its area cost is also found negligible. The power gating minimum idle time (MIT) cost induced by the energy consumed for monitoring the discharge time is evaluated on two scalar machine models using either x86 or ARM instruction sets. It is found less than $1.3\times $ and $1.45\times $ the original power gating MIT, respectively. We validate the proposed technique through accelerated aging experiments conducted with five actual chips that contain an ARM cortex M0 processor, manufactured with a 65 nm CMOS technology.

Transistor level realisation of power gated FSM

Power can be minimised for the power gated finite state machine (FSM) by suitable partitioning and encoding strategy. Power gating architecture designed previously at FSM level is hypothetical one and may not directly be used for practical implementation of power gated circuit in transistor level. Most of the previous works concern about power reduction of combinational parts only. In this work, a new architecture of power gating design which implements sequential circuit in transistor level has been proposed and considers power consumption of combinational as well as sequential parts. The sequential circuits are obtained after concurrent bi-partitioning and encoding of FSM benchmark circuit. Multi-level realisation of two-level PLA circuit has been done. The architecture is designed such that at a time combinational circuits corresponding to one sub-FSM is power gated by shutting-OFF power supply. Power gating technique in this work shows leakage saving of 47% and total power saving of 53.6%.

An Efficient and Effective Methodology to Control Turn-On Sequence of Power Switches for Power Gating Designs

As technology advances, power consumption becomes a big challenge in modern very large-scale integration designs. To resolve this problem, power-gated technology has been widely adopted in circuit designs. Since the turn-on sequence of power switches has a great impact on the rush current, wake-up, and sequence times of a power gating design, this paper proposes a methodology to construct a hybrid routing structure to connect power switches. Our hybrid routing structure can induce less rush current and satisfy timing constraints because a better daisy chain is constructed. To find members of the daisy chain, an integer linear programming algorithm is used to pick up suitable power switches. To determine suitable depth of a daisy chain, we propose a model for a power gating design and induct precise equations to estimate voltage and rush current equations according to the model. All of our experiments are based on industrial designs and measured by vendor tools. The experimental results demonstrate the efficiency and effectiveness of our design methodology.

파워 게이팅 설계에서 IR Drop에 견고한 셀 배치 방법

파워 게이팅은 반도체 칩의 누설전류(leakage current)를 감소시키는 데 효과적인 기술로 알려져 있으며, 전원 차단용 파워 게이팅 셀 (power-gating cell, PGC)에서의 IR drop 증가로 인한 성능 및 신뢰성 저하에 대해 많은 연구가 이루어져왔다. 그러나 최신 공정에서는 트랜지스터 사이즈 감소 추세에도 불구하고 금속 배선의 스케일링이 제한됨에 따라, IR drop에 견고한 파워 게이팅 설계 시 셀 배치와 금속 배선 면적을 고려한 새로운 접근 방식이 필요하다. 본 논문에서는 셀 점유율(cell utilization)과 소모 전류에 근거한 로직 셀 배치 기법을 통해 PGC 면적 및 IR drop을 개선한 파워 게이팅 설계 방법을 제안한다. 28nm 공정으로 제조된 스마트폰용 어플리케이션 프로세서(Application processor, AP) 내 고속 디지털 코어에 적용한 결과 기존 PGC 배치 기법 대비 PGC 면적은 12.59∼16.16%, 최대 IR drop은 8.49% 감소함을 확인하였다.

Hybrid Approach of Within-Clock Power Gating and Normal Power Gating to Reduce Power

Power gating (PG) is used to reduce leakage power by shutting down the power supply of the inactive block of the circuit. PG technique for finite state machine (FSM) is used to reduce not only leakage power but also the switching power of circuit. One FSM is partitioned into two sub-FSMs and encoded for minimizing total power for the power-gated design of the circuit. Depending on the state of the machine, at a time one sub-FSM is power gated by shutting off the power supply. There is a complete eradication of power in power-gated sub-FSM, but another one is in an active mode that continues to dissipate power. There is a scope to reduce leakage in active sub-FSM if the clock period is larger than the critical path delay of the combinational part of this sub-FSM. In this condition, there is a certain portion of the clock period which is idle and in this period PG may be used. The objective of this paper is to reduce power by applying PG at circuit level to the active sub-FSM, whereas, inactive sub-FSM is still power gated. This paper presents a new technique, called WCPG_IN_PG, which reduces the power of active sub-FSM (within the clock period) and power-gated FSM. By varying the frequency, power results are reported for different input combinations.

Applying partial power-gating to bit-sliced network-on-chip

In the many-core systems, network-on-chip (NoC) serves as an efficient and scalable architecture to connect numerous on-chip resources, whereas it encounters the crisis of the increasing leakage power as technology is continually scaling down. Power-gating which is a representative low-power technique can be utilized to mitigate the increasing leakage power, but the disconnection problem suffered in the conventional power-gated NoC may severely affect network performance. In this paper, we propose a novel partial power-gating approach to avoid the performance loss caused by the disconnection. Firstly, we utilize the asymmetrical bit-slicing scheme to split router into two slices. After the bit-slicing of router datapath, the wide slices can be switched off to save some leakage power by using partial power-gating, but all narrow slices should be kept in ever-active state to avoid the disconnection. Next, owing to the slicing of router datapath, we redefine the packet format for the packet׳s slicing and transferring, and present two essential conversion modules to achieve packet׳s slicing and reassembling. In the synthetic traffic simulation, our design gains considerable power-saving at low-load and exhibits better performance behavior than the conventional power-gated design. The application simulation shows that our design can averagely save 27.5% of total power compared with the baseline design, and reduce 45.0% packet latency on average when compared with the conventional power-gated design. On balance, the bit-sliced NoC with partial power-gating has a better tradeoff between performance and power-efficiency.

Placement Density Aware Power Switch Planning Methodology for Power Gating Designs

As advances in manufacture technology, leakage current increases dramatically in modern ICs. By turning off supply voltage in a low-power domain with power switches, power gating becomes a useful technique in resolving this problem. Since number and locations of power switches have great impact on chip area and IR-drop, an efficient and effective approach to insert power switches is required for the power gating designs. Unlike previous works using the greedy algorithm to handle this problem, this paper uses a simplified model to approximate required equivalent resistance of power switches in a low-power domain, and then determines number and types of power switches based on the value. In order to reduce impact on preplaced standard cells, we also propose a mathematical approach to find locations with less placement density to place power switches. The proposed methodology was integrated into a real-design flow. Experimental results demonstrate that our approach can insert less number of power switches and still satisfy the IR-drop constraint than other approaches.

Applying Partial Power-Gating to Direction-Sliced Network-on-Chip

Network-on-Chip (NoC) is one of critical communication architectures for future many-core systems. As technology is continually scaling down, on-chip network meets the increasing leakage power crisis. As a leakage power mitigation technique, power-gating can be utilized in on-chip network to solve the crisis. However, the network performance is severely affected by the disconnection in the conventional power-gated NoC. In this paper, we propose a novel partial power-gating approach to improve the performance in the power-gated NoC. The approach mainly involves a direction-slicing scheme, an improved routing algorithm, and a deadlock recovery mechanism. In the synthetic traffic simulation, the proposed design shows favorable power-efficiency at low-load range and achieves better performance than the conventional power-gated one. For the application trace simulation, the design in the mesh/torus network consumes 15.2%/18.9% more power on average, whereas it can averagely obtain 45.0%/28.7% performance improvement compared with the conventional power-gated design. On balance, the proposed design with partial power-gating has a better tradeoff between performance and power-efficiency.

CG-in-PG architecture implementation for power reduction in FSMs

By gating the power supply of the inactive part of the finite state machine (FSM) circuit, total power is reduced but the active part continues to dissipate power. So, there is a possibility of applying clock gating (CG) to the active part of the power-gated FSM. A transition may happen in which the states do not change but output changes. This issue has not been addressed by the conventional CG, so, for reducing the switching of register during CG and to overcome the issue, conventional CG has been modified by splitting the input latch of the FSM circuit. The architecture termed as CG-in-PG is designed in such a way that when one sub-FSM is inactive it adopts power gating (PG) for power reduction and other sub-FSM seeks for possible CG during its active period. So, both the sub-FSM is capable of reducing power either by PG or by CG depending on whether it is in inactive mode or active mode. To the best of our knowledge, this is the first ever approach of applying CG after power-aware genetic algorithm (GA)-based bi-partitioning and encoding of FSM for power-gated design. The synthesis of the proposed design has been implemented in Cadence digital synthesis tool. The results show 36.94% average saving after applying CG-in-PG with respect to only PG.

A Robust and Power-Efficient SoC Implementation in 65 nm

Godson2H is a complex SoC (System-on-Chip) of Godson series, which is a 117 mm2, 152 million transistors chip fabricated in 65 nm CMOS LP/GP process technology. It integrates a 1 GHz processor core and abundant high or low speed peripheral IO interfaces. To overcome on-chip-variation problems in deep submicron designs, many methods are adopted in clock tree, and PVT detectors are integrated for debug. To meet the low power constraints in different applications, most of state-of-the-art low power methods are used carefully, such as dynamic voltage and frequency scaling, power gating and aggressive multi-voltage design.

Towards Process Variation-Aware Power Gating

This paper presents a power gating design that considers process variation for proper wakeup control. First, the surge current constraint is examined and refined for a simpler and more realistic view of inter-module reliability. Following that, several circuits are proposed on top of a delay chain to adapt the timing control of power switches to process variations. Experimental results show that the proposed design is able to track process variation such that the surge current and the wakeup time are both kept to expectation in all process corners.

Efficient Wakeup Scheduling Considering Both Resource Usage and Timing Budget for Power Gating Designs

Power gating has been a very effective way to reduce power leakage. Normally, wakeup scheduling is required to control the turn-on times of sleep transistors to limit the surge current during the wakeup process. In this paper, a voltage sensor is adopted to compare the virtual ground voltage with the predesigned reference voltages, and use the result to determine the turn-on times of sleep transistors. We then propose a novel wakeup scheduling formulation that considers the tradeoff between wakeup times and hardware resources incurred by the voltage sensor. To address this problem, on the one hand, an efficient algorithm is proposed to find a wakeup scheduling with minimum wakeup time under the resource constraint. On the other hand, the algorithm to find a wakeup scheduling with minimum resource usage under the timing budget is presented. Experimental results show that with little increase in wakeup times, our algorithm can achieve significant hardware resource reduction for power gating designs.

Design of a Tri-Modal Multi-Threshold CMOS Switch With Application to Data Retentive Power Gating

A tri-modal multi-threshold CMOS (MTCMOS) switch design is presented. Similar to the conventional MTCMOS switches, the tri-modal switch comes in two flavors: header and footer. The tri-modal switch provides three different power modes for the underlying circuit: active, drowsy, and sleep. The ability of data retention in the drowsy mode makes the proposed tri-modal switch an excellent candidate for implementing data-retentive power gating designs. We will see that three different low-power design schemes, namely data-retentive power gating, multi-drowsy mode structures, and on-chip dynamic voltage scaling, are implemented using the proposed tri-modal switch. We show that our proposal introduces superior low-power solutions across various circuit operating modes using a single circuitry.