Power MOSFET Research Articles

Methodology for Characterizing Degradation Locations of Planar and Trench Gate SiC Power Mosfets Under Repetitive Short-Circuit Stress

Methodology for Characterizing Degradation Locations of Planar and Trench Gate SiC Power Mosfets Under Repetitive Short-Circuit Stress

A Cross-Scale Electrothermal Co-Simulation Approach for Power MOSFETs at Device–Package–Heatsink–Board Levels

This paper proposes a cross-scale simulation approach for evaluating the steady-state electrothermal performance of power MOSFETs at the device–package–heatsink–board (DPHB) level. A co-simulation framework is designed by employing the iterative process of power loss and chip temperature to bridge the device and package–heatsink–board (PHB) level simulators. As a result, the cross-scale electrothermal coupling effect within multilevel settings is considered. Correspondingly, variation values in chip temperature and temperature-dependent drain current can be obtained at various voltage biases, level settings, and DPHB structural parameters, incorporating cross-level physical insights. The simulation results are compared with existing methods, and their features and limitations are discussed. Additionally, this paper also derives an empirical equation from the co-simulations to characterize the relationship between the drain current and the chip temperature under different operations exactly. A commercial MOSFET with TO-220F packaging is implemented in experiments to extract the chip temperature and drain current in electrothermal equilibrium. The method comparisons and fair agreement among simulations, equations, and measurements presents the proposed approach as generalized and powerful for describing variations in chip temperature and drain current considering from micrometer devices to millimeter packages–heatsinks–PCB boards, thus providing effective support for DPHB-level co-design.

An improved 4H-SiC trench MOS barrier Schottky diode with current spreading layer and low resistance layer

This paper investigates an improved trench MOS barrier Schottky (TMBS) structure with extra double epitaxial layers (DE-TMBS) based on the conventional TMBS (C-TMBS) featuring a high-doped N-type current spreading layer (CSL) and a high-doped low resistance layer (LRL). Compared to the C-TMBS, the CSL in the improved structure is grown on the N-type drift region, and the LRL is extended on the CSL. According to the numerical simulations and analytical models, the specific on-resistance (Ron,sp) of DE-TMBS can be significantly reduced compared to the conventional one. This is primarily due to the high doping concentration in CSL, which effectively lowers both the JFET resistance and spreading resistance. Additionally, the increased doping concentration in LRL reduces the channel resistance and JFET resistance. Moreover, the doping concentration and thickness of CSL and LRL are optimized to maximize the figure of merit (FOM), that Ron,sp is reduced by 40.9 % and the FOM (BV2/Ron,sp) is improved by 67.9 % compared to the C-TMBS structure.

Double power MOSFETs high‐gain DC–DC topology using two‐winding coupled inductor for renewable energy usage

Double power MOSFETs high‐gain DC–DC topology using two‐winding coupled inductor for renewable energy usage

A Recessed Source Contact Technology to Reduce the Specific On-Resistance of Power MOSFET on 4H-SiC

A Recessed Source Contact Technology to Reduce the Specific On-Resistance of Power MOSFET on 4H-SiC

A Path Dependence Identification Method for Power MOSFETs Degradation Due to Bias Temperature Instability

A Path Dependence Identification Method for Power MOSFETs Degradation Due to Bias Temperature Instability

Modelling and Analysis of Adaptive ON-Time Controlled Boost Converter Using Verilog-A

ABSTRACT This paper presents a mixed modelling of adaptive ON-time controlled boost converter using Verilog-A. It is a mixture of Mathematical modelling, Behavioural modelling, and discrete components. While mathematical modelling has been used to model individual components, for circuits such as comparator and pulse generator behavioural modelling is used. Power MOSFETs in the power stage are the only discrete components used from the library. Each model was coded using Verilog-A in Cadence Virtuoso and its symbolic notation obtained. The symbols were then connected to obtain the complete schematic of the boost converter. The behavioural modelling of the boost converter is targeted for an output voltage of 1.2 V for an input voltage ranging from 0.5 to 0.7 V and switching frequency of 800 KHz. The modelling also captures the results for 40% variation in input and load, for which the output voltage is found to vary by about 5–6%. This work is an attempt at completely modelling a complex analog circuit. It also shows the successful integration of modelled components with discrete components. To validate the results obtained, the performance of the modelled converter is compared with that of circuit simulation, with both simulations being conducted at identical operating conditions. The results obtained with modelling simulation match that obtained with the circuit simulation.

Effects of die top system and trenches on large thin die mechanical robustness

Abstract Power MOSFET dies in the automotive industry are becoming larger (> 5 x 5 mm) and thinner (< 50 µm) to meet high-performance and lifetime requirements. Ensuring the mechanical robustness of these large ultrathin chips is crucial for reliable electronic devices and high-throughput packaging processes. The high aspect ratio and advanced chip designs incorporating trench technology present significant challenges in semiconductor assembly, packaging, and testing. This paper introduces an experimental front-end strategy aimed at strengthening the front side of large ultrathin dies using various die-top systems. Industry-equivalent 50 µm thick dummy power MOSFET dies were fabricated to evaluate the efficacy of different chip designs and materials, such as polyimide, in mitigating fracture risks. Fabrication-induced stresses and warpage in the device layers were measured using a thin-film stress measurement tool. Additionally, the frontside strength of the ultrathin dies was assessed using the three-point bending method, with the resulting data analyzed via two-parameter Weibull distribution plots. Results demonstrated that the deposition of 5 µm polyimide (PI) on the nitride die topside significantly increased die strength from 339 MPa to 760 MPa, with 5 µm PI proving more effective for die strengthening than 10 µm. The interaction between the metal-trench layer and the die was found to be critical to the robustness of ultrathin dies, influenced by the pattern and layout of the trenches. Die-top metallization designs, such as meandering patterns, showed promising improvements in die strength compared to standard designs. A proposed chip layout aims to maximize polyimide coverage for clip-bonded products on the die topside, leveraging its strengthening effect. The study also demonstrated that dummy reference chips can facilitate rapid and straightforward evaluation of extensive design experiments to identify robust chip designs.

Modelling of SiC MOSFET power devices incorporating physical effects

Modelling of SiC MOSFET power devices incorporating physical effects

Research on the influence of total dose on the short-circuit and avalanche characteristics of SiC MOSFET power devices

Research on the influence of total dose on the short-circuit and avalanche characteristics of SiC MOSFET power devices

A Double-Sided Cooled SiC MOSFET Power Module for EV Inverters

A Double-Sided Cooled SiC MOSFET Power Module for EV Inverters

Time-gated optical spectroscopy of field-effect-stimulated recombination via interfacial point defects in fully processed silicon carbide power MOSFETs

Time-gated optical spectroscopy of field-effect-stimulated recombination via interfacial point defects in fully processed silicon carbide power MOSFETs

Dynamic Bias-Temperature Instability Testing in SiC MOSFETs

For power converter development in mission critical applications, the attractive performances of SiC power MOSFETs are shadowed by reliability concerns, particularly those induced by the defects at the gate dielectric. Charge trapping at the oxide-semiconductor interface can lead to threshold voltage drift, degrading the power converter efficiency and lifetime. The scope of this contribution is to show a testing methodology under development to understand SiC power MOSFET threshold voltage stability under dynamic and accelerated operating conditions. The presented testing methodology relies on switching the device under test at high-voltage and current, simultaneously applying a gate stress and extracting threshold voltage from switching transients. The paper outlines the setup description, its operating modes and intended design of experiment to assess SiC MOSFET threshold voltage stability.

Experimental Demonstration and Analysis of 3.3kV 4H-SiC Common-Drain Bidirectional Charge-Balanced Power MOSFETs

By using 4H-SiC packaged Charge-Balanced (CB) MOSFET, we have experimentally demonstrated a 3.3kV 4H-SiC common-drain bidirectional (BD) CB power MOSFET and measured its static and dynamic characteristics compared to its unidirectional counterpart. We show that the BD CB MOSFET conducts and blocks at the first and third quadrants with the appropriate gate bias with an on-state resistance double its unidirectional counterpart, while its switching energies are 12 (19) and 34 (12) mJ/cm2 for BD CB MOSFET (UD CB MOSFET).

Comparative Performance Evaluation of High-Voltage Bidirectional, Conventional and Superjunction Planar DMOSFETs in 4H-SiC

We quantitively compare the static and dynamic performance for high-voltage SiC bidirectional (BD) conventional and superjunction (SJ) DMOSFETs by using 3D TCAD simulations. We extract the specific on-resistance (RON,sp) and the total specific switching charge (QT,sp), which is a sum of the specific gate charge (QG,sp) and drain charge (QDS,sp) to quantify both the static and switching characteristics respectively. We also develop a new Figure-of-Merit (FoM), which is the product of RON,sp . QT,sp, to evaluate the overall performance. We show that the high-voltage 4H-SiC BD SJ DMOSFET has the best FoM with substantial (>58%) improvement, compared to the BD conventional DMOSFETs, which increases with increasing breakdown voltage.

Investigation of the Short-Circuit Withstand Time and On-Resistance Trade-Off of 1.2 kV 4H-SiC Power MOSFETs

The short-circuit withstand time and on-resistance trade-off is investigated in 4H-SiC Power MOSFETs. We compare the static and short circuit withstand time results along with JFET width dependency and PWELL doping variation of MOSFET. We present that smaller Rds,on by wider JFET width and lighter doped PWELL results in worse short circuit withstand time.

SiC GAA MOSFET Concept for High Power Electronics Performance Evaluation through Advanced TCAD Simulations

In this work a groundbreaking SiC power MOSFET based on innovative vertical Gate All Around (GAA) concept is presented. Extensive TCAD simulations are performed to analyze the performance in forward as well as in reverse conditions for this new device concept. The proposed design has a target rating voltage of 1200V, suitable for e-mobility applications.

High-Speed and High-Temperature Switching Operations of a SiC Power MOSFET Using a SiC CMOS Gate Driver Installed inside a Power Module

In this study, the simultaneous realization of high-speed and high-temperature switching operations is demonstrated using a custom-made high-speed and high-temperature power module installed with a silicon carbide (SiC) CMOS gate driver, which can reduce gate loop inductance and operate at high temperatures. Approximate switching speeds of 70 and 60 V/ns are achieved during the turn-on and turn-off operations, respectively, at 300°C, 600 V DC bus voltage, and 20 A load current using the developed module. The switching speed remained above 50 V/ns in the temperature range from room temperature to 300°C. Numerical calculations based on the static properties of the SiC power MOSFET and CMOS gate driver can predict the actual switching properties over a wide temperature range when the developed module incorporating the fabricated SiC CMOS gate driver is used.

Dual injection enhanced super junction TIGBT with narrow mesa and floating-P region

Dual injection enhanced super junction TIGBT with narrow mesa and floating-P region

Dopant Activation Comparison in Phosphorus and Nitrogen Implanted 4H-Silicon Carbide

Bulk mobility and dopant activation of implanted species into 4H-SiC plays a crucial role in the carrier conduction, blocking behavior, and channel properties of a 4H-SiC vertical power MOSFET. Nitrogen and phosphorus ion implantation became the norm as n-type dopants for 4H-SiC. Therefore, the doping and temperature behavior of both species in 4H-SiC needs to be well characterized. In this study, we report a comparison in electrical characteristics between nitrogen and phosphorus implanted 4H-SiC as a function of temperature for various doping levels. For this purpose, 4-point van der Pauw samples are prepared, resistivity and Hall measurements are conducted. We found that resistivities drop as temperature increases from 140 K with phosphorus having higher resistivities at all implanted doping concentrations. The carrier concentrations increase with increase of temperature, indicating incomplete ionization of dopants. Mobilities drop at low temperature due to increased impurity scattering, reaches a peak near 300 K and drops at higher temperature due to increased phonon scattering. From the obtained data, using a two-level charge neutrality equation, the activation percentage and ionization energies of dopants in hexagonal and cubic sites for both species are extracted and compared.