Power MOSFET Research Articles

Modeling and Analysis of Monitoring Gate-Oxide Degradation of SiC Power MOSFETs in Circuit by the Fingerprints of Voltage Switching Transient

Modeling and Analysis of Monitoring Gate-Oxide Degradation of SiC Power MOSFETs in Circuit by the Fingerprints of Voltage Switching Transient

Experimental Demonstration of the Improved Single-Event Irradiation Hardness of Split-Gate 4H-SiC Power MOSFET With Integrated the P+N+ Structure

Experimental Demonstration of the Improved Single-Event Irradiation Hardness of Split-Gate 4H-SiC Power MOSFET With Integrated the P+N+ Structure

The FinFET effect in lateral 4H-SiC and Silicon multi-gate MOSFETs

Abstract This paper presents a comprehensive investigation on the role and manifestation of the FinFET effect in low voltage 4H-SiC MOSFETs as compared to their Si counterparts. For this purpose, a finite element model of a fabricated SiC FinFET with a fin width of 55 nm is constructed and calibrated to experimental data at a range of operating temperatures. The resulting TCAD model is then applied to examine the impact of the FinFET effect on the threshold voltage and the spatial variation of the carrier density and the drift mobility in the channel for a range of doping concentrations N A of the p-well. It is thereby shown that by reducing the fin width W fin from conventional values ≳ 500 nm down to an interval of optimal values ∼40 nm (keeping everything else constant), it is possible to enhance the channel mobility ∼2.5 times. This improvement is not only found to be much larger than the one predicted in Si (where it is ∼ 15% according to the TCAD model) but also arises at a larger fin width (for a given N A ). In this respect, it is demonstrated that this optimal range of fin widths can be moved to even larger, more practical values by reducing the doping of the p-well. As an alternative, the on-state performance of the gate-all-around FET is also examined in detail following a similar procedure. It is hence shown that this structure can display the FinFET effect at an even larger, nearly conventional W fin of ∼250 nm, whilst attaining a higher channel mobility and inversion layer density even than a stripe FinFET operated at the same overdrive. Thus, in light of all these advantages, the FinFET topology can play a key role in reducing the channel resistance of SiC power MOSFETs.

Enhancement of positive bevel β-Ga2O3 trench MOS barrier Schottky diode by post-etching treatment

A β-Ga2O3 trench MOS barrier Schottky (TMBS) diode with a novel terminal structure of positive bevel mesa and arc bottom corners has been designed and realized in this work. O2 plasma, hydrogen fluoride (HF), and tetramethylammonium hydroxide (TMAH) are used for post-etching treatment of devices, respectively. Measurement results shows that the specific on-resistance of the three devices are nearly with the same value of 2.60 mΩ·cm2. The breakdown voltage of the devices with O2 plasma, HF, and TMAH treatments are 1280 V, 1440 V, and 1800 V, respectively. Moreover, it is worth nothing that devices treated with O2 plasma have a lower reverse leakage. In addition, the breakdown location of the device is determined to be at the β-Ga2O3 interface under the edge of the field plate by combining simulation and capacitance breakdown testing. AFM and XPS are used to analyze the surface properties of β-Ga2O3 after post-etching treatments. The results show that the TMAH treatments have the most significant effect on reducing surface roughness, and the O2 plasma treatments is the most effective in decreasing oxygen vacancies.

Advancing renewable energy: A quadratic high-efficiency high gain step-up DC/DC converter

Presenting a new high-gain converter that incorporates a coupled inductor, this paper offers a range of advantages over existing designs. The circuit features a simple structure with two cascade semi-stages, two power switches operating in sync, and a coupled inductor. It provides an extensive output voltage range, ensures continuous input current with minimal ripple, maintains positive output voltage polarity, and follows a standard ground configuration. These features make it well-suited for various applications, particularly in photovoltaic systems. Additionally, the voltage stress across each power switch is significantly lower than that of other boost converters, allowing for the selection of power MOSFETs with reduced drain-source ON resistance to ensure high efficiency. This research presents comprehensive assessments of the steady-state and stress conditions as well as thorough comparisons with other similar converters operating in continuous conduction mode. Theoretical advantages of the proposed circuit design are further reinforced by experimental results obtained from a 200-W step-up 25–370 V arrangement.

A novel structure of less switching loss IGBT with super junction

In order to further reduce the switching loss (ESW), a novel floating CS layer and super-junction insulated gate bipolar transistor (FCS-SJBJ-IGBT) with internal barrier junction is proposed and simulated. On the premise of not affecting breakdown voltage (BV), the CS layer of FCS-SJBJ-IGBT is floating, so that the P-body is connected with the P-drift region, and a small part of P-pillar is formed between the CS layer and the left gate, which enables electrons to flow rapidly through this region in the on state, and provides an extraction hole path in the off state to reduce the loss. The simulation results show that，under the same forward conduction voltage (VON) condition, the turn-on energy loss (EON) of FCS-SJBJ-IGBT is significantly lower than that of the traditional super-junction IGBT (con-SJ-IGBT) and 34.5 % lower than that of the recently reported super-junction IGBT (SJBJ-IGBT) with blocking junction, P-pillar and N-pillar, while their turn-off energy loss (EOFF) is almost the same. The research results can provide important reference for reducing the ESW of IGBT.

Novel power MOSFET with drain-side N–Si/N-SiGe heterojunctions for improving reverse recovery performance

—A novel power MOSFET structure with Drain-side N–Si/N-SiGe Heterojunctions (DH-MOS) is proposed by introducing a N SiGe region which is sandwiched between the N-drift region and N+ substrate on the drain side. The operation mechanism and simulation verification of DH-MOS are presented. Due to the difference in valence band of N Si/N SiGe heterojunction, holes can be more easily expelled from the N-drift region into N SiGe region during the reverse conduction of DH-MOS, resulting in a significant reduction in hole density inside the N-drift region, thus improving the reverse recovery performance. Simulation results show that the reverse recovery charge (Qrr) of DH-MOS is 2.08 μC/cm2, approximately 66.34 % lower than the 6.18 μC/cm2 of conventional MOS. The introduction of new DH-MOS structure with N–Si/N-SiGe heterojunctions does not result in a significant increase in reverse conduction voltage (VF). In addition, it does not sacrifice any forward conduction and blocking characteristics. The proposed DH-MOS introduces changes on the drain side, unlike existing methods which focus on the source side or drift region. And it can be compatible with existing improving measures to further improve the reverse recovery performance.

Design an intelligent system comprising a fuzzy controller and a single-inductance DC/DC converter to improve photovoltaic system performance

In photovoltaic systems, the DC/DC converter operates in an environment characterized by disturbances, imprecise and uncertain variations in climatic parameters, and sensitivity to intrinsic photovoltaic module (PVM) parameters. These factors can significantly affect the operational efficiency and performance of both the DC/DC converters and the connected load. The objective of this research is to design an intelligent system comprising a fuzzy controller and a single inductance DC/DC converter to enhance the performance of PV systems. Two distinct Maximum Power Point Tracking (MPPT) methods are proposed: the first employs a traditional technique, while the second leverages fuzzy logic. The developed system incorporates a photovoltaic module that supplies power to a load through a step-down chopper. The experimental setup comprises two primary sections, namely an acquisition section and a power interface one. Signals acquired from the photovoltaic module transmitted to the PC via the serial port using a PIC16F877A microcontroller. This microcontroller undertakes signal processing and control of the power interface for the chopper, employing a MOSFET power transistor. The outcomes obtained during the implementation underscore the necessity for the fuzzy controller in optimizing the overall system performance.

Evaluation of Single-Event Effect Current-Carrier Mapping Based on Experimental Data.

For single-event radiation damage of power MOSFET devices, this paper aims to establish a statistical analysis method based on external observation (gate/drain current characteristics in irradiation environment) to recognize and evaluate the radiation evolution process and damage mechanism of microscopic physical quantities inside the devices, namely current-carrier (CC) mapping. Firstly, a special data fluctuate-collapse transform analysis method is proposed according to the temporal characteristics of the gate/drain current. Secondly, a carrier dynamic balance ratio based on current data is defined to evaluate the radiation damage degree of the device. TCAD is used to deeply study the relationship between the external current characteristics and the evolution process of internal physical quantities and the damage mechanism. The results show that the current data timing analysis based on fluctuate-collapse transformation can better peer into the evolution process of irradiation events inside the device, and the statistical analysis based on the dynamic balance ratio of carriers can evaluate the severity of irradiation damage to a certain extent.

Precise and Fast Real-Time Measurement of Junction Temperature in SiC Power MOSFETs

Precise and Fast Real-Time Measurement of Junction Temperature in SiC Power MOSFETs

Evaluation of Electrical Model Parameter Changes in SiC Power MOSFETs During Power Cycling Test

Evaluation of Electrical Model Parameter Changes in SiC Power MOSFETs During Power Cycling Test

Methodology for Characterizing Degradation Locations of Planar and Trench Gate SiC Power Mosfets Under Repetitive Short-Circuit Stress

Methodology for Characterizing Degradation Locations of Planar and Trench Gate SiC Power Mosfets Under Repetitive Short-Circuit Stress

A Cross-Scale Electrothermal Co-Simulation Approach for Power MOSFETs at Device-Package-Heatsink-Board Levels.

This paper proposes a cross-scale simulation approach for evaluating the steady-state electrothermal performance of power MOSFETs at the device-package-heatsink-board (DPHB) level. A co-simulation framework is designed by employing the iterative process of power loss and chip temperature to bridge the device and package-heatsink-board (PHB) level simulators. As a result, the cross-scale electrothermal coupling effect within multilevel settings is considered. Correspondingly, variation values in chip temperature and temperature-dependent drain current can be obtained at various voltage biases, level settings, and DPHB structural parameters, incorporating cross-level physical insights. The simulation results are compared with existing methods, and their features and limitations are discussed. Additionally, this paper also derives an empirical equation from the co-simulations to characterize the relationship between the drain current and the chip temperature under different operations exactly. A commercial MOSFET with TO-220F packaging is implemented in experiments to extract the chip temperature and drain current in electrothermal equilibrium. The method comparisons and fair agreement among simulations, equations, and measurements presents the proposed approach as generalized and powerful for describing variations in chip temperature and drain current considering from micrometer devices to millimeter packages-heatsinks-PCB boards, thus providing effective support for DPHB-level co-design.

An improved 4H-SiC trench MOS barrier Schottky diode with current spreading layer and low resistance layer

This paper investigates an improved trench MOS barrier Schottky (TMBS) structure with extra double epitaxial layers (DE-TMBS) based on the conventional TMBS (C-TMBS) featuring a high-doped N-type current spreading layer (CSL) and a high-doped low resistance layer (LRL). Compared to the C-TMBS, the CSL in the improved structure is grown on the N-type drift region, and the LRL is extended on the CSL. According to the numerical simulations and analytical models, the specific on-resistance (Ron,sp) of DE-TMBS can be significantly reduced compared to the conventional one. This is primarily due to the high doping concentration in CSL, which effectively lowers both the JFET resistance and spreading resistance. Additionally, the increased doping concentration in LRL reduces the channel resistance and JFET resistance. Moreover, the doping concentration and thickness of CSL and LRL are optimized to maximize the figure of merit (FOM), that Ron,sp is reduced by 40.9 % and the FOM (BV2/Ron,sp) is improved by 67.9 % compared to the C-TMBS structure.

Double power MOSFETs high‐gain DC–DC topology using two‐winding coupled inductor for renewable energy usage

Double power MOSFETs high‐gain DC–DC topology using two‐winding coupled inductor for renewable energy usage

A Recessed Source Contact Technology to Reduce the Specific On-Resistance of Power MOSFET on 4H-SiC

A Recessed Source Contact Technology to Reduce the Specific On-Resistance of Power MOSFET on 4H-SiC

A Path Dependence Identification Method for Power MOSFETs Degradation Due to Bias Temperature Instability

A Path Dependence Identification Method for Power MOSFETs Degradation Due to Bias Temperature Instability

Modelling and Analysis of Adaptive ON-Time Controlled Boost Converter Using Verilog-A

ABSTRACT This paper presents a mixed modelling of adaptive ON-time controlled boost converter using Verilog-A. It is a mixture of Mathematical modelling, Behavioural modelling, and discrete components. While mathematical modelling has been used to model individual components, for circuits such as comparator and pulse generator behavioural modelling is used. Power MOSFETs in the power stage are the only discrete components used from the library. Each model was coded using Verilog-A in Cadence Virtuoso and its symbolic notation obtained. The symbols were then connected to obtain the complete schematic of the boost converter. The behavioural modelling of the boost converter is targeted for an output voltage of 1.2 V for an input voltage ranging from 0.5 to 0.7 V and switching frequency of 800 KHz. The modelling also captures the results for 40% variation in input and load, for which the output voltage is found to vary by about 5–6%. This work is an attempt at completely modelling a complex analog circuit. It also shows the successful integration of modelled components with discrete components. To validate the results obtained, the performance of the modelled converter is compared with that of circuit simulation, with both simulations being conducted at identical operating conditions. The results obtained with modelling simulation match that obtained with the circuit simulation.

Effects of die top system and trenches on large thin die mechanical robustness

Abstract Power MOSFET dies in the automotive industry are becoming larger (> 5 x 5 mm) and thinner (< 50 µm) to meet high-performance and lifetime requirements. Ensuring the mechanical robustness of these large ultrathin chips is crucial for reliable electronic devices and high-throughput packaging processes. The high aspect ratio and advanced chip designs incorporating trench technology present significant challenges in semiconductor assembly, packaging, and testing. This paper introduces an experimental front-end strategy aimed at strengthening the front side of large ultrathin dies using various die-top systems. Industry-equivalent 50 µm thick dummy power MOSFET dies were fabricated to evaluate the efficacy of different chip designs and materials, such as polyimide, in mitigating fracture risks. Fabrication-induced stresses and warpage in the device layers were measured using a thin-film stress measurement tool. Additionally, the frontside strength of the ultrathin dies was assessed using the three-point bending method, with the resulting data analyzed via two-parameter Weibull distribution plots. Results demonstrated that the deposition of 5 µm polyimide (PI) on the nitride die topside significantly increased die strength from 339 MPa to 760 MPa, with 5 µm PI proving more effective for die strengthening than 10 µm. The interaction between the metal-trench layer and the die was found to be critical to the robustness of ultrathin dies, influenced by the pattern and layout of the trenches. Die-top metallization designs, such as meandering patterns, showed promising improvements in die strength compared to standard designs. A proposed chip layout aims to maximize polyimide coverage for clip-bonded products on the die topside, leveraging its strengthening effect. The study also demonstrated that dummy reference chips can facilitate rapid and straightforward evaluation of extensive design experiments to identify robust chip designs.

Modelling of SiC MOSFET power devices incorporating physical effects

Modelling of SiC MOSFET power devices incorporating physical effects