Power Delivery Network Impedance Research Articles

A Statistical Approach for Signal and Power Integrity Co-Design in High-Speed Interconnects Considering Non-Linear Power/Ground Noise and Bit-Patterns.

In this article, a novel statistical approach is proposed and applied to co-design signal and power integrity (SI/PI) in high-speed interconnects considering the non-linear power/ground noise generated by parallel buffers and bit-patterns. With increased data rates and decreased operating voltages, the allowed noise margin in high-speed interconnects is continuously reduced, and this trend requires SI/PI co-design. Specifically, non-linear power/ground noise associated with simultaneous switching circuits sharing a power delivery network (PDN) and bit-patterns must be carefully considered during the interconnects' design and analysis phase. In many cases, conventional electromagnetic (EM) and transient circuit simulators require heavy computational resources or even fail to deliver an accurate result. The proposed statistical method estimates the statistical eye-diagram in the high-speed interconnect considering power/ground noise and bit-patterns such as data bus inversion (DBI) coding. The accuracy and computational efficiency of the proposed method are validated by comparing the result with HSPICE transient simulation result. The proposed method is also compared with conventional statistical methods, such as peak distortion analysis (PDA) and statistical channel simulation in the transient simulator. Lastly, the proposed method is applied to the SI/PI co-design and co-analysis in the high bandwidth memory (HBM) interposer channel. Impacts of decoupling capacitors on hierarchical PDN impedance, statistical eye-diagram of the HBM channel, and bit error rate (BER) Bathtub curves are summarized. Finally, the BER eye-diagram is derived from the estimated statistical eye-diagram for timing and voltage analysis. The impacts of hierarchical PDN design and bit-patterns on SI/PI are discussed.

PDNPulse: Sensing PCB Anomaly With the Intrinsic Power Delivery Network

The ubiquitous presence of printed circuit boards (PCBs) in modern electronic systems and embedded devices makes their integrity a top security concern. To take advantage of the economies of scale, today’s PCB design and manufacturing are often performed by suppliers around the globe, exposing them to many security vulnerabilities along the segmented PCB supply chain. Moreover, the increasing complexity of the PCB designs also leaves ample room for numerous sneaky board-level attacks to be implemented throughout each stage of a PCB’s lifetime, threatening many electronic devices. In this paper, we propose <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">PDNPulse</i> , a power delivery network (PDN) based PCB anomaly detection framework that can identify a wide spectrum of board-level malicious modifications. PDNPulse leverages the fact that the PDN’s characteristics are inevitably affected by modifications to the PCB. By detecting changes to the PDN impedance profile against the golden model and using the Frechet distance-based anomaly detection algorithms, PDNPulse can robustly and successfully discern malicious modifications across the system. Using PDNPulse, we conduct extensive experiments on seven commercial-off-the-shelf PCBs, covering different design scales, different threat models, and seven different anomaly types. The results confirm that PDNPulse creates an effective security asymmetry between attack and defense.

Exploiting On-Chip Voltage Regulators for Leakage Reduction in Hardware Masking.

A design space exploration of the countermeasures for hardware masking is proposed in this paper. The assumption of independence among shares used in hardware masking can be violated in practical designs. Recently, the security impact of noise coupling among multiple masking shares has been demonstrated both in practical FPGA implementations and with extensive transistor level simulations. Due to the highly sophisticated interactions in modern VLSI circuits, the interactions among multiple masking shares are quite challenging to model and thus information leakage from one share to another through noise coupling is difficult to mitigate. In this paper, the implications of utilizing on-chip voltage regulators to minimize the coupling among multiple masking shares through a shared power delivery network (PDN) are investigated. Specifically, different voltage regulator configurations where the power is delivered to different shares through various configurations are investigated. The placement of a voltage regulator relative to the masking shares is demonstrated to a have a significant impact on the coupling between masking shares. A PDN consisting of two shares is simulated with an ideal voltage regulator, strong DLDO, normal DLDO, weak DLDO, two DLDOs, and two DLDOs with 180 phase shift. An 18 × 18 grid PDN with a normal DLDO is simulated to demonstrate the effect of PDN impedance on security. The security analysis is performed using correlation and t-test analyses where a low correlation between shares can be inferred as security improvement and a t-test value below 4.5 means that the shares have negligible coupling, and thus the proposed method is secure. In certain cases, the proposed techniques achieve up to an 80% reduction in the correlation between masking shares. The PDN with two DLDOs and two-phase DLDO with 180 phase shift achieve satisfactory security levels since t-test values remain under 4.5 with 100,000 traces of simulations. The security of the PDN improves if DLDO is placed closer to any one of the masking shares.

Machine learning modeling of power delivery networks with varying decoupling capacitors

&lt;p&gt;This paper presents modeling of power delivery network (PDN) impedance with varying decoupling capacitor placements using machine learning techniques. The use of multilayer perceptron artificial neural networks (ANN) and gaussian process regression (GPR) techniques are explored, and the effects of the hyperparameters such as the number of hidden neurons in the ANN, and the choice of kernel functions in the GPR are investigated. The best performing networks in each case are selected and compared in terms of accuracy using test data consisting of PDN impedance responses that were never encountered during training. Results show that the GPR models were significantly more accurate than the ANN models, with an average mean absolute error of 5.23 mΩ compared to 11.33 mΩ for the ANN.&lt;/p&gt;

A Frequency-Dependent Target Impedance Method Fulfilling Voltage Drop Constraints in Multiple Frequency Ranges

Target impedance plays a critical role in guiding a robust power delivery network (PDN) design. However, the traditional methodology has difficulty in associating time-domain information, such as current profile and voltage drop constraints, with frequency-domain PDN impedance. Existing works try to derive frequency-dependent target impedance, but the average voltage drop is not explicitly taken into account, and the dynamic voltage drop constraints are not considered separately in middle and high-frequency ranges. Such limitations can result in under- or over-designed PDN. This article proposes a frequency-dependent target impedance methodology, which determines the target impedance shape from the given constraints in multiple frequency ranges. The key idea is to exploit a concept of magnitude equivalent frequency to bridge the time-domain behavior and frequency-domain target impedance. Experiment results show that the proposed frequency-dependent target impedance tightly satisfies the given voltage drop constraints.

Development of Backside Buried Metal Layer Technology for 3D-ICs

Abstract In this study, we developed backside buried metal (BBM) layer technology for three-dimensional integrated circuits (3D-ICs). In this technology, a BBM layer for global power routing is introduced in the large vacant area on the backside of each chip and is parallelly connected with the frontside routing of the chip. The resistances of the power supply (VDD) and ground (VSS) lines consequently decrease. In addition, the BBM structure acts as a decoupling capacitor because it is buried in the Si substrate and has metal–insulator–silicon structure. Therefore, the impedance of power delivery network can be reduced by introducing the BBM layer. The fabrication process of the BBM layer for 3D-ICs was simple and compatible with the via-last through-silicon via (TSV) process. With this process, it was possible to fabricate the BBM layer consisting of electroplated Cu (thickness: approximately 10 μm) buried in the backside of the CMOS chip (thickness: 43 μm), which was connected with the frontside routing of the chip using 9 μm-diameter TSVs.

High-Frequency Electrothermal Characterization of TSV-Based Power Delivery Network

In this paper, high-frequency electrothermal characteristics of the power delivery network (PDN) are investigated for through-silicon-via (TSV)-based 3-D ICs by utilizing a self-developed electrothermal co-simulation solver. The solver circularly solves the full-wave electromagnetic equation and the steady heat conduction equation using the finite-element method. The preconditioned biconjugate gradient method combined with the element-by-element approximate factorization method is employed to speed up the simulation and save memory cost. Based on the solver, the impacts of the excitation condition and dielectric loss tangent are analyzed for a one-chip power grid, while the influence of TSV location is studied for a two-chip PDN structure. In the modeling, both the conductor and dielectric losses are taken into account, and the temperature dependence of material parameters is treated appropriately. As results, PDN impedance and self-heating-induced temperature rise are emphatically analyzed in a wide frequency range, and the electric field and temperature distributions of several resonance modes are presented. The results would be beneficial for the design and thermal management of 3-D PDNs.

Power delivery network impedance characterization for high speed I/O interfaces using PRBS transmissions

This paper presents a method to characterize power delivery network impedance seen at the silicon level in a high-speed I/O interface using pseudorandom bit stream (PRBS) patterns. Moreover, results from a transient simulation using the extracted impedance are compared with laboratory measurements, showing good correlation.

Improvements of System-in-Package Integration and Electrical Performance Using BVA Wire Bonding

In this paper, bond via array (BVA) wirebond is used to achieve compact vertical integration and improve the electrical performance for system in package (SiP). Two techniques are presented. In the first technique, BVA wirebonds are utilized to integrate some passive or active components vertically onto other components. This significantly reduces the horizontal footprint of the entire SiP. In terms of electrical performance, this vertical integration provides much lower parasitic inductance than conventional 2-D horizontal integration design because of shorter interconnection. For example, the proposed technology can significantly reduce power delivery network impedance compared to a conventional design. In the second technique, we propose BVA wirebond wires as an electromagnetic interference (EMI) shield between different domains within SiP. This provides a lower cost solution for EMI shielding, particularly when regions within a package need to be shielded.

Modeling and Analysis of PDN Impedance and Switching Noise in TSV-Based 3-D Integration

This paper reports on modeling and analysis of power delivery network (PDN) impedance and switching noise in through silicon via (TSV)-based 3-D integration. PDN is simulated in SPICE with the combination of lumped-element models and distributed-element models, where the elements are extracted from full-wave electromagnetic modeling. PDN impedance explicitly distinguishes the contributions from off-chip PDN and on-chip PDN, and reveals the TSV-induced resonant effect associated with the 3-D chip stack. The simultaneously switching noises in PDN are simulated and analyzed in different frequency regions, in which 3-D integration has distinct impacts on the PDN impedance.

Through-Silicon-Via-Based Decoupling Capacitor Stacked Chip in 3-D-ICs

In this paper, a new decoupling capacitor stacked chip (DCSC) based on extra decoupling capacitors and through-silicon-vias (TSVs) is proposed to overcome the narrow-bandwidth limitation of the conventional decoupling capacitor solutions in three-dimensional-integrated circuits (3-D-ICs), as exhibited by expensive on-chip metal-oxide-semiconductor (MOS) decoupling capacitors and inductive off-chip discrete decoupling capacitors. In particular, in comparison to the on-chip decoupling solutions, such as MOS, metal-insulator-metal and deep trench capacitors, the proposed TSV-based DCSC represents several advantages, such as small leakage currents, large capacitances ranging from tens of nF to a few μF, low equivalent series inductance (ESL) with tens of pH, and high flexibility in TSV arrangements. The proposed TSV-based DCSC can be applied by mounting decoupling capacitors, such as Si-based MOS capacitors and discrete capacitors, on the backside of a chip and connecting the capacitors to the on-chip power delivery network (PDN) through TSVs. To demonstrate the performance of the proposed DCSC structure, a segmentation method was applied to compare the PDN impedance (Z11) of the TSV-based DCSC with those of the well-known conventional decoupling capacitor methods. The TSV-based DCSC was found to exhibit the advantages of both low on-chip level ESL (under several tens of pH) and high off-chip level capacitance (up to several μF). Additionally, the PDN impedance properties of the TSV-based DCSC were analyzed with respect to the variations in the number of power/ground TSV pairs, on-chip PDN size, and capacitance values of the stacked off-chip discrete decoupling capacitors using the segmentation method.