Viewpoint Of Power Consumption Research Articles

Power Consumption Analysis and Miniaturization Design of Permanent Magnet Synchronous Motor for Washing Machine with respect to Gear Use

In this paper, the energy consumption of PMSM was compared simultaneously in direct and indirect drive systems, considering the efficiency of the operating point in the washing and dehydration modes. DD (Direct Drive) washing machines have the disadvantage of high-power consumption due to the difference in driving point efficiency of washing and dehydration. Therefore, in this paper, a method of changing the washing operation point using a gear is proposed. Two types of miniaturization models that satisfies the output level under two gear conditions are designed, and energy consumption with respect to the operating mode of the washing machine is analyzed and compared. From the viewpoint of power consumption, optimal stacking and gear combination model is selected. In conclusion, the energy consumption of the optimum gear model is decreased about 97 Wh and material cost of the motor down by 57.3 % compared with base DD motor.

3-D Magnetic Orientation Control of Ferromagnetic Film/Guanine Crystal Hybrid Plate

The light reflection intensity from a biogenic guanine crystal that shows strong light scattering on the broadest surface of the crystal can be modulated by the magnetic field switching due to the dynamic motion of magnetic orientation caused by the diamagnetic anisotropy. Magnetic field amplitudes required for magnetic orientation are drastically decreased by hybridizing the guanine crystal with a ferromagnetic thin film, which is one of the important factors for device application from the viewpoint of power consumption and field generation method. In this paper, we present the 3-D magnetic orientation control of the guanine crystal hybridized with the 5 nm thick permalloy film by applying the magnetic field with a three-axis Helmholtz coil. Vertical magnetic field dependences of the tilt angle of (102) plane of the guanine crystal from the substrate for various in-plane magnetic fields are investigated. It is clarified that the hybrid plate can be controlled three-dimensionally with the magnetic field less than several milliteslas by applying the suitable in-plane field. It is shown that the hybrid plate floating under water is transported by the magnetic field gradient using the permanent magnet, which is effective for carrying it to the target position. The 3-D magnetic orientation characteristics of the hybrid plate that shows the similar behavior to the biogenic guanine crystal for the vertical magnetic field are also mentioned.

MAC protocol with clock synchronization correction for a practical infrastructure monitoring system

Sensor networks for infrastructure monitoring systems require battery-operated sensing nodes with a lifetime of 10 years, a standardized technology, and low engineering costs. Receiver-initiated transmission and coordinated sampled listening are promising power-saving communication methods that can be used for infrastructure monitoring. First, we compared receiver-initiated transmission and coordinated sampled listening from the viewpoint of power consumption and communication success probability. The results of the comparison showed that if we can continue coordinated sampled listening synchronous communication mode, we can satisfy the low power consumption performance required for infrastructure monitoring. However, coordinated sampled listening synchronous communication cannot be maintained for a longer period owing to performance variations of the clock crystal oscillator (CXO). We solved this problem by developing energy efficient system-media access control protocol (NES MAC), a MAC protocol with the additional function of correcting the dispersion of CXO and maintaining synchronization for a long time. NES-MAC is fully compatible with coordinated sampled listening. Furthermore, NES-MAC also has a high power-saving effect when communicating with normal coordinated sampled listening. Therefore, it is possible to expand the network easily and economically without affecting the power-saving performance. In addition, we found that through actual equipment evaluation that sensor nodes that adopt NES-MAC can operate for more than 10 years with two CR123A-type batteries.

Performance Analysis of Slinky Horizontal Ground Heat Exchangers for a Ground Source Heat Pump System

This paper highlights the thermal performance of reclined (parallel to ground surface) and standing (perpendicular to ground surface) slinky horizontal ground heat exchangers (HGHEs) with different water mass flow rates in the heating mode of continuous and intermittent operations. A copper tube with an outer surface protected with low-density polyethylene was selected as the tube material of the ground heat exchanger. Effects on ground temperature around the reclined slinky HGHE due to heat extraction and the effect of variation of ground temperatures on reclined HGHE performance are discussed. A higher heat exchange rate was experienced in standing HGHE than in reclined HGHE. The standing HGHE was affected by deeper ground temperature and also a greater amount of backfilled sand in standing HGHE (4.20 m3) than reclined HGHE (1.58 m3), which has higher thermal conductivity than site soil. For mass flow rate of 1 L/min with inlet water temperature 7 °C, the 4-day average heat extraction rates increased 45.3% and 127.3%, respectively, when the initial average ground temperatures at 1.5 m depth around reclined HGHE increased from 10.4 °C to 11.7 °C and 10.4 °C to 13.7 °C. In the case of intermittent operation, which boosted the thermal performance, a short time interval of intermittent operation is better than a long time interval of intermittent operation. Furthermore, from the viewpoint of power consumption by the circulating pump, the intermittent operation is more efficient than continuous operation.

A simple structure wavelet transform circuit employing function link neural networks and SI filters

ABSTRACTSignal processing by means of analog circuits offers advantages from a power consumption viewpoint. Implementing wavelet transform (WT) using analog circuits is of great interest when low-power consumption becomes an important issue. In this article, a novel simple structure WT circuit in analog domain is presented by employing functional link neural network (FLNN) and switched-current (SI) filters. First, the wavelet base is approximated using FLNN algorithms for giving a filter transfer function that is suitable for simple structure WT circuit implementation. Next, the WT circuit is constructed with the wavelet filter bank, whose impulse response is the approximated wavelet and its dilations. The filter design that follows is based on a follow-the-leader feedback (FLF) structure with multiple output bilinear SI integrators and current mirrors as the main building blocks. SI filter is well suited for this application since the dilation constant across different scales of the transform can be precisely implemented and controlled by the clock frequency of the circuit with the same system architecture. Finally, to illustrate the design procedure, a seventh-order FLNN-approximated Gaussian wavelet is implemented as an example. Simulations have successfully verified that the designed simple structure WT circuit has low sensitivity, low-power consumption and litter effect to the imperfections.

Reducing Cache Hardware by Focusing on Data Redundancy

SUMMARYThere is one reason to utilize cache that mitigates processor performance limitation comes from data transfer bandwidth. Recently, cache size expansion is required in this use because data transfer bandwidth requirement is increasing for recent large data size and multi‐core trends. However, cache size expansion is unwelcome because it causes problems arising from circuit area and power consumption viewpoint. This paper focuses a data redundancy with the goal of reducing cache size and proposes a mechanism that does not store redundant data into cache. The proposed mechanism divides data into higher bit and lower bit that stored into higher cache and lower cache, respectively. We reduced higher cache size to half size by keeping 46% redundant data in higher bit area not to store into higher cache. The evaluation results show that the proposed mechanism increases IPC by 3.3% on average compared with same circuit area conventional cache under SPECCPU2000 benchmarks.

Segmented Architecture for Successive Approximation Analog-to-Digital Converters

In this paper, the structure of a binary-weighted capacitive digital-to-analog converter (DAC) in a successive-approximation analog-to-digital converter (SA-ADC) is modified to a unary or segmented configuration to reduce the power consumption and improve the static linearity performance. In order to be able to choose the optimum value of the segmentation degree (i.e., the number of unary bits), the power consumption and the static linearity behavior of the segmented architecture as functions of the segmentation degree are analyzed. Circuit-level simulation results are presented to show the accuracy of the proposed equations. It is shown that for moderate and high-resolution ADCs, a segmentation degree of four or five bits is the optimum choice from the power-consumption viewpoint. Simulation results of a 1 V, 10-bit, 100-kS/s SA-ADC show that the power consumption of the entire capacitive DAC and the digital circuit of the segmented implementation with a segmentation degree of 4 is 30% less than the conventional design while the standard deviation of the differential nonlinearity is reduced by a factor of 2√(2).

Reducing Cache Hardware by Focusing on Data Redundancy

There's one reason to utilize cache that mitigates processor performance limitation comes from data transfer bandwidth. Recently, cache size expansion is required in this use because data transfer bandwidth requirement is increasing for recent large data size and multi-core trends. However, cache size expansion is unwelcome because it causes problems come from circuit area and power consumption viewpoint. This paper focuses a data redundancy with the goal of reducing cache size and proposes a mechanism that does not store redundant data into cache. The proposed mechanism divides data into Higher Bit and Lower Bit, that stored into Higher Cache and Lower Cache, respectively. We reduced Higher Cache size to half size by keeping 46% redundant data in Higher Bit area not to store into Higher Cache. The evaluation results show that the proposed mechanism increases IPC by 3.3% on average compared with same circuit area conventional cache under SPECCPU2000 benchmarks.

Implementing Wavelets in Continuous-Time Analog Circuits With Dynamic Range Optimization

Signal processing by means of analog circuits offers advantages from a power consumption viewpoint. A method is described to implement wavelets in analog circuits by fitting the impulse response of a linear system to the time-reversed wavelet function. The fitting is performed using local search involving an L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> criterion, starting from a deterministic starting point. This approach offers a large performance increase over previous Padé-based approaches and allows for the circuit implementation of a larger range of wavelet functions. Subsequently, using state-space optimization the dynamic range of the circuit is optimized. Finally, to illustrate the design procedure, a sixth-order L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> -approximated orthonormal Gaussian wavelet filter using G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> -C integrators is presented.

A power-aware code-compression design for RISC/VLIW architecture

We studied the architecture of embedded computing systems from the viewpoint of power consumption in memory systems and used a selective-code-compression (SCC) approach to realize our design. Based on the LZW (Lempel-Ziv-Welch) compression algorithm, we propose a novel cost effective compression and decompression method. The goal of our study was to develop a new SCC approach with an extended decision policy based on the prediction of power consumption. Our decompression method had to be easily implemented in hardware and to collaborate with the embedded processor. The hardware implementation of our decompression engine uses the TSMC 0.18 μm-2p6m model and its cell-based libraries. To calculate power consumption more accurately, we used a static analysis method to estimate the power overhead of the decompression engine. We also used variable sized branch blocks and considered several features of very long instruction word (VLIW) processors for our compression, including the instruction level parallelism (ILP) technique and the scheduling of instructions. Our code-compression methods are not limited to VLIW machines, and can be applied to other kinds of reduced instruction set computer (RISC) architecture.

A comprehensive study of energy efficiency and performance of flash-based SSD

Use of flash memory as a storage medium is becoming popular in diverse computing environments. However, because of differences in interface, flash memory requires a hard-disk-emulation layer, called FTL (flash translation layer). Although the FTL enables flash memory storages to replace conventional hard disks, it induces significant computational and space overhead. Despite the low power consumption of flash memory, this overhead leads to significant power consumption in an overall storage system. In this paper, we analyze the characteristics of flash-based storage devices from the viewpoint of power consumption and energy efficiency by using various methodologies. First, we utilize simulation to investigate the interior operation of flash-based storage of flash-based storages. Subsequently, we measure the performance and energy efficiency of commodity flash-based SSDs by using microbenchmarks to identify the block-device level characteristics and macrobenchmarks to reveal their filesystem level characteristics.

Separation Characteristics of Submicron Particles in an Electrostatic Precipitator with Alternating Electric Field Corona Charger

Experiments were carried out to investigate filtration characteristics of an electrostatic precipitator (ESP) with alternating and direct electric field corona charger. Potassium Sodium Tartrate Tetrahydrate as the material was used to generate polydisperse submicron aerosols by using Constant Output Atomizer. The results indicated that the aerosol penetration through the ESP decreased as applied voltage increased. The maximum collection efficiency of either alternating or direct electric field was more than 98%, though the applied voltage of alternating electric field was higher than that of direct electric field. However, from the viewpoint of power consumption, the direct electric field had higher power consumption rate than alternating electric field at similar collection efficiency. For example, when the 0.2 μm particle penetration was about 4%, the power consumptions of alternating and direct electric field were 16 watt and 18 watt, respectively. Hence the separation quality of alternating electric field was better than that of direct electric field. Moreover, considerably lower ozone concentration was found in alternating electric field ESP, compared to direct electric field.

MEMS integrated narrow band infrared emitter and detector for infrared gas sensor

With the development of microfabrication technology, compact, lightweight, inexpensive and portable micro-spectrum detection and analyzing products are expected to be extensively applied in the future commercially. From the viewpoint of power consumption and compact volume, integration of various components on one substrate is desirable. In this work, integrated infrared gas sensor with micro infrared emitter and detector elements based on MEMS technology are developed. The integrated suspended infrared emitter and infrared micobolometers are designed and fabricated on a silicon substrate.

Improvement in quality of speech received by a mistuned receiver at suppressed carrier SSB

Single sideband modulation (SSB) is the most efficient speech transmission system from the viewpoint of power consumption and bandwidth occupation. It is widely used in amateur radio, mobile radio, and others. At suppressed carrier SSB(SCSSB), the receiver should tune to the carrier frequency accurately. Manual tuning, however, is very difficult due to the lack of the carrier signal. It fails in fine tuning at the reception and the quality of received speech degrades seriously owing to the shift of speech spectrum. This paper proposes a method to improve the quality of speech degraded at SCSSB. Received speech is transformed into the log spectrum and its autocorrelation function (ACLOS) is calculated. If tuning is carried out correctly, the log spectrum of voiced sound has a harmonic structure. Mistuning gives a spectrum shift on that frequency axis. On the other hand, ACLOS is always a periodic signal that corresponds to the harmonic structure. By calculating a cross-correlation function between ACLOS and the log spectrum, mistuning frequency can be easily estimated. This method is able to estimate the mistuning frequency within the accuracy of 10 Hz, even in noisy channels. After obtaining the mistuning frequency, the shifting spectrum of received speech is carried out and more natural speech is obtained.