Power Consumption Information Research Articles

Automatic Collection Method of Machining Progress Information for Large-size Workpieces Based on Reference Power Curve

Large-size workpieces are the common parts in the large equipment manufacturing industry. It is very significant for management staff to know the on-site machining progress information of the large-size workpieces in order to ensure the timely completion of jobs,improve production efficiency,optimize production management and support dynamic optimal schedule. Because the machining period of a large-size workpiece is long and in many cases only a single workpiece is machined,it is difficult to automatically collect the machining progress information. Based on this,the automatic collection method of machining progress information for large-size workpieces is proposed by using the power consumption information of the machine tool's main transmission system. The reference power curve of the machining workpiece is established based on the starting power database and the idle power database of the spindle transmission system of machine tools,which is obtained in advance,and the relative machining parameters,such as cutting parameters,workpiece material,and process time. Although the reference power curve is not exactly precise,the shape of the curve is enough to reflect the machining process of the workpiece. The machining progress information of the workpiece is collected by comparing the real-time data power curve with the reference power curve. The qualitative information is obtained by comparison of the shape characteristics of the two power curves ,and the quantitative progress data is calculated by analyzing the time of the two power curve. The case study of machining the large-size workpiece in a certain metallurgical equipment manufacturing workshop shows the method is practical.

A digital design flow for secure integrated circuits

Small embedded integrated circuits (ICs) such as smart cards are vulnerable to the so-called side-channel attacks (SCAs). The attacker can gain information by monitoring the power consumption, execution time, electromagnetic radiation, and other information leaked by the switching behavior of digital complementary metal-oxide-semiconductor (CMOS) gates. This paper presents a digital very large scale integrated (VLSI) design flow to create secure power-analysis-attack-resistant ICs. The design flow starts from a normal design in a hardware description language such as very-high-speed integrated circuit (VHSIC) hardware description language (VHDL) or Verilog and provides a direct path to an SCA-resistant layout. Instead of a full custom layout or an iterative design process with extensive simulations, a few key modifications are incorporated in a regular synchronous CMOS standard cell design flow. The basis for power analysis attack resistance is discussed. This paper describes how to adjust the library databases such that the regular single-ended static CMOS standard cells implement a dynamic and differential logic style and such that 20 000+ differential nets can be routed in parallel. This paper also explains how to modify the constraints and rules files for the synthesis, place, and differential route procedures. Measurement-based experimental results have demonstrated that the secure digital design flow is a functional technique to thwart side-channel power analysis. It successfully protects a prototype Advanced Encryption Standard (AES) IC fabricated in an 0.18-mum CMOS

AES-Based Security Coprocessor IC in 0.18-<tex>$muhbox m$</tex>CMOS With Resistance to Differential Power Analysis Side-Channel Attacks

Security ICs are vulnerable to side-channel attacks (SCAs) that find the secret key by monitoring the power consumption or other information that is leaked by the switching behavior of digital CMOS gates. This paper describes a side-channel attack resistant coprocessor IC fabricated in 0.18- <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$muhbox m$</tex> CMOS consisting of an Advanced Encryption Standard (AES) based cryptographic engine, a fingerprint-matching engine, template storage, and an interface unit. Two functionally identical coprocessors have been fabricated on the same die. The first coprocessor was implemented using standard cells and regular routing techniques. The second coprocessor was implemented using a logic style called wave dynamic differential logic (WDDL) and a layout technique called differential routing to combat the differential power analysis (DPA) side-channel attack. Measurement-based experimental results show that a DPA attack on the insecure coprocessor requires only 8000 encryptions to disclose the entire 128-bit secret key. The same attack on the secure coprocessor does not disclose the entire secret key even after 1 500 000 encryptions.

An instruction-level energy model for embedded VLIW architectures

In this paper, an instruction-level energy model is proposed for the data-path of very long instruction word (VLIW) pipelined processors that can be used to provide accurate power consumption information during either an instruction-level simulation or power-oriented scheduling at compile time. The analytical model takes into account several software-level parameters (such as instruction ordering, pipeline stall probability, and instruction cache miss probability) as well as microarchitectural-level ones (such as pipeline stage power consumption per instruction) providing an efficient pipeline-aware instruction-level power estimation, whose accuracy is very close to those given by RT or gate-level simulations. The problem of instruction-level power characterization of a K-issue VLIW processor is O(N/sup 2K/) where N is the number of operations in the ISA and K is the number of parallel instructions composing the very long instruction. One of the advantages of the proposed model consists of reducing the complexity of the characterization problem to O(K/spl times/N/sup 2/). The proposed model has been used to characterize a four-issue VLIW core with a six-stage pipeline.

Application of load survey systems to proper tariff design

This paper proposes a proper rate making strategy for a public owned utility by taking into account the customer load characteristics. The load survey system has been well designed by sampling theory to find the customers for power consumption information collection. By this manner, the typical load patterns derived can effectively represent the load behavior of each customer class. The load patterns of each test customer during different seasons are solved by statistical analysis according to the load information collected. The seasonal typical load pattern of each customer class is then determined by integrating the load patterns of the same type customers. The power consumption of the customer class is then estimated by the typical class load pattern and the energy consumption of all customers in the same class, which can be retrieved from the customer information database. The typical load pattern of whole power system is then determined by aggregating the power consumption of all customer classes. The estimated system load consumption is then compared to the actual system load profile, it is found that a rather accurate system load profile can be predicted by the load survey system.

Low Power Consumption Mobile Ad Hoc Network System

In order to solve the environmental crisis problem and to realize the sustainable environment, we need the efforts to reduce energy consumption. It is reported that the energy consumption by IT including communication will rapidly grow. Based on this situation, Japan Science and Technology Agency (JST) has begun the project of “Ultra low power consumption information technology” under the umbrella of the competitive research fund named “Core Research for Evolutional Science and Technology (CREST)”. We have applied to the open call for proposal and our proposal “Ultra low power Data Driven Networking System (ULPDDNS)” has been accepted as one of 2007-2012 frame projects by JST CREST. Our objective is to develop a data-driven networking system that can achieve reduction of power consumption to 1/100-1/1000 compared with the existing systems, especially in the situation just after a disaster happened. We believe the most applicable network to disaster situation is Mobile Ad hoc NETwork (MANET). This paper introduces the ULPDDNS research activities mainly from the viewpoint of network, i.e., MANET and shows three techniques to establish highly efficient and energy saving MANETswith reasonable performance: (1) GPS-aided target information discovery, (2) Load-aware broadcast-type contents delivery, and (3) Trust relationship list based key management.