Power Consumption In VLSI Circuits Research Articles

3T-SAPON technique to reduce Power Consumption

Scaling down CMOS technology has rapidly improved cost, area effectiveness, switching speed of the circuits & high device reliability. However, scaling has an immense impact on static power consumption in VLSI circuits. For battery operating applications higher power dissipation is not desirable because it reduces the efficiency and cooling effects of the battery. Thus, designing a low-power consuming circuit has become the major criteria in circuit designs. A new circuit model called 3T-SAPON is designed to reduce static power consumption. 3T-SAPON technique power consumption has been reduced around 45%. Using this technique inverter, NAND are implemented and compared with some of the existing standard techniques like LCNT, LECTOR, ONOFIC and SAPON. All these circuits are simulated in Cadence 90nm technology.

High-Speed, Energy-Efficient Magnetic Nonvolatile Flip-Flop With Self-Adaptive Write Circuit Utilizing Voltage-Controlled Magnetic Anisotropy

Flip-flops (FFs) account for a very significant portion of the entire power consumption of VLSI circuits. Magnetic tunnel junctions (MTJs) can be combined with conventional FFs to achieve nonvolatility, almost unlimited write times, and higher energy efficiency. The mainstream MTJ switching mechanisms include spin-transfer torque (STT), spin-orbit torque (SOT), and voltage-controlled magnetic anisotropy (VCMA) effect, among them the first two mechanisms all facing the disadvantages of both large writing energy and writing latency. Instead, utilizing the VCMA effect to switch MTJ only needs a sub-nanosecond and has low energy consumption, which is more energy-efficient. In this article, first, a double-stage pre-charge sense amplifier (DPCSA) is proposed, reducing 53.9% of sensing delay compared with the conventional one. Second, based on DPCSA, a VCMA-MTJ-based multi-bit shared magnetic nonvolatile FF (MNV-FF) with a self-adaptive writing circuit is designed, achieving high speed and energy efficiency for backup and restore operations. Finally, by extending the MNV-FF, a magnetic nonvolatile register group (MNV-RG) with high area efficiency can be obtained. An SMIC 55 nm CMOS design kit and a VCMA-MTJ compact model described by Verilog-A language are used for hybrid simulation on the Cadence/Specter Platform. Simulation results in $0.7\times $ and $1.3\times $ of the improvements in data backup time and backup energy, respectively, compared with the efficient VCMA-MTJ-based MNV-FF. Two more improvements of $158.7\times $ and $19.6\times $ in data restore time and restore energy are also achieved in the same comparison.

Design of modified low power CMOS differential ring oscillator using sleepy transistor concept

As the technology feature size shrinks, leakage power is dominating in the total chip power consumption of VLSI circuits. In this work to reduce the leakage power, sleepy transistor technique is used for differential ring oscillator (RO). First design is proposed using CMOS inverter stage in a differential manner to form ring oscillator with sleepy NMOS and sleepy PMOS transistors. Second design of differential ring oscillator is proposed with CMOS cross-coupled cell with sleepy NMOS and PMOS transistors. Further, substrate-biasing concept has been applied to proposed design for improvement in the power consumption. The power consumption for sleepy NMOS inverter stage differential ring oscillator (RO) is 0.696–0.953 mW and the frequency of operation is 3.09–4.56 GHz. Sleepy NMOS cross-coupled based ring oscillator design shows the power consumption of 0.78–1.21 mW at an operating frequency of 2.23–4.25 GHz. The power consumption for sleepy PMOS inverter stage differential RO design is 1.95–2.04 mW and the frequency of operation is 4.41–4.63 GHz. Further, sleepy PMOS cross-coupled RO design shows power consumption of 0.97–1.06 mW at an operating frequency of 2.26–2.41 GHz. The substrate biasing of sleepy NMOS inverter stage ring oscillator design gives power consumption of 0.862–0.924 mW and the frequency of operation is 4.16–4.45 GHz. Substrate biasing of sleepy NMOS cross-coupled ring oscillator design shows power consumption of 1.06–1.16 mW and output frequency varies from 1.86–2.05 GHz. The simulations have been performed using SPICE in 0.18 µm CMOS technology. Results of power consumption, tuning range, phase noise, FoM and output frequency have been compared with earlier circuits and proposed circuits show improvement in results.

Optimization of Power Consumption in VLSI Circuit

Increasing speed and complexity of design gives a significant increase in power consumption in VLSI chips. Speed, power consumption and space are major issues in VLSI circuit. To meet these challenges there are certain design techniques which are used to reduce power. Optimization of power can be done by considering various components such as transistor sizing, voltage scaling, variable VDD, multiple threshold voltages, voltage islands, power gating, long channel transistor, stacking & parking states and logic styles etc. Power consumption in VLSI circuit is data dependent. In this paper different design methods are tested to optimize the power. It is found that algorithm based design reduces gate switching activity that results reduction of power in multiplier circuit. Keyword: Transistor sizing, voltage scaling, variable VDD, multiple threshold voltages, voltage islands, long channel transistor, stacking & parking states, logic styles, Genetic algorithm, Booth multiplication I. Introduction Reduction in power dissipation is an important design issue in VLSI circuits. The design parameters have major effect on the overall performance of the system. On the basis of component used and their function different optimization techniques can be used. For example in case of multiplier power consumption depends upon data. This is because switching contributes to more power consumption. This can be optimized by using various gate combinations. Gate switching can be reduced by using algoritms. For example of in case of multiplier design method Booth algorithm as well as modified Booth algorithm can be used for efficient multiplication. In this paper various approaches are used for power consumption eg. transistor sizing, voltage scaling, variable VDD, multiple threshold voltages, voltage islands, long channel transistor, stacking& parking states, logic styles, Genetic algorithm, Booth multiplication etc. This paper is divided into five sections. First section is of introduction. Second section is about preliminary studies. Third section includes different design methods and their testing. Fourth section is of comparison with discussion. Finally, fifth section is conclusion of the work reported here.

Optimization of Power Consumption in VLSI Circuit

Optimization of Power Consumption in VLSI Circuit

A New Statistical Method for Maximum Power Estimation in CMOS VLSI Circuits

A method for maximum power estimation in CMOS VLSI circuits is proposed. The method is based on extreme value theory and allows for the calculation of the upper end point of the probability distribution which is followed by the instantaneous power drawn from the supply bus. The main features of the method are the relatively small and circuitin-dependent subset of input patterns required for accurate prediction of maximum power and its simulative nature which ensures that no over-simplifying assumptions are made. Application of the proposed method to eight distributions, which come close to the behavior of power consumption in VLSI circuits, proved its superior capabilities with respect to existing methods.