Power Consumption In Digital Circuits Research Articles

A Gate-Level Power Estimation Approach with a Comprehensive Definition of Thresholds for Classification and Filtering of Inertial Glitch Pulses

Estimation of power consumption in digital circuits is performed at gate-level simulation. Its accuracy depends on the models of gate delays that capture the effects of spurious signal transitions, called “glitches”. Electronic Design Automation (EDA) software considers inertial gate delays and represses a glitch in the cell’s output if its width is below a threshold. Selecting threshold values for the inertial glitch classification and filtering is crucial for precise power estimations. In this direction, we explore the effectiveness of automatically adjusting such thresholds on a cell-specific basis according to the local cell’s information. We used a commercial industry-standard gate-level power estimation tool and a 32 nm CMOS standard cell library. Via power measurements in circuit simulations, we created customized lookup tables for each library cell employed in the benchmark circuits. We compared the proposed approach’s performance with other methods for glitch threshold definition. Our method demonstrated good power estimation accuracy while presenting the lowest mean absolute error among all the cells of the circuits under test and the smallest standard deviation. The latter suggests that the proposed method achieves better cell-specific accuracy, which is expected to allow for more precise circuit-level power estimations in complex circuits with a large number of combinational cells.

Comparison between Power Dissipation and Propagation Delay on 6T SRAM Cell Design Using GDI Logic with Transmission Gate VMSA and Voltage Divider

The rapid evolution of the semiconductor industry has witnessed shrinking portable and mobile devices alongside an increasing demand for extended battery life. Addressing the critical challenges of speed and battery life in digital devices, this paper investigated the effectiveness of innovative low-power design techniques. Focusing on the Gate Diffusion Input (GDI) approach, a recent advancement in the field, a comprehensive analysis revealed its significant potential for reducing power consumption in digital circuits. Additionally, a comparative analysis was conducted to evaluate the performance of conventional 6T GDI SRAM cells and their Modified 6T GDI SRAM with Voltage Divider, considering the influence of Sense Amplifiers. Simulation data demonstrated that Modified 6T SRAM designs, particularly the Voltage Divider and TGVMSA variants, achieved significantly lower power dissipation and delay despite having a larger cell area. Remarkably, the proposed design substantially improved power dissipation and propagation delay, achieving 1.3 ps, and 889.41mV at 1.8V shows that the suggested design enhances power dissipation and propagation delay. These findings suggest that the proposed design offers a promising strategy for enhancing power efficiency and performance in digital devices, thereby mitigating the limitations of battery life and speed in the modern technological landscape.

Tunneling towards efficiency: A survey of design and optimization strategies for tunnel FETs in ultra-low power applications

The tunnel field-effect transistor (TFET) is a promising technology for low-power applications due to its high performance at reduced voltages through quantum tunneling. This article overviews TFETs and their potential to reduce power consumption in digital circuits, analog circuits, and energy harvesting applications. It highlights the challenges faced in TFET design, including gate electrostatics, source doping, and off-state limitations. The importance of design considerations and material selections is discussed, emphasizing their impact on TFET performance. Various fabrication techniques for TFETs are explored, highlighting their significance in achieving efficient and effective devices. The review concludes by stressing the need for further research and development to address existing challenges and unlock the full potential of TFETs in low-power electronic systems.

Voltage over‐scaling CNT‐based 8‐bit multiplier by high‐efficient GDI‐based counters

A new low-power and high-speed multiplier is presented based on the voltage over scaling (VOS) technique and new 5:3 and 7:3 counter cells. The VOS reduces power consumption in digital circuits, but different voltage levels of the VOS increase the delay in different stages of a multiplier. Hence, the proposed counters are implemented by the gate-diffusion input technique to solve the speed limitation of the VOS-based circuits. The proposed GDI-based 5:3 and 7:3 counters save power and reduce the area by 2x and 2.5x, respectively. To prevent the threshold voltage (Vth) drop in the suggested GDI-based circuits, carbon nanotube field-effect transistor (CNTFET) technology is used. In the counters, the chirality vector and tubes of the CNTFETs are properly adjusted to attain full-swing outputs with high driving capability. Also, their validation against heat distribution under different time intervals, as a major issue in the CNTFET technology is investigated, and their very low sensitivity is confirmed. The low complexity, high stability and efficient performance of the presented counter cells introduce the proposed VOS-CNTFET-GDI-based multiplier as an alternative to the previous designs.

Comparative Analysis of Single-Phase-Clocked Low Power Flip-Flops with Transmission-Gate Flip-Flop

Flip-flops are fundamental building block in designing the digital circuits. They contribute significant amount of power consumption in the digital systems. In the modern era of VLSI design, power consumption has become crucial factor. As the technology is scaled down below 65nm, leakage power contributes significantly to overall power consumption of digital circuits. Since, Flip-flop is a fundamental building block in designing digital systems, reducing the power consumption of Flip-flop is required to achieve low power consumption of digital systems. Recently single-phase clocking technique has been employed in designing FFs to achieve low power consumption. This technique reduces excess loading on the clock signal. In this article performance of recent single-phase clocked FFs is compared with the conventional transmission-gate Flip-flop. Also, drawbacks of these FFs are discussed. For the comparison of performance of single-phase-clocked FFs with conventional transmission-gate FF, all the simulations are performed at 45-nm predictive technology on Tanner EDA tool.

Comparison of Vedic Multiplier Implementation Using Gate Diffusion Input and Modified Gate Diffusion Input Techniques

Vedic maths is an ancient mathematical theory based on 16 sutras that has a unique computation technique. We employ the fourteenth sutra, 'Urdhva Tiryakbhyam', from the 16 sutras. Multiplication can be done 'vertically and crosswise' using this sutra. The creation of a high-speed Vedic Multiplier based on ancient Indian Vedic Mathematics principles that have been tweaked to boost efficiency. Power, area, and latency are the three fundamental restrictions in modern VLSI technological advancements. Multipliers are used in high-speed arithmetic logic units, multiplier and accumulate units, and other similar applications. With the rising limits on latency, the design of faster multiplications is becoming increasingly important. Many changes are being done to improve speed. Vedic multipliers based on Vedic Mathematics are among them. Power, area, and latency are the three fundamental restrictions in modern VLSI technological advancements. CMOS (Complementary metal-oxide-semiconductor) designs take up more space and use more energy. Power dissipation causes an IC to heat up, which has a direct impact on its reliability and performance. Gate Diffusion Input (GDI) technology reduces the size, propagation delay, and power consumption of digital circuits while also lowering logic complexity as compared to traditional CMOS and existing pass transistor logic approaches. We compared a 2x2 Vedic multiplier based on the GDI and mGDI (Modified GDI) techniques in this study. In comparison to the GDI approach, the mGDI technology employs much less transistors. The Vedic multiplier is implemented in the cadence virtuoso tool, on 180nm and 90nm technology.

LOW POWER DIGITAL FILTERING USING ADAPTIVE APPROXIMATE PROCESSING: FIR FILTER STRUCTURES

Techniques for reducing power consumption in digital circuits have become increasingly important because of the growing demand for portable multimedia devices. Digital filters, being ubiquitous in such devices, are a prime candidate for low power design. Algorithmic approaches to low power frequency-selective digital filtering which are based on the concepts of adaptive approximate processing have been developed and formalized by introducing the class of approximate filtering algorithms in which the order of a digital filter is dynamically varied to provide time-varying stopband attenuation in proportion to the time-varying signal-to-noise ratio (SNR) of the input signal, while maintaining a fixed SNR at the filter output. Since power consumption in digital filter implementations is proportional to the order of the filter, dynamically varying the filter order is a strategy which may be used to conserve power. In this paper we introduce a class of approximate filter structures using FIR digital filter constituent elements. These filter structures are explored and shown to be an important element in the characterization of approximate filtering algorithms.

The Importance of Energy Efficiency in Engineering and Informatics

Techniques for reducing power consumption in digital circuits that underly automatic control of modern engineering systems are of paramount importance due to the simultaneously growing demands for portable multimedia devices and energy conservation. Digital filters, being ubiquitous in such devices, are thus a prime candidate for low power design. We review an algorithmic approach to low power frequency-selective digital filtering, an essential ingredient for energy efficient technological innovation in many domains.

The Importance of Energy Efficiency in Engineering and Informatics

Techniques for reducing power consumption in digital circuits that underly automatic control of modern engineering systems are of paramount importance due to the simultaneously growing demands for portable multimedia devices and energy conservation. Digital filters, being ubiquitous in such devices, are thus a prime candidate for low power design. We review an algorithmic approach to low power frequency-selective digital filtering, an essential ingredient for energy efficient technological innovation in many domains.

On the Accuracy in Modeling the Statistical Distribution of Random Telegraph Noise Amplitude

The power consumption of digital circuits is proportional to the square of operation voltage and the demand for low power circuits reduces the operation voltage towards the threshold of MOSFETs. A weak voltage signal makes circuits vulnerable to noise and the optimization of circuit design requires modelling noise. Random Telegraph Noise (RTN) is the dominant noise for modern CMOS technologies and Monte Carlo modelling has been used to assess its impact on circuits. This requires statistical distributions of RTN amplitude and three different distributions were proposed by early works: Lognormal, Exponential, and Gumbel distributions. They give substantially different RTN predictions and agreement has not been reached on which distribution should be used, calling the modelling accuracy into questions. The objective of this work is to assess the accuracy of these three distributions and to explore other distributions for better accuracy. A novel criterion has been proposed for selecting distributions, which requires a monotonic reduction of modelling errors with increasing number of traps. The three existing distributions do not meet this criterion and thirteen other distributions are explored. It is found that the Generalized Extreme Value (GEV) distribution has the lowest error and meet the new criterion. Moreover, to reduce modelling errors, early works used bimodal Lognormal and Exponential distributions, which have more fitting parameters. Their errors, however, are still higher than those of the monomodal GEV distribution. GEV has a long distribution tail and predicts substantially worse RTN impact. The work highlights the uncertainty in predicting the RTN distribution tail by different statistical models.

Asymptotically Optimal Low-Power Digital Filtering Using Adaptive Approximate Processing

Techniques for reducing power consumption in digital circuits have become increasingly important because of the growing demand for portable multimedia devices. Digital filters, being ubiquitous in such devices, are a prime candidate for low-power design. We present a new algorithmic approach to low-power frequency-selective digital filtering which is based on the concepts of adaptive approximate processing. This approach is formalized by introducing the class of approximate filtering algorithms in which the order of a digital filter is dynamically varied to provide time-varying stopband attenuation in proportion to the time-varying signal-to-noise ratio (SNR) of the input signal, while maintaining a fixed SNR at the filter output. Since power consumption in digital filter implementations is proportional to the order of the filter, dynamically varying the filter order is a strategy which may be used to conserve power. From this practical technique we abstract a theoretical problem which involves the determination of an optimal filter order based on observations of the input data and a set of concrete assumptions on the statistics of the input signal. Two solutions to this theoretical problem are presented, and the key results are used to interpret the solution to the practical low-power filtering problem. We construct a framework to explore the statistical properties of approximate filtering algorithms and show that under certain assumptions, the performance of approximate filtering algorithms is asymptotically optimal.

Optimizing Power in Sequential Circuits by Reducing Leakage Current using Enhanced Multi Threshold CMOS

Technical thirst of man is in exponential rise and posing critical challenges in using this technology. This is much evident in the design of VLSI circuits. Sequential circuit designing demands lesser energy consumption, smartness and increased functional density. In this domain, every development in the recent past has energy as the focal point. MTCMOS exactly serves the purpose of reduced power consumption in digital circuits. This technique provides lower leakage current and offers enhanced speed. It uses low threshold voltage devices for low leakage and high threshold voltage components as sleep transistors. These sleep transistors are good enough to isolate the logic modules from the supply, ground in order to reduce the leakage current. Care is ensured particularly in the mode transition and also the least possible time for turn ON state in a circuit, as these are the primary concerns for power consumption and thereby for the performance degradation of integrated circuits. In this paper, a successful attempt was made in enhancing the advantage of employing MTCMOS technique towards lesser power consumption in sequential circuit designing.

Novel Design of Reversible MUX and DEMUX using GDI Techinque

Now a day’s Reversible logic is playing a crucial role in designing of digital circuits and it is used in reducing power consumption in digital design. By regaining the bit loss it reduces the power consumption in digital circuits. Gate diffusion input (GDI) is a technique of low-power digital circuit design. This technique reduces the power consumption, delay, and transistor count by maintaining the complexity very low of logic design. In these paper a novel MUX and DEMUX has been presented, which can be extended up to 1:2n and 2n:1 respectively and these are developed by using only one type of Reversible gate i.e. Fredkin Gate (FRG) and Not Gate. The simulations are done in H-Spice using 90nm technology.

Clock gating methodologies and tools: a survey

SummaryClock gating (CG) is a widely used design method for reducing the dynamic power consumption in digital circuits. Although it is a mature technique, theoretical work and tools for its application are still evolving and considered a matter of ongoing research, due to its significant effect in the overall power of the designs under study. This paper introduces a detailed review of the spectrum of CG approaches, theoretical and practical, from an architectural and register transfer level to synthesis, place and route, and testing issues. Furthermore, tools availability, limitations, and requirements concerning CG are examined for each design flow step. Conclusively, an evaluation of the presented techniques and literature is provided, estimating their usefulness and identifying areas for future research, exploration, and automation. Copyright © 2015 John Wiley & Sons, Ltd.

Continuous-time analog filter in CMOS nanoscale era

Analog filters are key blocks in analog signal processing. They are widely employed in many systems, like wireless transceivers, detectors read-out, sensors interfaces, etc. The IC technology choice for such systems is mainly dictated by the requirements of high speed and low power consumption of digital circuits. This pushed an impressive movement towards scaled technology and this has important consequences on the analog circuits design. The impact of technology scaling down to nanometre scale on analog filters design is here investigated. For instance, supply voltage reduction in analog filters limits circuits design solutions and could result in higher power consumption. Moreover, at the same time, innovative systems push analog filters to get higher and higher operation frequencies, due to the increasing bandwidth/speed requirements. Recent solutions for efficient low-voltage and high frequency analog filters in nanometre technology are described.

High performance 8 bit cascaded carry look ahead adder with precise power consumption

SummaryMultiple bit adders like ripple carry adder make the propagation of carry bit very slow and this is the reason why it must be replaced with fast adders as carry‐look‐ahead adder (CLA). Power consumption in digital circuits depends on the number of metal–oxide–semiconductor field‐effect transistor employed and various other parameters. If number of metal–oxide–semiconductor field‐effect transistor is reduced the power consumption would definitely be reduced. Conventional CLAs would consume significant amount of power that still needs to be improved. The paper here deals with the implementation of 8 bit CLA with the aim of reducing the size and to precise the power consumption within nanowatt range, by improving the fundamental components of the circuit. All the parameters have been calculated by using Cadence Virtuoso tool at 45 nm technology. Copyright © 2014 John Wiley & Sons, Ltd.

A Review on Energy Efficient CMOS Digital Logic

Autonomy of power supply used in portable devices directly depends on energy efficiency of digital logic. This means that digital systems, beside high processing power and very complex functionality, must also have very low power consumption. Power consumption depends on many factors: system architecture, technology, basic cells topology-speed, and accuracy of assigned tasks. In this paper, a review and comparison of CMOS topologies techniques and operating modes is given, as CMOS technology is expected to be the optimum choice in the near future. It is shown that there is a full analogy in the behavior of digital circuits in sub-threshold and strong inversion. Therefore, synthesis of digital circuits is the same for both strong and weak operating modes. Analysis of the influence of the technology, MOS transistor threshold voltage (Vt) and power supply voltage (Vdd) on digital circuit power consumption and speed for both operating modes is given. It is shown that optimal power consumption (minimum power consumption for given speed) depends on optimal choice of threshold, and power supply voltage. Multi Vdd /Vt techniques are analyzed as well. A review and analysis of alternative logical circuit's topologies – pass logic (PL), complementary pass logic (CPL), push-pull pass logic (PPL) and adiabatic logic – is also given. As shown, adiabatic logic is the optimum choice regarding energy efficiency.

Reliability assessment of CMOS differential cross-coupled LC oscillators and a novel on chip self-healing approach against aging phenomena

In this paper, reliability of CMOS differential cross-coupled LC oscillators is examined, and a novel on chip aging detection and healing technique is developed to increase the lifetime of oscillator circuits. Aging causes degradation in several transistor parameters, such as threshold voltage, mobility, and transconductance. While these changes cause irregular timing characteristics and increased power consumption in digital circuits, the case is quite different for their analog counterparts. Analog circuits, especially nonlinear ones, show more deviations at the output due to parameter changes. In order to evaluate the aging effects on nonlinear analog circuits, two different oscillator structures (n-type and p-type) with 5GHz oscillation frequency were designed using 0.13μm technology. The phase noise analysis of fresh and aged oscillators was performed analytically and through simulations. Based on these analyses the robustness of oscillators was discussed. Finally, an on chip aging sensor and self recovery mechanism are proposed to increase the robustness of the CMOS LC oscillators.

A Fast and Near-Optimal Clustering Algorithm for Low-Power Clock Tree Synthesis

Clocks are known to be major source of power consumption in digital circuits. In this paper, we propose a clustering algorithm for the minimization of power in a local clock tree. Given a set of sequentials and their locations, clustering is performed to determine the clock buffers that are required to synchronize the sequentials, where a cluster implies that a clock buffer drives all the sequentials in the cluster. The results produced by the algorithm are often within 1.3 × of the lower bound and have 32% lower costs, on average, than those due to an approximation algorithm with 2.5 × faster runtimes. Compared to competitive heuristic from a vendor tool, the results due to the algorithm on several blocks in microprocessor designs in advanced nanometer technologies show 14% reduction, on average, in clock tree power while meeting skew or slew constraints. The algorithm has been employed for clock tree synthesis for several microprocessor designs across process generations due to consistently significant clock tree power savings over the results due to competitive alternatives.

Dynamic Supply and Threshold Voltage Scaling for CMOS Digital Circuits Using In-Situ Power Monitor

A generalized power tracking algorithm that minimizes power consumption of digital circuits by dynamic control of supply voltage and the body bias is proposed. A direct power monitoring scheme is proposed that does not need any replica and hence can sense total power consumed by load circuit across process, voltage, and temperature corners. Design details and performance of power monitor and tracking algorithm are examined by a simulation framework developed using UMC 90-nm CMOS triple well process. The proposed algorithm with direct power monitor achieves a power savings of 42.2% for activity of 0.02 and 22.4% for activity of 0.04. Experimental results from test chip fabricated in AMS 350 nm process shows power savings of 46.3% and 65% for load circuit operating in super threshold and near sub-threshold region, respectively. Measured resolution of power monitor is around 0.25 mV and it has a power overhead of 2.2% of die power. Issues with loop convergence and design tradeoff for power monitor are also discussed in this paper.