Power Bus Noise Research Articles

Characterization and Extraction of Power Loop Stray Inductance With SiC Half-Bridge Power Module

The power loop stray inductances of the silicon carbide (SiC) half-bridge power module (HBPM) must be included in the circuit simulation model to predict the power device switching characteristics and the power bus noise caused by the power converter. Instead of a full equivalent circuit model of the SiC HBPM, a simplified but accurate three-terminal equivalent circuit model is presented in this article. Based on the simplified model, a novel frequency-domain impedance measurement method based on the two-port network technique is proposed to extract the power loop inductances through direct measurement. By using the extracted power loop inductances of a 1.2-kV 300-A SiC HBPM, a three-terminal equivalent model of the HBPM is obtained, and its accuracy is validated by the finite element method and experiments.

Practical EBG application to multilayer PCB: Impact on power integrity

This work reviews the use of planar electromagnetic bandgap structures for power bus noise reduction in the GHz band. The key points for a quick and efficient design of planar EBG are also reviewed. A practical application example is offered that is able to combine a good reduction level of power bus noise, together to a limited impact for the interconnects referenced to the EBG patterned plane. This latter effect is investigated in details in a follow-up article. The case study focuses on the EBG laid out on an inner stack-up layer, to avoid loosing generality in the EBG implementation. The placement of the additional stitching vias required by the embedded EBG layout is investigated and discussed extensively. Simulation results are provided to validate the proposed EBG layout techniques.

Determining the Maximum Allowable Power Bus Voltage to Ensure Compliance With a Given Radiated Emissions Specification

It is generally understood that excessive power bus noise voltage on a printed circuit board will result in unacceptable radiated emissions levels, but how much noise is too much? In this paper, an analysis based on a lossy cavity model is performed to determine the maximum possible radiated field corresponding to a given power bus noise voltage. A closed-form expression relating the maximum power bus noise voltage to the radiation peaks is then derived. This expression is solved in reverse to determine the minimum power bus voltage that is necessary to generate a radiated field above a specified limit. When troubleshooting a radiated emissions problem, this expression can be applied to measured values of power bus noise voltage to determine whether radiation directly from the power bus is potentially the emissions source.

Modeling Radiated Emissions Due to Power Bus Noise From Circuit Boards With Attached Cables

A two-step technique for modeling the radiation from circuit boards with attached cables is developed and applied to various board-cable structures. The technique divides a complex source geometry into two components. One component consists of differential-mode sources and the pieces of the structure that contribute to the differential-mode radiation. The other component consists of common-mode sources at cable attachment points and the parts of the structure that play a role in the radiation due to common-mode cable currents. The two component geometries are much easier to model than the complete structure. This modeling approach also provides the modeler with insight regarding the design parameters that most influence one type of radiation or the other.

Importance and Limitations of Modeling Parasitic Capacitance between Package and PCB for Power Bus Noise and Radiation

Power and ground planes on multilayer PCBs can effectively radiate electromagnetic fields excited by the IC simultaneous switching noise. The high frequency electromagnetic radiation is often calculated from the electric field along the edge of the PCB, which can be estimated with a cavity model using magnetic walls. The excitation of the cavity modes is related to the via current passing through the power bus planes at the interconnection between IC package and PCB. Usually the attention is focused on the differential-mode current of the package pins, but in the present paper it is shown that the common-mode current flowing out from package pins plays a very important role in the excitation of cavity modes, and its neglect implies a fatal underestimation of the electromagnetic radiation from the power bus planes in some circumstances. A second important contribute to the radiation is given by the common mode current on the pins, together with the current flowing on the PCB ground plane. With the proposed equivalent circuit, the effectiveness of decoupling inductors depending on their location and on the value of the parasitic capacitance is studied.

Modeling and Simulation of Via-Connected Power Bus Stacks in Multilayer PCBs

Power bus noise problem has become a major concern for both EMC engineers and board designers. A fast algorithm, based on the cavity-mode model, was employed for analyzing resonance characteristics of multilayer power bus stacks interconnected by vias. The via is modeled as an inductance and its value is given by a simple expression. Good agreement between the simulated results and measurements demonstrates the effectiveness of the cavity-mode model, together with the via model.

Coupling between differential signals and the dc power-bus in multilayer PCBs

Differential and common-mode transfer impedances are proposed herein to analyze noise coupled to (from) the dc power-bus from (to) via transitions in differential signals. Expressions for the two transfer impedances in terms of conventional single-ended transfer impedances are derived and verified through measurements, full-wave finite-difference time-domain (FDTD) simulations and an analytical cavity model. Some properties of the differential and common-mode transfer impedances are investigated to facilitate engineering design. The impact of signal current imbalances on power-bus noise and the benefit of differential signals as compared to single-ended signals are quantified.

An efficient path-based equivalent circuit model for design, synthesis, and optimization of power distribution networks in multilayer printed circuit boards

In high-speed printed circuit boards, the decoupling capacitors are commonly used to mitigate the power-bus noise that causes many signal integrity problems. It is very important to determine their proper locations and values so that the power distribution network should have low impedance over a wide range of frequencies, which demands a precise power-bus model considering the decoupling capacitors. However, conventional power-bus models suffer from various problems, i.e., the numerical analyzes require huge computation while the lumped circuit models show poor accuracy. In this paper, a novel power-bus model has been proposed, which simplifies the n-port Z-parameters of a power-bus plane to a lumped T-network circuit model. It exploits the path-based equivalent circuit model to consider the interference of the current paths between the decoupling capacitors, while the conventional lumped models assume that all decoupling capacitors are connected in parallel, independently with each other. It also models the equivalent electrical parameters of the board parasitic precisely, while the conventional lumped models employ only the inter-plane capacitance of the power-ground planes. Although it is a lumped model for fast and easy calculation, experimental results show that the proposed model is almost as precise as the numerical analysis. Consequently, the proposed model enables a quick and accurate optimization of power distribution networks in the frequency domain by determining the locations and values of the decoupling capacitors.

The development of a closed-form expression for the input impedance of power-return plane structures

In multilayer printed circuit boards, the noise on the power bus is influenced by the impedance between the power and ground planes. Power-bus noise estimates require an accurate estimate of the power-bus input impedance. This paper develops a closed-form estimate of the input impedance for circular power-return plane structures. When the structure is lossy (e.g., boards employing embedded capacitance or densely populated boards), the energy reflected from the board edge does not significantly affect the input impedance. In general, the expressions developed here for circular structures can be used to estimate the impedance of lossy power-return plane structures of any shape.

DC power-bus noise isolation with power-plane segmentation

Power-plane segmentation is often used for DC power-bus noise isolation in multilayer printed circuit board (PCB) designs. To achieve a desirable noise isolation, different power-plane segmentations can be used. A suitable modeling approach, as well as measurements, were employed in this work to study the noise isolation with several power-plane segmentation designs. The geometries studied include power islands, and totally segmented power planes. The effects of the power-bus noise isolation with different types of power island connections, locations of segmentation, and shapes were analyzed, and compared. The modeled and measured results show that suitable power-plane segmentation can result in significant power-bus noise isolation.

Investigation of the radiation from parallel-plane power-bus structures on printed circuit boards

The electromagnetic radiation of multilayer boards due to power-bus noise is investigated within the scope of electromagnetic compatibility. The analytic computation of the far field is based on the field equivalence principle, using a lossy cavity model for the required boundary electric field distribution. The maximum electric field is studied within the frequency range of 30 MHz–1 GHz. A parameter study clearly shows that the most effective parameter to lower radiation is the distance between the planes.

Power-bus decoupling with embedded capacitance in printed circuit board design

This paper experimentally investigates the effectiveness of embedded capacitance for reducing power-bus noise in high-speed printed circuit board designs. Boards with embedded capacitance employ closely spaced power-return plane pairs separated by a thin layer of dielectric material. In this paper, test boards with four embedded capacitance materials are evaluated. Power-bus input impedance measurements and power-bus noise measurements are presented for boards with various dimensions and layer stack ups. Unlike discrete decoupling capacitors, whose effective frequency range is generally limited to a few hundred megahertz due to interconnect inductance, embedded capacitance was found to efficiently reduce power-bus noise over the entire frequency range evaluated (up to 5 GHz).

Application of the cavity model to lossy power-return plane structures in printed circuit boards

Power-return plane pairs in printed circuit boards are often modeled as resonant cavities. Cavity models can be used to calculate transfer impedance parameters used to predict levels of power bus noise. Techniques for applying the cavity model to lossy printed circuit board geometries rely on a low-loss assumption in their derivations. Boards that have been designed to damp power bus resonances (e.g., boards with embedded capacitance) generally violate this low-loss assumption. This paper investigates the validity of the cavity model when applied to printed circuit board structures where the board resonances are significantly damped. Cavity modeling results for sample lossy power-return plane structures are validated using a three-dimensional full wave numerical code. A simple method is also established to check the validity of the cavity model for a power-return plane structure with imperfect conductors and lossy dielectric substrates.

Power bus isolation using power islands in printed circuit boards

Power islands are often employed in printed circuit board (PCB) designs to alleviate the problem of power bus noise coupling between circuits. Good isolation can be obtained over a wide frequency band due to the large series impedance provided by the gap between the power islands. However, power bus resonances may degrade the isolation at high frequencies. The amount of isolation also depends on the type of connection between power islands and the components on the board. This paper experimentally investigates the effectiveness of several power island structures up to 3.0 GHz.

Power Supply Design Parameters for Switching-Noise Control in Deep-Submicron Circuits Design Flows

In high performance integrated circuits phenomena like crosstalk, i>IR drops, electromigration and ground bounce are assuming increasing proportions because of the growing complexity in ultra deep submicron designs: their effects are assuming increasing impact compromising circuits functionality and not only their performances. This paper suggests a methodology to evaluate and to prevent power supply noise generation in more and more increasing dimensions circuit blocks. The power supply busses modeling is addressed to find out actual parameters to face early in the design phase noise phenomena related to power distribution. In particular using the equations reported in this paper the designer has the possibility to control the global power bus noise generation depending on the design strategy used, on the library characteristics and on the given performance constraints. The appropriateness of the developed methodology seems to be helpful if applied during the circuit design flow in conjunction with a project tool having as a target noise reduction besides delay and power optimization.

Quantifying SMT decoupling capacitor placement in dc power-bus design for multilayer PCBs

Noise on a dc power-bus that results from device switching, as well as other potential mechanisms, is a primary source of many signal integrity (SI) and electromagnetic interference (EMI) problems. Surface mount technology (SMT) decoupling capacitors are commonly used to mitigate this power-bus noise. A critical design issue associated with this common practice in high-speed digital designs is placement of the capacitors with respect to the integrated circuits (ICs). Local decoupling, namely, placing SMT capacitors in proximity to ICs, is investigated in this study. Multilayer PCB designs that employ entire layers or area fills for power and ground in a parallel plate structure are considered. The results demonstrate that local decoupling can provide high-frequency benefits for certain PCB geometries through mutual inductive coupling between closely spaced vias. The associated magnetic flux linkage is between the power and ground layers. Numerical modeling using an integral equation formulation with circuit extraction is used to quantify the local decoupling phenomenon. Local decoupling can effectively reduce high-frequency power-bus noise, though placing capacitors adjacent to ICs may limit routing flexibility, and tradeoffs need to be made based on design requirements. Design curves are generated as a function of power-bus layer thickness and SMT capacitor/IC spacing using the modeling approach to quantify the power-bus noise reduction for decoupling capacitors located adjacent to devices. Measurement data is provided to corroborate the modeling approach.

Power-supply decoupling on fully populated high-speed digital PCBs

The effectiveness of buried capacitance technology, used with discrete surface mounted decoupling capacitors, in reducing circuit malfunctions due to the noise voltage between power/ground planes in a multilayer printed circuit board is investigated. The analysis is carried out on a fully populated multilayer board, where an integrated circuit with very large package provides a lot of digital signals with measured rise/fall times equal to 400 ps. The role of the integrated circuit's package in damping out the resonance peaks at resonance frequencies on the power plane is highlighted. The relations between the power-bus transfer impedance and noise spectrum are also studied, in order to better evaluate the effects of the buried capacitance technology and decoupling capacitors on the power-bus noise filtering.

EMI mitigation with multilayer power-bus stacks and via stitching of reference planes

General methods for reducing printed circuit board (PCB) emissions over a broad band of high frequencies are necessary to meet EMI requirements, as processors become faster and more powerful. One mechanism by which EMI can be coupled off a PCB or multichip module (MCM) structure is from high-frequency fringing electric fields on the DC power and reference planes at the substrate periphery. An approach for EMI mitigation by stitching multiple ground planes together along the periphery of multilayer PCB power-bus stacks with closely spaced vias is reported and quantified in this paper. Power-bus noise induced EMI and coupling from the board edges is the major concern herein. The EMI at 3 m for different via stitch spacing and layer thickness is modeled with the finite-difference time domain (FDTD) method. Design curves and an empirical equation are extracted from a parametric study to summarize the variation of the radiated EMI as a function of layer thickness and stitch spacing.

DC power-bus design using FDTD modeling with dispersive media and surface mount technology components

DC power-bus modeling in high-speed digital design using the finite-difference time-domain (FDTD) method is demonstrated herein. The dispersive character of the dielectric layers used in printed circuit board substrates is taken into account in this study. In particular, FR-4 is considered. The complex permittivity of the dielectric is approximated by a Debye model. A wide-band frequency response (100 MHz-5 GHz) is obtained through a single FDTD simulation. Good agreement is achieved between the modeled and measured results for a typical dc power-bus structure with multiple surface mount technology (SMT) decoupling capacitors placed on the printed circuit board (PCB). The FDTD method is then applied to investigate some general approaches of power-bus noise decoupling.

Internal node probing of a DRAM with a low-temperature e-beam tester

In order to measure signals on internal nodes of circuits operated at liquid-nitrogen temperature, all electron-beam (e-beam) tester has been modified to cool circuits to this temperature during test. This apparatus has made it possible to measure signals on internal nodes of a high-speed DRAM operated at low temperature. The waveforms, which cannot be measured by other methods, provide the only means of determining the internal operation of the circuit. The instrument is described, and measurements of some critical DRAM signals are presented. In particular, the constancy of the bit-line equalization level, is shown, and observations of the interrelationship between power supply voltage, power bus noise, access time, and temperature are reported. >