Back-off Power Level Research Articles

Asymmetric Doherty power amplifier design considering the effects of peaking power amplifier early conduction

During the design of a Doherty power amplifier (DPA), the phenomenon of peaking PA turning on in advance is commonly observed. This is mainly due to the feedback of the main PA signal to the gate of the peaking PA through the gate-drain feedback capacitor, which results in an increase in its gate voltage. As a result, the overall efficiency of the back-off region is significantly reduced. This paper first describes the phenomenon of peaking PA turning on in advance. The formula for the voltage (referred to as the feedback gate voltage, FGV) imposed on the gate of the peaking PA by the main PA signal is then deduced. On this basis, the FGV is analysed numerically. For verification, an asymmetric DPA with a 9 dB output back-off (OBO) power level is designed and fabricated in this paper using GaN CGH40010F and CGH40025F transistors. According to the measurement results, the saturated drain efficiency of the DPA is 53.5%–63.3% in the 0.75–1.25 GHz band, the efficiency at the 9 dB OBO level is between 45.5%–54%, and the saturated output power is between 45 dBm–45.7 dBm, with a saturation gain of more than 8 dB.

Inverted sequential load-modulated balanced amplifier for extending dynamic power range over wide bandwidth

This paper propose an inverted sequential load-modulated balanced amplifier (ISLMBA) for extending the dynamic power range of a power amplifier (PA) over a wide bandwidth. The proposed ISLMBA consists of a control amplifier (CA) and a balanced PA (BPA) pair. A composited impedance inverter is inserted between each BPA transistor and the output coupler. The composited impedance inverter is composed by the intrinsic elements and output matching network (OMN) of the BPA transistor. In this way, the intrinsic elements can be fully absorbed into the impedance inverter over a wide bandwidth. Meanwhile, the load modulation trajectories of the BPA transistors can be optimized over a wide bandwidth by tuning the characteristic impedance of the impedance inverter. The theoretical current, voltage and load-modulation profiles of the ISLMBA are comprehensively analyzed. It is illustrated that the proposed ISLMBA could maintain high efficiency at deep output back-off power level over a wide bandwidth. Moreover, this work designs and fabricates an ISLMBA operating over 1.3–2.55 GHz to verify the proposed PA architecture. The fabricated ISLMBA exhibits a saturation drain efficiency (DE) of 54.5%–73.8% and a saturation output power of 42.9–45.9 dBm. At the same time, the fabricated ISLMBA achieves a 10 dB back-off DE of 42.1%–63.9% over the frequency band of interest. When the fabricated ISLMBA is stimulated by a 20 MHz wideband signal with a peak-to-average power ratio (PAPR) of 10.2 dB at 2.0 GHz, the measured adjacent channel leakage ratios (after predistortion) are −47.7 and −48.8 dBc at the lower and upper bands, respectively.

A Wideband and Highly Efficient Circulator Load Modulated Power Amplifier Architecture

A complete theoretical analysis is presented for a highly efficient power amplifier (PA) architecture based on a non-reciprocal combiner. The architecture consists of two amplifier branches and a microwave circulator acting as the output combiner, referred to as the circulator load-modulated amplifier (CLMA). The continuous-mode (CM) design technique has been further exploited for the CLMA to demonstrate the wideband capabilities of the architecture. The analysis reveals that the CLMA performs active load modulation to maintain high PA efficiency performance across a wide bandwidth and large output power dynamic range. As a proof of concept, a CLMA demonstrator circuit based on gallium nitride (GaN) transistors and a microwave circulator, is designed and characterized with continuous-wave and modulated-signal measurements. The implemented CLMA prototype circuit experimentally demonstrates Doherty-like efficiency enhancement over a large bandwidth covering 2.1 to 3.5 GHz. In measurements, the prototype exhibits a drain efficiency of 46.7-57.5% at peak output power and 35.6-50.6% at 7-dB output power back-off level, within the design bandwidth. When tested with a 60-MHz multi-carrier orthogonal frequency-division multiplexing (OFDM) signal having a 7-dB peak-to-average power ratio (PAPR), an average efficiency of 48.5% with better than <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula> 47.5-dBc adjacent channel leakage ratio (ACLR) is achieved after applying digital pre-distortion (DPD).

A High-Relative-Bandwidth Doherty Power Amplifier with Modified Load Modulation Network for Wireless Communications

This paper presents a novel load modulation network to realize a broadband Doherty power amplifier (DPA). The proposed load modulation network consists of two generalized transmission lines and a modified coupler. A comprehensive theoretical analysis is carried out to explain the operation principles of the proposed DPA. The analysis of the normalized frequency bandwidth characteristic shows that a theoretical relative bandwidth of approximately 86% can be obtained across a normalized frequency range of 0.4-1.0. The complete design process that allows the design of the large-relative-bandwidth DPA based on derived parameter solutions is presented. A broadband DPA operating between 1.0 GHz and 2.5 GHz was fabricated for validation. Measurements demonstrate that the DPA can deliver an output power of 43.9-44.5 dBm with a drain efficiency of 63.7-71.6% in the 1.0-2.5 GHz frequency band at the saturation level. Moreover, a drain efficiency of 45.2-53.7% can be obtained at the 6 dB power back-off level.

A Ka-Band Watt-Level High-Efficiency Doherty Amplifier MMIC in 90-nm GaAs Technology

This letter presents a Ka-band watt-level high-efficiency Doherty power amplifier (DPA) monolithic microwave integrated circuit (MMIC) in 90-nm gallium arsenide (GaAs) pseudomorphic high-electron-mobility transistor (pHEMT) technology. To realize the high efficiency of DPA at 6-dB power back-off (PBO), a low-loss compact Doherty output network is proposed to directly combine the matching network and the load modulation network (LMN) into a compact network. Then, the peaking amplifier of DPA is an optimized design to guarantee a sufficient load modulation at the 6-dB PBO level. The proposed DPA exhibits a measured saturation output power in the range of 29.5–30 dBm, with a corresponding peak power-added efficiency (PAE) in the range of 35%–40% from 26.5 to 30.5 GHz. Moreover, the PAE at the 6-dB PBO level of the proposed DPA is in the range of 25%–30.2% from 26.5 to 30.5 GHz.

Miniaturized Broadband Doherty Power Amplifier Using Simplified Output Matching Topology

This paper presents a Doherty power amplifier (DPA) with reduced size and wide bandwidth by using a simplified output matching topology. In broadband DPA designs, post-matching networks are usually added after the combing node, which usually occupy large circuit sizes. However, in this design, the post-matching network is not used. Instead, two ideal transformers and specific output matching components are employed at carrier and peaking branches. Then, by rearranging the output matching components in the two branches, Norton transformation can be used and the ideal transformers can be eliminated. In this way, the impedance at the combining node is directly matched to a 50- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Omega $ </tex-math></inline-formula> load without using a post-matching network, resulting in both compact size and wide bandwidth. For verification, a broadband DPA prototype with a very simple structure is implemented. The fabricated circuit shows a compact size. A wide bandwidth from 1.3 to 2.8 GHz (73%) is achieved with a saturated output power of 41.4–44.6 dBm. The drain efficiencies at saturation and 6-dB back-off power level are 60.1–79.1% and 41.8–61%, respectively, which are comparable to those of state-of-the-art designs.

A 37-GHz Asymmetric Doherty Power Amplifier With 28-dBm P sat and 32% Back-Off PAE in 0.1-μm GaAs Process

In this article, the analysis, design, and development of a 37-GHz asymmetric Doherty power amplifier (DPA) are presented. In a practical DPA, the main power amplifier (PA) shows nonideal characteristic, which varies the effect of the load modulation. Based on the theoretical analysis, we derive the relationship among the efficiency, power back-off (PBO) level, and the corresponding load impedance in a nonideal load modulation. The result suggests that a Class-AB main PA shows a decreased PBO efficiency during the load modulation. To achieve a good compromise between PBO level and PBO efficiency of the main PA, the load modulation scheme is redesigned in this work. A 2-dB PBO of the main PA is chosen to maintain the high efficiency during the load modulation. An asymmetric DPA topology is employed to compensate the inadequate PBO of the main PA so that a desired 6-dB PBO is achieved. Generally, the RF leakage at the DPA output degrades its performance. To solve this issue, we propose a modified low characteristic impedance DPA output network. The output matching network of the auxiliary PA is particularly designed to enlarge its output impedance. Through these design techniques, the leakage loss is significantly reduced to 0.2 dB, which improves the gain and power-added efficiency (PAE) at PBO. To validate the proposed techniques, a DPA chip is designed and fabricated in a D-mode 0.1- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> GaAs pHEMT process. At 37 GHz, the 1.6 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times1.8$ </tex-math></inline-formula> mm integrated chip exhibits a measured small-signal gain of 15.6 dB and a saturated power ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$P_{\mathrm{sat}}$ </tex-math></inline-formula> ) of 28.0 dBm, with an associated 33.2% peak PAE and a 32.0% PAE at 6-dB PBO. To the best of our knowledge, the proposed chip exhibits the state-of-the-art overall performance among DPAs operating around 37 GHz for 5G n260 millimeter-wave (mm-wave) band.

A Generic Theory for Design of Efficient Three-Stage Doherty Power Amplifiers

An analytical load—pull-based design methodology for three-stage Doherty power amplifiers (PAs) is presented and demonstrated. A compact output combiner network, together with the input phase delays, is derived directly from transistor load—pull data and the design requirements. The technique opens up a new design space for three-stage Doherty PAs with reconfigurable high-efficiency power back-off levels. The method is designed to enable high transistor power utilization by maintaining full voltage and current swings of the main and auxiliary amplifier cells. Therefore, a wide efficiency enhancement range can be achieved also with symmetrical devices. As a proof of concept, a 2.14-GHz 30-W three-stage Doherty PA with identical gallium nitride (GaN) HEMT active devices is designed, fabricated, and characterized. The prototype PA is able to linearly reproduce 20-MHz long-term evolution signals with 8.5- and 11.5-dB peak-to-average power-ratio (PAPR), providing average efficiencies of 56.6% and 46.8% at an average output power level of 36.8 and 33.8 dBm, respectively. Moreover, an average efficiency as high as 54.5% and an average output power of 36.3 dBm have been measured at an adjacent power leakage ratio of −45.7 dBc for a 100-MHz signal with 8.5 dB of PAPR, after applying digital predistortion linearization.

Frequency analysis of load modulation networks for asymmetric Doherty power amplifiers in GaN

AbstractThis paper investigates the frequency response of load modulation networks for asymmetric Doherty power amplifiers (ADPA) with an output back-off power level larger than 6 dB and a power ratio of peak to main amplifier (N − 1) larger than 1. The influence of the main path impedance transformer (IT) on the Doherty impedances at main and peak path as well as on the ADPA's efficiency is analyzed. Scaling of the main IT's characteristic impedance via ξ indicates a maximum broadband matching for an input voltage Vin of ξ · Vin,max. By weighting the frequency- and ξ-dependent efficiency curves using a probability density function (PDF), an optimum is obtained for ξ = 1/N. To verify the theory, three ADPAs with different ξ-scaled ITs are designed, measured, and compared. For the design at 3.6 GHz, a gallium nitride (GaN) transistor is used. By means of the intrinsic node matching technique, matching at the current source plane is obtained. In laboratory measurements, the ADPA with ξ = 1/N achieves a power-added efficiency (PAE) of 63% at 42 dBm output power and a PDF-weighted average PAE of 38.8% within 400 MHz bandwidth for 8 dB peak-to-average power ratio. Comparison with similar state-of-the-art ADPAs in GaN technology shows highest PAE and operation power gain GP for center frequencies larger than 3.0 GHz.

확장된 백오프 출력에서 고효율 동작을 위한 최적화된 대칭 이단 도허티 전력 증폭기 설계

This article presents a symmetric two-stage Doherty power amplifier (DPA) for the extended output power back-off level, which can be attained even with a reduced circuit size by changing the output impedance of the peaking amplifier to be inductive without the offset line. The ABCD matrix is employed to design the output matching network of the peaking amplifier with a simple transmission line. Consequently, we can reduce the design complexity by applying the same circuit to the carrier amplifier as the DPA is symmetric. To deal with reduced output power of the class-C peaking amplifier, a two-stage DPA structure was applied. The power amplifier exhibited a drain efficiency (DE) of 63.5 %, and a power added efficiency (PAE) of 50.6 % at 7.5 dB output backoff was obtained using the 3.5 GHz pulsed continuous wave (CW) signal. Furthermore, a DE of 53.3 %, a PAE of 43.2 % and a power gain of 18 dB were obtained at the power level of 41 dBm using a 20 MHz LTE signal with a peak-to-average power ratio of 7.5 dB.

A Monolithically Integrated Single-Input Load-Modulated Balanced Amplifier With Enhanced Efficiency at Power Back-Off

In this article, the design of a power amplifier (PA) using a simple but effective architecture, namely, load-modulated balanced amplifier (LMBA), is presented. Using this architecture for PA design, it can achieve not only a relatively high saturated output power but also an excellent efficiency enhancement at the power back-off (PBO) region. To prove that the presented approach is feasible in practice, a PA is designed in a 1- μm gallium arsenide (GaAs) HBT process. Operating under a 5-V power supply, the PA can deliver more than 31-dBm saturated output power with 36% collector efficiency (CE) at 5 GHz. Moreover, it also achieves 1.2 and 1.23 times CE enhancement over an idealistic Class-B PA at 6- and 9-dB PBO levels, respectively. Finally, the designed PA supports 64-quadrature amplitude modulation (QAM) with 80 Msys/s at 22-dBm average output power while still maintaining an error vector magnitude (EVM) and adjacent channel power ratio (ACPR) better than -29.5 dB and -29.4 dBc, respectively.

Design and Analysis of Continuous-Mode Doherty Power Amplifier With Second Harmonic Control

While continuous-mode Doherty power amplifier (CM-DPA) can achieve high efficiency at output back-off (OBO) power levels, their achievable bandwidth and load modulation have not yet been fully investigated. This brief reveals that the bandwidth of CM-DPA is limited by the impedance trajectories of the peaking transistors. In particular, the peaking transistor degrades the bandwidth in the high power region and limits the fractional bandwidth (FBW) of the CM-DPA. Moreover, based on post-matching Doherty architecture, an analytical method for harmonic control in CM-DPAs is presented. A broadband CM-DPA with harmonic control is implemented, fabricated and measured. The CM-DPA delivers a saturation output power (Psat) of 42.6–44.4 dBm from 1.50 to 2.55 GHz, i.e., FBW of 51.8%. The drain efficiencies in the interested frequency band are 50.7%–69.7% and 43.3%–57% at the Psat and 6-dB OBO power levels, respectively.

Multi-port Active Load Pulling for mm-Wave 5G Power Amplifiers: Bandwidth, Back-Off Efficiency, and VSWR Tolerance

The opening of spectral bands in the millimeter-wave (mm-Wave) spectrum from 26 GHz and extending up to the E-band poses new challenges to the power amplifier (PA) design for spectrally agile radios. They are expected to operate with high energy efficiency at peak and back-off levels to process signals with high peak-to-average power ratio (-.10 dB), while being able to maintain their performance across a wide range of 5G bands. In addition, the PAs can experience strong load impedance mismatch conditions in a user equipment (TIE) that pose additional challenges in handling strong voltage-standing-wave-ratio (VSWR) events. In this article, we present a systematic approach to exploit active load pulling in a multi-port network that synthesizes optimal impedance conditions for 1) broadband peak and back-off operation and 2) mitigating VSWR events at peak power. As proofs of concept, we present two PAs in 65-nm bulk CMOS process. The first chip demonstrates Psat between 16.3 and 19.3 dBm across 37-73 GHz, with an improvement in the output drain efficiency (ηout) of up to 3.2×/5.8× at 6-/9.6-dB power back-off (PBO) across the frequency range compared to class-A operation. The second chip achieves 26-42-GHz Psat, ...1 dB bandwidth with Psat > 19 dBm and PAEpeak > 20% across all 28-40-GHz bands and with up to 3.35× and 4.84× enhancement in PAE at the PBO levels of 6 and 9.6 dB over class-A operation, respectively. The PA also demonstrates strong tolerance to VSWR events with only 2 dB degradation over a VSWR 4:1 load circle at a frequency of 33 GHz.

A high-efficiency Doherty Power Amplifier for wireless base stations

ABSTRACT This paper presents a new high-efficiency two-way Doherty Power Amplifier (DPA) with a modified output matching structure for Wideband Code Division Multiple Access (W-CDMA) low-to-medium power base station applications. A blended design is proposed using the symmetrical topology of equal rated power amplifying devices with unequal output impedances for the carrier and peaking amplifier to achieve enhanced efficiency and desired linearity in 1900 MHz band. The proposed output circuit modifications encompass the usage of parasitic capacitor compensation technique for the carrier amplifier, optimum offset line along with the Doherty combiner to achieve high efficiency over 6 to 10 dB extended range of back-off operation. The measured results of the DPA demonstrate a Power Added Efficiency (PAE) of more than 49.9% at +34 dBm W-CDMA signal power, which is between 8 and 8.5 dB back-off from the peak power level of 42.2 dBm. The DPA has a large signal power gain of 13 dB at 1960 MHz. Further, the PAE is 39.5% and linearised Adjacent Channel Power Ratio (ACPR) is −46.2 dBc, both at 10 dB back-off from peak power. In these back-off power levels, this implementation provides significant efficiency improvement using symmetrical devices and with excellent linearity.

A 28-GHz Beamforming Doherty Power Amplifier With Enhanced AM-PM Characteristic

This article presents a beamforming Doherty power amplifier (B-DPA) for the 28-GHz fifth-generation (5G) new-radio band. The proposed B-DPA is based on a new combiner topology that allows the current profile in the auxiliary branch of the DPA to be relaxed while simultaneously canceling the amplitude-to-phase (AM-PM) distortion exhibited in the active devices. This approach enables efficiency and linearity enhancements. In addition, the DPA is augmented with high-accuracy digitally assisted vector multipliers at its input stage to provide the required relative and absolute phase adjustments for proper Doherty operation and the overall phase shift required for beamforming. A proof-of-concept prototype was implemented in the 45-nm silicon on insulator (SOI)-CMOS technology. Measurement results reveal that the proposed B-DPA demonstrated good Doherty operation with drain efficiencies of 18%–20% and 33%–35% at 6-dB back-off and saturation power (Psat, 18 dBm) levels, respectively, between 28 and 30 GHz. In particular, excellent AM-PM characteristics were noted with a peak value of only 1.5° up to Psat, which remained below 2.5° as the B-DPA was swept with a 0° to 360° phase shift. Finally, modulated-signal tests revealed error vector magnitudes of 3.1% and 0.9% for 4-MHz $\times100$ -MHz orthogonal frequency division multiplexing (OFDM) signals before and after applying digital predistortion, respectively.

Design of continuous mode Doherty power amplifiers using generalized output combiner

In this paper, a continuous mode Doherty power amplifier (DPA) working over an octave bandwidth is constructed using a generalized combiner. The generalized combiner provides the PA designers with more freedoms for realizing broadband DPAs. Theoretically, the generalized combiner could expand the working bandwidth of continuous mode DPA. A continuous mode DPA working over 1.2–2.7 GHz (a relative bandwidth of 76.9%) is implemented in this contribution for demonstrating the universality of the generalized combiner. As a demonstrator circuit, the fabricated DPA achieves drain effciencies of 40–54% and 44–75% at 6 dB back-off and saturation power levels, respectively. The maximum output power of the fabricated DPA is 42.1–44.2 dBm with a saturation gain of 7.2–11.3 dB over 1.2–2.7 GHz. When the designed DPA is excited by a 20 MHz LTE signal with a peak to average power ratio of 7.04 dB, the fabricated DPA achieves adjacent channel leakage ratios (ACLRs) of −29.5 dBc and −49.5 dBc at 2.4 GHz before and after DPD technique, respectively.

Analysis and Design of Outphasing Transmitter Using Class-E Power Amplifiers With Shunt Capacitances and Shunt Filters

In this paper, a novel outphasing power amplifier (PA) based on class-E amplifiers with shunt capacitances and shunt filters is proposed. The new design provides high drain efficiency for both peak and back-off power levels. A mathematical model for the class-E power amplifier with shunt capacitance and shunt filter is presented. The proposed model enables derivation of load circuit parameters that provide optimum drain efficiency for the peak and back-off power levels using closed form mathematical expressions. Based on this model, an outphasing power amplifier is designed and subsequently implemented using microstrip transmission lines and a GaN HEMT devices. The fabricated power amplifier prototype is optimized for 2.14 GHz and provides drain efficiency of over 60% for back-off power levels up to 8.5 dB. The amplifier demonstrates a 44.3% drain efficiency for 64QAM OFDM modulated signal with 20 MHz bandwidth. Adjacent channel leakage ratio (ACLR) of −39.5 dB and error vector magnitude (EVM) of 0.9 % were achieved after the application of a memory polynomial linearization algorithm.

A Dual-Fed PIFA Antenna Element With Nonsymmetric Impedance Matrix for High-Efficiency Doherty Transmitters: Integrated Design and OTA-Characterization

A single planar inverted F-antenna is proposed employing two input ports to optimally power-combine the output signals of two nonlinear power amplifiers inside the metal-only low-loss antenna structure. High power-added efficiency (PAE) at back-off power levels is reached through a Doherty combiner architecture, where the optimal power combination is seen to generally require the synthesis of a nonsymmetric antenna input impedance matrix. The dual-fed antenna is compact and exhibits close to single-mode radiation properties; it has a relatively stable gain pattern despite the nonequal Doherty power amplifier (PA) output powers. An integrated active prototype has been designed, fabricated, and characterized over-the-air in both an anechoic and a reverberation chamber. Good agreement is observed and an uncertainty analysis is performed. The Doherty transmitter features a max-PAE of 58% at 2.14 GHz and a 6 dB back-off PAE of 52%; a minimum system power gain of 9.5 dB (max 12 dB); and a maximum system output power of 43.5 dBm.

Broadband Doherty Power Amplifier With Transferable Continuous Mode

In this paper, in-band continuous mode transferring (CMT) method is presented for designing broadband Doherty power amplifier (DPA). Specifically, transferable continuous mode, transferring between class-J continuum to class-F <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> continuum, is introduced into DPA at output back-off (OBO) power level for improving bandwidth and efficiency. For validation, a broadband DPA with operation mode transferring from continuous class-J to continuous class-F <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> is designed, fabricated and measured. Experimental results show the drain efficiencies (DEs) of the fabricated DPA are 46.3%-57.7% and 58.4%-69.1% at 6 dB OBO and peaking power levels over 1.7-2.6 GHz. The saturation power of this DPA is 43.1-45.2 dBm with a gain of 9.1-11.2 dB in the interested band. Furthermore, when the fabricated DPA is stimulated by a 20 MHz wideband signal with a peak-to-average power ratio (PAPR) of 7.05 dB at 2.4 GHz, the measured average power is 36.5 dBm with an average DE of 45.7%, and the measured adjacent channel leakage ratios (ACLRs) are -31.9 dBc and -50.4 dBc before and after DPD technique, respectively.

Co-Design of Matching Sub-Networks to Realize Broadband Symmetrical Doherty With Configurable Back-Off Region

In this brief, a technique using the co-design of three matching sub-networks is proposed to solve the contradiction between bandwidth and extended the back-off region of symmetrical Doherty power amplifier (DPA). The phase-shifting solution space of DPA output matching networks is calculated, and its relationship with the input impedance of the post-matching network is analyzed with and without the frequency variable. Configurable back-off region and adjustable operating center frequency can also be realized in the design by using the proposed method. The design flow is given, and then a detailed example under 9-dB back-off region is presented. To verify the proposed theory, a DPA is designed and fabricated across 1.9-2.4 GHz. The experimental results show drain efficiencies of 44.2-49.7% at 8.5-9 dB output power back-off levels across 1.9-2.4 GHz. The fabricated DPA achieves output powers of 44.1-44.8 dBm.