The modern processor requires multiple dedicates, fully pipelined architecture uses instructional level parallelism. So, this pipeline is very important in it. The proposed system is implemented using the fully pipelined architecture FPU in FPGA’s. Square root and division have many complications in DSP but it is important to implement in FPGA because it is so tough. Some of them will not implement the add and multiply components when compared to the slow or large which will match the real time applications. In every clock cycle, pipeline should have the capability of accepting the square root and divider. In single precision floating point Verilog code is written and implemented using spartan 6 FPGA for sqrt/division. The operation latency and issue rate have 18 clock cycles and 15 clock cycles. It uses many adders/subtractors in other high pipelined implementations. The operation latency and issue rate have 15 clock cycles and 1 clock cycles. It reduces power dissipation. It has some advantages like area utilization will be less and latency bound.